HY3118/HY3116 Datasheet

HY3118/HY3116
24-Bit Analog-to-Digital Convert
High Resolution Σ∆ADC
9.4. Input Channel Multiplexer with IRQ
• Flexible input multiplexer for measurement
and reference signal
• Network switchable input multiplexer
design and ADC conversion data
suppression function
• Steady time calculation for ADC
conversion data suppressed output
• Response IRQ function for end of ADC
data conversion
Measurement signal input network
.
Reference voltage input network
Figure 23 Input Channel Multiplexer
Signal input is featured with flexible network switchable multiplexer design. After
the input network controller is switched, the embedded data conversion suppressor is
initiated to delay data update in ADO[23:0] register until ADC data conversion is
completed. The data update steady time can be derived from the equation described
below:
t
ADC
Stable
1
128
4
f
ADC
OSCS
1
f
…………………………………………….. (Formula 1)
ADC
OSR
tStable
: steady time after ADC network switch
ADC
fOSCS
: ADC sampling frequency
ADC
fOSR
: ADC conversion frequency
If IRQEN of ADC4[7:0] is set to “1”, then a piece of data will be written into
register ADO[23:0] and an IRQ signal will be generated at SDA pin. The IRQ signal is a
low potential pulse signal that triggers the master end to read contents in ADO[23:0]
after being received at the master end.
Please note that after configuration of the input channel multiplexer is switched,
both the +/- input short or exchange and reference voltage change need a period of
ADC
t before the ADC can generate valid conversion data or interruption response IRQ.
Stable
ADC
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www.hycontek.com
DS-HY3118- V08_EN
Page 34