HY3118/HY3116 Datasheet

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HY3118/HY3116 24-Bit Analog-to-Digital Convert High Resolution Σ∆ADC i. Write Register then Read Register j. IRQ Read Register k. Call Chip Reset . © 2011-2014 HYCON Technology Corp www.hycontek.com DS-HY3118- V08_EN Page 24
HY3118/HY3116 24-Bit Analog-to-Digital Convert High Resolution Σ∆ADC SCL LINE SDA LINE Figure 10 Valid Data Wave Form of Communication I 2 C . Figure 11 Start and End Wave Form of Communication I 2 C *1 When the 8 th -clocking SCL signal is sent from the mater to the slave end, the master’s SDA pin must change from output to input status for receiving the ACK signal sent by the slave end. When the slave end is set up with ADC IRQ interruption signal, the master’s SDA pin must set to input status for receiving the IRQ low potential pulse signal sent by the slave end. Figure 12 ACK Wave Form of Communication I 2 C © 2011-2014 HYCON Technology Corp www.hycontek.com DS-HY3118- V08_EN Page 25
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HY3118/HY3116 Datasheet

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