Analysis and design of a 200W LDMOS based doherty amplifier for ...

WE5A-3
Analysis and Design of a 200W LDMOS Based
Doherty Amplifier for 3G Base Stations
John R. Gajadharsing, Olof Bosma*, and Pim van Westen*
Philips Semiconductors, BU Mobile Communications, Nijmegen, The Netherlands
*MAP, Meerlaan 21, 1671 ED, Medemblik, The Netherlands
Abstract - In tbis paper the analy& and design of a
2OOW classical Doherty amplifier is described using dlscrete
LDMOS devices. The peak (class-C) and main (class-AB)
amplifiers are desigbed with two stages to obtain flat AM-
AM and AM-PM charPCteristics for the Doherty amplifier.
An asymmetrical planar coupler structure is uWed as an
input splitter and microship based elements are used for
phase matching and power combloing at the output. Thh
Doherty PA has a measured PldB of 53dBm and exhibits an
efiiciency of 34% at 6dB backoff (47") for two-carrier
WCDMA. The ACPR and IM3 obtained at 47dBm are 37dBc
and 33dBc respectively. The gain at 6dB backoff is ZZdB over
the frequency range 2.11-2.17GHz Design considerations for
a Doherty ampMer based on discrete LDMOS devices are
addressed.
Index terms - Doherty, LDMOS, AM-AM, AM-PM,
WCDMA, power amplifiem
I. INTRODUCTION
In contemporary base stations amplifier designs for
WCDMA, one of the main concerns is the power
consumption. Due to the linearity requirements the
operating point of these amplifiers are constrained to the
backdff region where it is not most efficient. Although
we can still expect to see @proved backoff efficiency
through advancement in device technology it is
theoretically limited. The Doherty amplifier is a technique
for improving the efficiency of backed-off amplifiers
beyond the limits of conventional amplifiers.
In this paper we will discuss a 200W amplifier design
for WCDMA that has a significantly improved efficiency
in the backoff region using discrete LDMOS devices.
(PAZ) amplifier, typically biased in class AB and C
respectively, with their outputs connected by an
impedance inverter, usually a quarter-wave transmission
line. The delay introduced by this N4 line is compensated
by a N4 delay in the input path to PA2 to ensure that the
correct phase relationship is restored.
Input 4
Peak
"DD
Fig. 1 Topology of a two stage Dohem.
The amplifiers operation is well described hy Raab [2]
In essence an active load-pulling effect is created as each
amplifier tums on at different power levels. The two-stage
Doherty amplifier therefore exhibits two efficiency
peaking points. The power range over which high
efficiency can be obtained depends on the peak power
ratio of the main and peak amplifier in a two-stage
Doherty [2]. If we assume that the amplifiers utilized, are
ideal class-B devices and that the Doherty amplifier is
operating into a resistive load, a general set of equations
can be derived for the currents, power levels and
efficiency as function of the output voltage:
11. Two STAGE DOHERR &VIEW
The Doherty amplifier is a technique for improving the
efficiency of backed-off linear amplifiers. In a Doherty
amplifier, the output powers of two amplifiers operating at
a proper phase alignment and bias level, are combined
using appropriate power combining techniques [l]. The
topology of this so called two-stage Doherty amplifier is
shown in Figure 1. It consists of a main (PAl) and peak
0-7803-8331-1/04/$20.00 Q 2004 IEEE
529
2004 IEEE MTT-S Digest

The individual power levels as indicated in Fig.] are
plotted (4)

e lost when the Doherty amplifier is operating below its
transition point. It is therefore necessary to add a driver
stage to maximize efficiency. A driver is also added to the
main amplifier to accommodate shaping of the transfer
characteristics, which is critical in a Doherty amplifier.
The splitter asymmetry (A) is set by the gain difference:
A=G,-G, (9)
The gain of the total Doherty amplifier, at full power, can
then be determined from:
Gm, - 3 +GI - IOlog(l+ (10)
In order to maintain a constant gain over power for the
total Doherty amplifier, the gain characteristics (AWAM)
of the peak amplifier should be matched to that of the
main amplifier, and,can be determined from:
G, = 101og(lO"'lo(l+ IOd~~o)-lOG1po)- A (1 1)
The amplifiers are designed using internally matched
Philips LDMOS transistors. In order to get maximum
efficiency improvement in a Doherty amplifier the
transistors need to have specific properties. The transistor
for the peak amplifier should he designed to have a high
off-state output impedance and exhibit low reverse RF
drive. For the main amplifier the transistor should he able
to provide maximum performance under the load pulling
conditions.
The implementation of the two-stage class-AB main
amplifier, using two BLF2022-40 (5OWpeak) in the final
stage and one BLF2043(10W) in the driver stage, is
shown in Fig. 5. The final stage devices are paralleled
without using a quadrature combiner, since both
transistors must experience in-phase load-pulling for
Doherty operation. The interstage matching is designed to
meet the bandwidth requirement of 60MHz and to obtain
approximately 3dB compression required for Doherty
operation.
Fig. 5. Class-AB main amplifier implementation.
The resulting M AM and AMPM characteristics for a
50n load are shown in Fig. 6 with a peak power capability
of 1oow.
Poldhl
Fig. 6. AM-AM and AM-PM characteristics of the class-AB
main amplifier for a 5011 load:
The implementation of the two-stage class-C peak
amplifier is shown in Fig. 7. It utilizes two BLF2022-40 in
the final stage and one similar device in the driver stage.
The interstage circuit not only provides impedance
matching but also the correct phase matching between the
driver output and final stage input in order to obtain a
predistortion effect that aligns the M AM and AM/PM
characteristics of the peak amplifier with main amplifier.
The resulting M AM and AWM characteristics for a
50n load are shown in Fig. 8 with a peak power capability
of 1oow.
Fig. 7. Class-C peak amplifier implementation.
X I I I I I I I -,&a
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a11 21 zs a U 24 xi Y U) e " 48 4a a U
hldbl
Fig. 8. AM-AM and AM-PM characteristics of the class-C peak
amplifier for a 5On load.
Fig. 9 shows the circuit diagram of the total Doberty
implementation. The transmission lines TL3 and TL4 are
used to maximize overall efficiency. TL3 provides the
phase matching to rotate the off-state impedance of the
peak amplifier to a high impedance level at the combining
point between TL5 and TL6. TL4 provides the phase
matching to ensure that a resistive load of twice the
nominal value is presented at the die level of the main PA
transistors. The input utilizes an asymmetrical (5dB)
branch line coupler as a splitter. TLl and TJ2 are added to
53 1

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ensure that the output arrive in phase at the combining
point.
IM3 obtained at 47dBm are 37dBc and 33dBc
respectively. The gain at 6dB back-off is 22dB over the
frequency range 2.11-2.17GHz.
x1
21:
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.............
Fig. 9. Schematic of the Dohaty implementation.
SCC
c
The AMIAM and AM/F’M characteristics of the total
Doherty system are shown in Fig. 10. The contribution of
the peak amplifier becomes significant above 48dBm.
4 10
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P : ::
137
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-10
-3s
a
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Fig. IO. AM-AM and AM-PM characteristics of the total
Doherty amplifier.
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Y a I
U,., 47 50 53
Fig. 11. CW gain and efficiency of the total Doherty amplifier at
t 2.14GHz.
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