PUBLICATIONS and TALKS of J.S. Tsai - Nec
PUBLICATIONS and TALKS of J.S. Tsai - Nec
PUBLICATIONS and TALKS of J.S. Tsai - Nec
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US Patent 7145170B2, “COUPLED SUPERCONDUCTING CHARGE QUANTUM BIT DEVICE<br />
AND CONTROLLED-NOT GATE USING THE SAME”<br />
J.S <strong>Tsai</strong>, T. Yamamoto, Y. Nakamura, registered 12/05/06<br />
US Patent 7443720B2, “METHOD AND CIRCUIT FOR READING QUANTUM STATE”<br />
J.S <strong>Tsai</strong>, Yu. Pashkin, O. Astafiev, registered date 10/28/08<br />
Japanese Patent H11-277907, “NONVOLATILE MEMORY”<br />
J.S <strong>Tsai</strong>, T. Yasui, Y. Nakamura, J. Sone, Y. Ootsuka, registered 1/6/09<br />
Japanese Patent H14-370135, “QUANTUM LOGIC GATE AND ITS OPERATION”<br />
J.S <strong>Tsai</strong>, T. Yamamoto, registered 12/19/09<br />
Japanese Patent H15-286640, “COUPLED SUPERCONDUCTING CHARGE QUANTUM BIT<br />
DEVICE AND CONTROLLED-NOT GATE USING THE SAME”<br />
J.S <strong>Tsai</strong>, T. Yamamoto, Y. Nakamura, registered 6/9/10<br />
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