ncr/doc/RealPOS/7454/Technical_Manuals/7454_Re... - Alsys Data

Technical Note 

NCR 7454 MSR Hardware Interfaces 

NCR Corporation 

Retail Solutions Division 

Doc. Num: 497-0427389 Revision: A 

Issue Date: August 2002 

DLC Ref: 

Doc. Type: Technical Note 

Prepared By: 

Diane Nowakowski 

Luis Garcia-Verona 

The electronic version of this document is the revision-controlled copy. 

All printed copies are considered uncontrolled copies. 

NCR Corporation CONFIDENTIAL 

Copyright © 2002 

NCR Corporation 

Dayton, Ohio U. S. A. 

All Rights Reserved 

Confidential, Unpublished 

Property of NCR Corporation

SCER ATL1120 Date August 2002 497-0427389 

Technical Note Revision: A Page 2 of 16 

Please verify on-line that this is the latest revision 

Document Change Sheet 1 of 1 

Revision Date Description of Change 

A August 2002 Initial Release




Table of Contents 

1.0 OVERVIEW ........................................................................................................................................................... 4 

1.0 OVERVIEW ........................................................................................................................................................... 4 

2.0 MSR FIRMWARE/HARDWARE INTERFACES ............................................................................................. 4 

2.1 MEMORY AREA LAYOUT ................................................................................................................................ 4 

2.2 MSR TRACK DATA BUFFERS .......................................................................................................................... 5 

2.3 MSR TRACK DATA BYTE COUNTERS (0XF0, 0XF1, 0XF2)....................................................................... 6 

2.4 TRACK 2&3 F2F REGISTER (0XF3)................................................................................................................. 6 

2.5 ASIC OPERATIONAL MODE REGISTER (0XF4).......................................................................................... 6 

2.6 ASIC REV. REGISTER (0XF6) ........................................................................................................................... 7 

2.7 MSR COMMAND AND STATUS (C/S) REGISTER (0XF8) ........................................................................... 8 

2.7 MSR INTERRUPT RESET IRQ REGISTER (0XF9) ....................................................................................... 9 

2.8 ALTERNATE RAM CLEAR REGISTER (0XFA) ............................................................................................ 9 

3.0 FORMAT OF DATA ........................................................................................................................................... 10 

4.0 NCR 7454 MSR DRIVER (TAPS DRIVER) ..................................................................................................... 11




1.0 Overview 

The MSR is a memory-mapped device. The address is specified in the BIOS. The addresses 

available are CC000, CE000, and D0000. By default IRQ 15 is used for the MSR. On early 

models of the 7454/7401, this IRQ was not changeable. 

On the 7454-22xx/35xx terminals the IRQ is also definable in the BIOS. The default is 15 but 

other settings allowed are 5, 6, 7, 10, 11, and 15. 

The MS-DOS MSR driver for the 7454/7401 terminal, was written to have the user specify the 

MSR memory address (default is CC000). The IRQ was fixed at 15. 

NOTE: It is important that the BIOS setting and the address used by the software match. 

2.0 MSR Firmware/Hardware Interfaces 

The following interfaces were extracted from the firmware documentation for the 8051 

implementation of the Wedge/MSR hardware. This is the base for the ASIC implementation for 

the MSR hardware on the NCR 74XX terminal. 

2.1 Memory Area Layout 

The MSR software communicates via this memory-mapped area. A series of registers and data 

buffers are defined. The memory area is specified in the BIOS (CC000, CE000 or D0000). The 

layout of this area is: 

0x00 

Track 1 Buffer (length 96 bytes) 

Empty space 

0x80 

Track 2 Buffer (length 40 bytes) 

Empty space 

0xF0 Track 1 Byte counter 

0xF1 Track 2 Byte counter 

0xF2 Track 3 Byte Counter 

0xF3 Track 3 F2F / Track 2 F2F 

0xF4 ASIC Operation Mode 

Track 1 F2F / 

0xF5 Speaker Frequency




0xF6 

0xF7 

0xF8 

0xF9 

0xFA 

0xFB 

- 

0xFF 

0x100 

ASIC Rev Level / Speaker Volume 

Not used 

Command/ Status Register 

Reset IRQ (Write Only) 

TrackRam Clear/ Spkr ON/ unused 

Not Used 

Track 3 data (length 104 bytes) 

2.2 MSR Track Data Buffers 

Each track has a separate block of RAM to serve as a buffer for the data read from the MSR 

device. These tracks are controlled independently. Track 1 is 96 bytes in length, track 2 is 40 

bytes long and track 3 is 104 bytes. The MSR firmware has read and write access to the ASIC 

RAM buffers unless the corresponding track has been enabled (Tk[123] bit in C/S register is set 

to 1) and the Data Present bit is zero, meaning a swipe has not yet been completed. Each 

buffer is independently enabled/disabled for access. 

Prior to issuing each track read command to the internal MSR support hardware of the ASIC 

device, the RAM buffers must be cleared to ensure the integrity of the data being stored in the 

buffers during the next card swipe. 

When a card swipe is in progress, the Track 1, Track 2, and Track 3 RAM Buffers are filled with 

data by the internal MSR support hardware, starting at the lowest RAM buffer address (00h for 

track 1, 80h for track 2, 100h for track 3). If more data is received from a track than there is 

room in the buffer, a buffer overflow condition will occur. The appropriate overflow bit in the 

corresponding Data Byte Counter is used to indicate whether or not a buffer overflow condition 

has occurred. Additional incoming data on this track will be ignored by the MSR interface 

hardware. 

When an MSR card is read, the bytes are written into the buffer, the count is written to the Byte 

Counter offset. The fill value bit (see ASIC Operational Mode Register) indicates completion of 

the read.




2.3 MSR Track Data Byte Counters (0xF0, 0xF1, 0xF2) 

Read 

Overflow 

Unused 

in counter 

0xF1 

MSR Track Read Data Byte Counter (b0 - b6) 

b7 

b6 

MSR Track Data Byte Counters 

The MSR Track 1, Track 2, and Track 3 Data Byte Counters are used by the firmware to locate 

the last byte of data read from the MSR into the Track 1 , Track 2, and Track 3 RAM Buffers and 

to ascertain the number of bytes read on each track of the MSR device. The Data Byte 

Counters always contain the offset of the next location to be written by the reader. Thus, a value 

of zero indicates no data is present; a value of 01 indicates that 1 byte is present, and so forth. 

The high bit of each of the Data Byte Counters is an overflow flag. If more data bytes are read 

from the track than can fit in the buffer, the overflow flag bit is set, and the Data Byte Counter is 

set to its maximum value. 

The Track 2 Data Byte Counter is limited to 6 bits so for the counter at 0xF1 always has bit 6 set 

to zero. 

b0 

2.4 Track 2&3 F2F Register (0xF3) 

Track 3 Leading zeroes to ignore Unused Track 2 Leading zeroes to ignore Unused 

b7 b6 b5 b4 b3 b2 b1 b0 

Track 2&3 F2F Register 

The Track 2 and 3 F2F register is a tuning tool which sets the number of leading zeros to be 

ignored before data is accepted for an individual track. The default value is 62h. The track 1 

value is set in the ASIC Operational Mode Register, below. 

The default is used for the MS-DOS driver. 

2.5 ASIC Operational Mode Register (0xF4) 

Enable 

Reset Ram 

@Reg FA 

Enable 

Reset Ram 

@Reg F8 

Fill 

Value 

Track 1 Leading zeroes to ignore Auto- 

Recover 

Unused 

b7 b6 b5 B4 b3 B2 b1 b0 

ASIC Operational Mode




The ASIC Operational Mode register controls certain aspects of the ASIC MSR Read operations. 

Bits 5 to 7 contain the number of leading zero bits to ignore in the MSR bit stream. The value 

can range from 0 to 7. The hardware default is 3. This value provides a tuning parameter for 

more reliable reads, and is factory set by the firmware. 

The Auto-Recover bit, b4, when set to 1, instructs the ASIC to re-enable itself if it detects 

CLOCK but never receives valid data. This could occur from a swipe, which begins with a cardinsertion, 

a pause, then a swipe. The clock appears during the insertion, but no data appears. If 

the Auto-Recover bit is set to a one, then the ASIC will automatically re-enable itself during the 

pause. Otherwise, the ASIC will report a swipe complete with no data present, and the firmware 

must re-enable the ASIC. 

The Enable Reset Ram at Register FA bit, when set to 1, enables the circuitry which clears RAM 

when a zero is written to one (or more) of the Track Select bits in Register FA. When this bit is 

set to zero, Ram cannot be cleared through register FA. 

The Enable Reset Ram at Register F8 bit, when set to 1, enables the circuitry which clears RAM 

when a zero is written to one (or more) of the Track Select bits in Register F8. When this bit is 

set to zero, Ram cannot be cleared through register F8. 

The Fill Value bit contains the value to be used to fill any unused bits in the last byte of data read 

from each track. At the end of a card swipe, the last clocked bit of data may not exactly fill a 

byte. The last byte will be padded with the Fill Value contained in this Register. The bits read 

from the tracks are sequenced into memory in low-to-high bit order within bytes, so the fill bits 

will appear in the highest bits of the last byte. 

2.6 ASIC Rev. Register (0xF6) 

ASIC Revision Level 

Reserved 

b7 

b3 

b0 

ASIC Revision Register 

The revision level of the ASIC part is available to be read on bits b4 thru b7 of this register.




2.7 MSR Command and Status (C/S) Register (0xF8) 

The MSR support hardware of the ASIC device is controlled through the ASIC Operational Mode 

Register and the MSR C/S Register, mapped at data memory addresses 0xF4 and 0xF8, 

respectively. Through the C/S Register, the ASIC is able to monitor the status of the MSR 

hardware. 

The upper four bits of the MSR C/S Register are Command bits, used for sending a track read 

command to the MSR hardware, or masking an interrupt upon completion of a card swipe. The 

lower four bits are Status bits, used to monitor the presence or absence of the MSR hardware, 

the status of a requested track read command, and the status of the MSR RAM buffers. 

Bit Definitions of MSR C/S Register (R/W) 

b0 

Not Used 

b1 

b2 

b3 

b4 

b5 

b6 

b7 

Busy/Idle 

Read/Data Present 

Not Used 

Interrupt Mask 

Track 1 control 



0-Idle 

1-Stripe Clock present; Read In Progress 

0-Ready 

1-Read Complete; Data Present 

0-Disable Interrupt on read complete 

1-Enable Interrupt on read complete 

0-Reset track registers 

1-Enable Track Read 





b5, b6, b7 set to 000 = Reset and Disable MSR 

Control/Status Register Contents 

Bits 5, 6 and 7 are used to control the data input to the device from the MSR hardware. The 

value of these bits is set by the host. These bits are cleared to 0 by device reset. 

Setting these bits to 0, resets the MSR Track data Byte Counters and the Read Complete 

indication (bit 2) in this register. [The three bits are independent. Setting any one bit resets the 

corresponding registers.] Furthermore, if the RAM_RESET bit of the ASIC Mode register is set, 

then setting these bits to zero also clears ASIC data ram. 

Bit 4 is used to prevent a "Read Complete" Interrupt from being issued. If this bit is clear, no 

interrupt will be issued at the conclusion of an MSR device read; in this case, the MSR C/S 

Register (bit 2) must be polled to determine when a card swipe has been completed. Bit 4 is 

cleared to 0 by device reset.




Bits 1 and 2 are used to reflect the status of the card swipe or track read once it has been 

requested. Bit 1 is zero until the card clock is detected. Once the card clock is detected, this bit 

is set to 1. When the clock disappears, this bit becomes zero, and bit 2 is set on. The transition 

from zero to one of bit 2 causes an interrupt to be issued to indicate that a track read or card 

swipe has been completed (unless bit 4 masks this interrupt). As long as bit 2 remains set, data 

from subsequent card swipes will be ignored. Bit 2 can be reset by clearing bits 5, 6, and 7 of 

this register. (Note: Bit 2 must be cleared before another track read command can be issued.) 

Bits 1 and 2 are cleared to 0 by clearing the track control bits 5 to 7 of this register. 

2.7 MSR Interrupt Reset IRQ Register (0xF9) 

There is one interrupt that can be generated by the internal MSR support within the ASIC device. 

This is the Read Complete Interrupt, which is issued at the completion of a card swipe. This 

interrupt is cleared when the ASIC writes the MSR Reset-IRQ Register at address 0xF9 or by 

device reset. The Read Complete Interrupt can be masked by writing a 1 to bit 4 of the MSR 

C/S Register. 

Note: The Read Complete Interrupt is cleared by reading the Reset-IRQ Register; however, 

address 0xF9. However bit 2 of the MSR C/S Register, the Read Complete Flag, will not be 

cleared until bits 5, 6 and 7 of the MSR C/S Register are cleared by the ASIC. As long as bit 2 

of the MSR C/S Register remains set, data from subsequent card swipes will be ignored. 

NOTE: The MS-DOS driver does not use this register. 

2.8 Alternate RAM Clear Register (0xFA) 

Track 3 

Clear 

Track 2 

Clear 

Track 1 

Clear Reserved Not Used 

b7 b6 b5 b4 b1 b0 

Alternate RAM Clear Register 

Bits 7, 6, and 5 of this Register provide an alternate method to clear ASIC RAM. If the ASIC 

Operational Mode Register bit 2, Alternate RAM Clear Enable, is set to 1, then a write of zeros to 

these bits will result in ASIC RAM being cleared. If the Alternate RAM Clear Enable bit is reset, 

then writing to these bits has no effect.




3.0 Format of Data 

The data returned from the MSR hardware is in raw format. It needs to be unpacked and 

formatted for use. The MS-DOS driver used by NCR provides unpack and formatting routines. 

The source of these routines in provided to assist in unpacking and formatting this data. The 

source code is also provided for this driver. 

ISO TRACK 1 

Start Sentinel (45h) 76 chars -7 bit with parity End Sentinel (1Fh) LRC 

JIS TRACK 1 

Start Sentinel (FFh) 

69 chars- 8 bit with parity 

End Sentinel (FFh) 

LRC 

ISO & JIS TRACK 2 

Start Sentinel (0Bh) 

37 chars-5 bit with parity 

End Sentinel (1Fh) 

LRC 

ISO & JIS TRACK 3 

Start Sentinel (0Bh) 104 chars-5 bit with parity 

End Sentinel (1Fh) 

LRC




4.0 NCR 7454 MSR DRIVER (TAPS driver) 

The DOS driver for the 7454 MSR is provided as an example. 

For this driver, the MSR address (settable in the BIOS) must be specified. The IRQ is defaulted 

to 15. Later versions of the hardware allowed the MSR irq to be specified in the BIOS. The 

MSR configuration is also specified at boot time (command line parameter), values are ISO or 

JIS. 

The following modules are present in the DOS driver for the 7454 MSR in alphabetical order: 

Infm.c 

Infm_dos.c 

Infmappl.h 

Infmconst.hi 

Infdata.c 

Infmdos.c 

Infmextr.hi 

Infmfunc.hi 

Infminit.c 

Infmserv.c 

Infmstruc.h 

Infmtaps.c 

DOS interface functions in C 

DOS interfaces in asm 

Include file definitions 

Constants 

Global data 

C language of driver interfaces 

External declarations 

Function prototypes 

DOS initialization 

Service functions 

Structures 

Taps interfaces 

BOLD indicates modules useful for your development. 

The 7454 MSR initialization via the DOS driver is…. 

Infminit.c (DOS initialization) 

The following steps occur: 

1) The command line is parsed to determine the MSR address: 

Valid addresses are: CC000, CE000, D0000 

(saved at msr_address) 

2) Check to determine if MSR is located at specified address. 

Reads at msr_address + F4 

Set auto recover mode 

(0x10) 

Set reset by alternate reg mode (0x04) 

Reset reset by C&S reg 

(0x02) 

Reset test fill value (0x01) 

Save this value at msr_address + F4




3) Clear Track buffer 

Read IO_ALTERNATE_RAM_CLEAR register 

Msr_address + FA 

Clear track 3 buffer 



(0x80) 

(0x40) 

(0x20) 

4) Check for Track 1, Track2, and Track 3 data to be 00. 

Track 1 data located at msr_address + 0x00 length of 96 bytes 



5) Verify msr_config is ISO or JIS. In the DOS driver this is defaulted or set via command line 

parameter. 

Infmserv.c Extended Driver Initialization 

During extended initialization, the following occurs: 

1) Save current IRQ 15 address, hook IRQ 15 (infm_interrupt_routine) 

Initialize various MSR registers… 

2) Set up ASIC Operational Mode register 

AT msr_address + F4 (IO_ASIC_OPERATIONAL_MODE) 

Set TEST_AUTO_RECOVER bit 

(0x10) 

Set TEST_RESET_BY_ALTERNATIVE bit (0x04) 

Reset TEST_RESET_BY_C_S_REGISTER bit (0x02) 

Reset TEST_FILL_VALUE bit 

(0x01) 

Save new value at msr_address + 0xF4 

3) Reset PIC and enable the IRQ 

Output to port 0x20 -> 0x20 

Output to port 0xA0 -> 0x20 

Read port (0xA1) 

Output to port 0xA1 -> value read & ~(1




Enable interrupt (or with 0x10) 

Save new value at msr_address +0xF8 

5) Clear track buffer 

Read msr_address + 0xFA (IO_ALTERNATE_RAM_CLEAR) 

Clear track 3 or with 0x80 



Save new value at msr_address + 0xFA 

6) Reset interrupt once (don’t know why this is done) 

Read msr_address + 0xF8 

Disable track 3 read (and with 0x7f) 

Disable track 2 read (and with 0xbf) 

Disable track 1 read (and with 0xdf) 

Enable interrupt (or with 0x10) 

Save new value at msr_address + 0xF8 

INFM_INTERRUPT_ROUTINE Hardware Interrupt handling 

The DOS driver interrupt routines places the data in a structure with the following format… 

_CARD_DATA { 

unsigned long ulTrack1Bytes; 

unsigned char auchTrack1Data[LENGTH_TRACK_1_DATA]; 





} 

// len track 1 data 

// track 1 data 

// len track 2data 



// track 3 data




When the interrupt is received the following steps occur: 

1) Read Status and command Register 

Read msr_address + 0xF8 

Test TEST_DATA_PRESENT bit (0x04) 

If present, 

Clear the TEST_INTERRUPT_MASK bit (0x10) 

Disable track 3 read (set TEST_TRACK_3_ENABLE bit) 0x80 



Write new value to msr_address + 0xF8 

2) Read msr_address + 0xF0 (IO_TRACK_1_DATA_COUNTER) to get number of track 1 

bytes read 

Check for overflow bit set , set ulTrack1Bytes to # of bytes or 0 (if overflow) 


bytes read 



bytes read 


5) Copy Track 1 data to above data structure.. 

Read msr_address + 0x00 (OFFSET_TRACK_1_BUFFER) 

Copy bytes from memory-mapped I/O area to driver buffer 







Notify driver that MSR data is ready. 

8) Reset PIC and enable the proper IRQ 

Out 0x20 to port 0x20 

Out 0x20 to port 0xA0 

Read port 0xA1 

Out (value read & ~(1




MSR Data Decode routines 

The MSR data decode routines unpack and format the MSR data. These routines are 

included in the msr driver. The source code for this driver is also included. The areas 

required are specifically in the MSRUPACK.C module. This module contains several 

subroutines used to decode the ‘raw msr data’ to the packed and formatted data the 

application would typically see. The remainder of the files are included for include 

references etc. 

When this driver was written, the variables used were global variables – 

msr_raw_data_buffer and msr_unpacked_buffer. These routines have been used by 

others as a base for decoding the msr data. 

The msr_raw_data_buffer will have the format: 

_CARD_DATA { 







} 



// len track 2data 




Returned Data Formats for Track Reads (msr_unpacked_buffer) 

The formats for the track read data returned to applications are dependent upon the type of card 

being read and the type of reader attached to the system. As mentioned earlier, track 1 on a JIS 

card is the track on the front of the card. Track 2 on an ISO card and track 2 on a JIS card are 

physically in identical locations. 

Delimiters will be used when returning formatted data to separate the track data as well as 

indicate good or bad reads. The default delimiters may be modified if the track is re-configured 

(MSR_CONFIG_TRACK). The default tracks are as follows: 

Good 

BAD 

Track1 (ISO)- 0x61 0xF1 



Track1 (JIS)- 0xE1 0xF1 



The End of Data delimiter will always be a 0x6F for ISO cards and 0xEF for JIS cards.




Track Read Error Codes 

On a track read, if the track delimiter indicates a bad read, the next byte will indicate the error 

cause as follows: 

TRK_START_SENT - Missing start sentinel character 

TRK_PARITY_ERR - Track character parity error 

TRK_END_SENT - Missing end sentinel character 

TRK_LRC_ERR - Longitudinal redundancy check error 

TRK_NO_DATA - No data present on track 

The following are examples of returned MSR data: 

TRACK 1 READ 

ISO Card Cases 0x61 track_data 0x6F ISO track 1 good read 

0xF1 exep_code 0x6F ISO card exception, or JIS II track 

where start sentinel not found 

JIS Card Cases 0xE1 track_data 0xEF JIS II track good read 

0xF1 excep_code 0xEF JIS card exception, at least the JIS II 

track start sentinel was read 

TRACK 2 READ 

Either Card 0x62 track_data 0x6F Track good read 

0xF2 excep_code 0x6F Track exception 

TRACK 1 & 2 READ 

ISO Card Cases 0x61 track1 0x62 track2 0x6F Good read 

0xF1 excep1 0x62 track2 0x6F 

Track 1 exception. Track 2 good read. Also 

returned for JIS card where JIS II track start 

sentinel not read. 

0x61 track1 0xF2 excep2 0x6F Track 1 good read. Track 2 

exception 

0xF1 excep1 0xF2 excep2 0x6F Track 1 and 2 exceptions. Also returned 

for JIS card where JIS II track start 

sentinel not read. 

JIS Card Cases 0xE1 track1 0xE2 track2 0xEF Good read 

0xF1 excep1 0xE2 track2 0xEF Track1 exception. Track 2 good read. At 

least the JIS II track start sentinel was 

read. 

0xE1 track1 0xF2 excep2 0xEF Track 1 good read. Track 2 exception 

0xF1 excep1 0xF2 excep2 

0xEF 

Track 1 and 2 exceptions. At least the 

JIS II track start sentinel was read.

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