ADC 10-bit 2 Gsps Evaluation Board - TSEV83102G0B User Guide

ADC 10-bit 2 Gsps Evaluation
Board - TSEV83102G0B
..............................................................................................
User Guide

Table of Contents
Section 1
Overview............................................................................................... 1-1
1.1 Description ................................................................................................1-1
1.2 TSEV83102G0B Evaluation Board ...........................................................1-2
1.3 Board Mechanical Characteristics.............................................................1-3
1.4 Analog Input, Clock Input and De-embedding Fixture Accesses..............1-4
1.5 Digital Outputs Accesses ..........................................................................1-4
1.6 Power Supplies and Ground Accesses.....................................................1-4
1.7 ADC Function Setting Accesses ...............................................................1-4
Section 2
Layout Information ................................................................................ 2-1
2.1 Board ........................................................................................................2-1
2.2 AC Inputs/Digital Outputs..........................................................................2-1
2.3 DC Function Settings ................................................................................2-1
2.4 Power Supplies .........................................................................................2-2
Section 3
Operating Procedures and
Characteristics ...................................................................................... 3-1
3.1 Introduction ...............................................................................................3-1
3.2 Operating Procedure (ECL Mode) ............................................................3-1
3.3 Use with DMUX Evaluation Board ............................................................3-2
3.4 Electrical Characteristics...........................................................................3-3
3.5 Operating Characteristics..........................................................................3-4
Section 4
Application Information ......................................................................... 4-1
4.1 Introduction ...............................................................................................4-1
4.2 Analog Inputs ............................................................................................4-1
4.3 Clock Inputs ..............................................................................................4-1
4.4 Setting the Digital Output Data Format .....................................................4-1
4.5 ADC Gain Adjust.......................................................................................4-2
4.6 SMA Connectors and Microstrip Lines De-embedding Fixture .................4-2
4.7 Die Junction Temperature Monitoring.......................................................4-3
4.8 Decimation Function .................................................................................4-5
4.9 Pattern Generator Enable .........................................................................4-5
4.10 Data Ready Output Signal Reset..............................................................4-6
4.11 Sampling Delay Adjusting .........................................................................4-6
4.12 Test Bench Description.............................................................................4-7
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Table of Contents
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Section 5
Package Description............................................................................. 5-1
5.1 TS83102G0B Pinout .................................................................................5-1
5.2 Thermal Characteristics ............................................................................5-3
5.2.1 Thermal Resistance from Junction to Ambient: Rthja ........................5-3
5.2.2 Thermal Resistance from Junction to Case: Rthjc .............................5-4
5.2.3 Heatsink..............................................................................................5-4
5.3 Ordering Information .................................................................................5-5
Section 6
Schematics ........................................................................................... 6-1
6.1 TSEV83102G0B Electrical Schematic ......................................................6-1

Section 1
Overview
1.1 Description The TSEV83102G0B Evaluation Board (EB) is a prototype board which has been
designed in order to facilitate the evaluation and the characterization of the
TS83102G0B device (in CBGA152) up to its 3 GHz full power bandwidth at up to 2 Gsps
in the extended temperature range.
The high speed of the TS83102G0B requires careful attention to circuit design and layout
to achieve optimal performance. This four metal layer board with an internal ground
plane has the functions that allow a quick and simple evaluation of the TS83102G0B
ADC performances over the temperature range.
The TS83102G0B Evaluation Board (EB) is very straightforward as it only implements
the TS83102G0B ADC device, SMA connectors for input/output accesses and a
2.54 mm pitch connector compatible with high speed acquisition system high frequency
probes.
The board has been designed to be fully compatible with Atmel’s DMUX evaluation
board (TSEV81102G0).
The board also implements a de-embedding fixture in order to facilitate the evaluation of
the high frequency insertion loss of the input microstrip lines.
The board is constructed like a sandwich of two dielectric layers, featuring low insertion
loss and enhanced thermal characteristics for operation in the high frequency domain
and extended temperature range.
The board dimensions are 120 mm x 150 mm.
The board set comes fully assembled and tested, with the TS83102G0B installed and
with a heatsink.
TSEV83102G0B - Evaluation Board User Guide 1-1
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Overview
1.2 TSEV83102G0B
Evaluation Board
Figure 1-1. TSEV83102G0B Block Diagram
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CLK
Differential
Clock inputs
CLKB
VIN
Differential
analog inputs
VINB
TEST
CAL1
CAL2
VCC
VEE
GND
DVEE
GAIN
SDA
OA
+5V
-5V
-5V
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
VEE
CLK
CLKB
VIN
VINB
GA
PGEB
SDA
SDAEN
TS83102G0B
DRRB
VCC
GND
VPLUSD
VEE
DVEE
DIODE
L = 50 mm typ
LVIN/VINb = LCLK/CLKb = 43 mm typ
Loutputs = 58 mm typ
Short-circuit
possibility
here
DR/DRB
D0/D0B
D7/D7B
PC/PCB
VCC = +5V
GND = 0V
VEE
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
VPLUSD = -0.8V (ECL)
VPLUSD = 1.6V (LVDS)
VEE = -5V
DVEE = -5V
DRRB
B/BG
J - diode
V - diode
V-GND
I-GND

1.3 Board
Mechanical
Characteristics
Overview
The board’s layer number, thickness, and functions are given below, from top to bottom.
Table 1-1. Board’s Layer Thickness Profile
Layer Characteristics
Layer 1
Copper layer
Layer 2
RO4003 dielectric layer
(Hydrocarbon/Wovenglass)
Layer 3
Copper layer
Layer 4
BT/Epoxy dielectric layer
Layer 5
Copper layer
Layer 6
BT/Epoxy dielectric layer
Layer 7
Copper layer
Layer 8
BT/Epoxy dielectric layer
Layer 9
Copper layer
Layer 10
BT/Epoxy dielectric layer
Layer 11
Copper layer
Copper thickness = 40 µm
AC signal traces = 50Ω microstrip lines
DC signal traces (B/GB, GAIN, DIODE, OA, TEST, SDA)
Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz
-0.044 dB/inch insertion loss at 2.5 GHz
-0.318 dB/inch insertion loss at 18 GHz
Copper thickness = 39 µm
Ground plane = reference plane 50Ω microstrip return
Layer thickness = 330 µm
Copper thickness = 35 µm
Power and ground planes
Layer thickness = 330 µm
Copper thickness = 35 µm
Power and ground planes (identical to layer 5)
Layer thickness = 330 µm
Copper thickness = 35 µm
Ground planes (identical to layer 3)
Layer thickness = 200 µm
Copper thickness = 35 µm
Power and ground planes
The TSEV83102G0B is an eleven layer PCB made of six copper layers and five dielectric
layers. The six metal layers correspond respectively from top to bottom to the AC
and DC signals layer (layer 1), two ground layers (layers 3 and 5), and one supply layer
(layer 7).
Considering the severe mechanical constraints due to the wide temperature range and
the high frequency domain in which the board is to operate, it is necessary to use a
sandwich of two different dielectric materials, with specific characteristics:
� A low insertion loss RO4003 Hydrocarbon/Wovenglass dielectric layer of 200 µm
thickness, chosen for its low loss (-0.318 dB/inch) and enhanced dielectric
consistency in the high frequency domain. The RO4003 dielectric layer is dedicated to
the routing of the 50Ω impedance signal traces (the RO4003 typical dielectric
constant is 3.4 at 10 GHz). The RO4003 dielectric layer characteristics are very close
to PTFE in terms of insertion loss characteristics.
� A BT/Epoxy dielectric layer of 0.9 mm total thickness which is sandwiched between
the upper ground plane and the back-side supply layer.
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Overview
1.4 Analog Input,
Clock Input and
De-embedding
Fixture Accesses
1.5 Digital Outputs
Accesses
1.6 Power Supplies
and Ground
Accesses
1.7 ADC Function
Setting Accesses
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The BT/Epoxy layer has been chosen because of its enhanced mechanical characteristics
for elevated temperature operation. The typical dielectric constant is 4.5 at 1 MHz.
More precisely, the BT/Epoxy dielectric layer offers enhanced characteristics compared
to FR4 Epoxy, namely:
� Higher operating temperature values: 170° C (125° C for FR4).
� Better withstanding of thermal shocks (-65° C up to 170° C).
The total board thickness is 1.6 mm. The previously described mechanical and frequency
characteristics makes the board particularly suitable for device evaluation and
characterization in the high frequency domain and in military temperature ranges.
The differential active inputs (Analog, Clock, De-embedding fixture) are provided by
SMA connectors.
Reference: VITELEC 142-0701-851.
Connector mounting plates have been used for fastening the SMA connectors.
Access to the differential output data port is provided by a 2.54 mm pitch connector,
compatible with the high speed digital acquisition system. It enables access to the converter
output data, as well as proper 50Ω differential termination.
The power supply accesses are provided by five 2 mm section banana jacks respectively
for DVEE , VEET , VDD , VPLUSD and VCC .
The power supply access is provided by one 4 mm section banana jack for VEE .
The Ground accesses are provided by four 2 mm and one 4 mm banana jacks.
For ADC function setting accesses (B/GB, Die junction temp., Test), 2 mm section
banana jacks are provided.
Three potentiometers are provided for ADC gain adjust, Sampling delay adjust and Offset
adjust.
One sub-screw is provided for Asynchronous data ready reset.

Section 2
Layout Information
2.1 Board The TS83102G0B requires proper board layout for optimum full speed operation.
The following explains the board layout recommendations and demonstrates how the
Evaluation Board fulfills these implementation constraints.
A single low impedance ground plane is recommended, since it allows the user to lay
out signal traces and power planes without interrupting the ground plane.
Therefore a multi-layer board structure has been retained for the TSEV83102G0B.
Six copper metal layers are used, dedicated respectively (from top to bottom) to the signal
traces, ground planes and power supplies.
2.2 AC Inputs/Digital
Outputs
2.3 DC Function
Settings
The board uses 50Ω impedance microstrip lines for the differential analog inputs, clock
inputs, and differential digital outputs.
The input signals and clock signals must be routed on one layer only, without using any
through-hole vias. The line lengths are matched to within 2 mm.
The digital output lines are 50Ω differentially terminated.
The output data trace lengths are matched to within 0.25 inch (6 mm) to minimize the
data output delay skew.
For the TSEV83102G0B the propagation delay is approximately 6.1 ps/mm
(155 ps/inch). The RO4003 typical dielectric constant is 3.4 at 10 GHz.
For more informations about different output termination options refer to the specification
application notes.
The DC signal traces are low impedance.
They have been routed with a 50Ω impedance near the device because of space
restriction.
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Layout Information
2.4 Power Supplies The bottom metal layers 5 and 7 and 11 are dedicated to power supply traces (VEE, DVEE, VEET, VDD, VPLUSD and VCC). The supply traces are approximately 6 mm wide in order to present low impedance, and
are surrounded by a ground plane connected to the two inner ground planes.
The analog and digital negative power supply traces are independent, but the possibility
exists to short-circuit both supplies on the top metal layer).
No difference in ADC high speed performance is observed when connecting both negative
supply planes together. Obviously one single negative supply plane could be used
for the circuit.
Each power supply incoming is bypassed by a 1 µF Tantalum capacitor in parallel with
1 nF chip capacitor.
Each power supply access is decoupled very close to the device by 10 nF and 100 pF
surface mount chip capacitors in parallel.
Note: The decoupling capacitors are superposed. In this configuration, the 100 pF capacitors
must be mounted first.
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Section 3
Operating Procedures and
Characteristics
3.1 Introduction This section describes a typical single-ended configuration for analog inputs and clock
inputs.
The single-ended configuration is preferable, as it corresponds to the most straightforward
and quickest TSEV83102G0B board setting for evaluating the TS83102G0B at full
speed in its temperature range.
The inverted analog input VINB and clock input CLKB common mode level is Ground
(on-chip 50Ω terminated). In this configuration, no balun transformer is needed to convert
properly the single-ended mixer output to balanced differential signals for the
analog inputs.
In the same way, no balun is necessary to feed the TS83102G0B clock inputs with balanced
signals.
Directly connect the RF sources to the in-phase analog and clock inputs of the
converter.
However, dynamic performances can be somewhat improved by entering either analog
or clock inputs in differential mode.
3.2 Operating
Procedure (ECL
Mode)
1. Connect the power supplies and Ground accesses
(V CC = +5V, GND = 0V, V PLUSD = 0V, V EE = DV EE = -5V) through the dedicated
banana jacks.
The -5V power supplies should be turned on first.
Note: one single -5V power supply can be used for supplying the digital DV EE and
analog V EE power planes.
2. The board is set by default for digital outputs in binary format.
3. Connect the CLK clock signal.
The inverted phase clock input CLKB may be left open (as on-chip 50Ω terminated).
Use a low phase noise RF source. The clock input level is typically
4 dBm and should not exceed +10 dBm into the 50Ω termination resistor (maximum
ratings for the clock input power level is 15 dBm).
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Operating Procedures and Characteristics
3.3 Use with DMUX
Evaluation Board
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4. Connect the analog signal V IN . The inverted phase clock input V INB may be left
open (as on cavity 50Ω terminated). Use a low phase noise RF source. Full
scale range is 0.5V peak to peak around 0V, (±250 mV), or -2 dBm into 50Ω.
Input frequency can range from DC up to 1.8 GHz. At 3.0 GHz, the ADC attenuates
the input signal by -3 dB. The board insertion loss (S21) will be furnished in
the definitive document release.
5. Connect the high speed data acquisition system probes to the output connector.
The connector pitch (2.54 mm) is compatible with high speed digital acquisition
system probes. The digital data are on-board differentially terminated. However,
the output data can be picked up either in single-ended or differential mode.
The TSEV81102G0 DMUX evaluation board has been designed to be fully compatible
with the TSEV83102G0B ADC evaluation board.
The DEMUX input configuration has been optimized to be connected to the
TS83102G0B ADC (CBGA152 package).
When using the DEMUX board with the ADC board, do not forget to set, for proper use,
CLKINTYPE in mode DR/2 (jumper on-board).
The power-up sequence should be:
1. Supply the ADC first
2. Supply the DMUX
3. Perform an asynchronous reset on the DMUX board
When this power up sequence has been completed, the synchronization between the
DEMUX and ADC boards can be achieved via the DEMUXDelADjCtrl potentiometer on
the DEMUX evaluation board. To achieve a good synchronization between the two
boards, it is recommended to run the ADC at its full speed (max sampling rate) and tune
the DEMUX Delay Adjust Control potentiometer to the left and take down the settings for
which the boards are de-synchronized and similarly to the right to see the loss of synchronization
at the other extremity. The right setting of the potentiometer is in the middle
of these two settings and should be right for all sampling rates of the ADC.
Please refer to the "ADCs and Demux Application Notes" document for more
information.

3.4 Electrical
Characteristics
Table 3-1. Absolute Maximum Ratings
Operating Procedures and Characteristics
Parameter Symbol Comments Value Unit
Positive supply voltage V CC GND to 5.5 V
Digital negative supply voltage DV EE GND to -5.5 V
Digital positive supply voltage V PLUSD GND -1.1 to 2.0 V
Negative supply voltage V EE GND to -5.5 V
Maximum difference between negative supply voltages DV EE to V EE 0.3 V
Analog input voltages V IN or V INB -1.5 to +1.5 V
Maximum difference between V IN and V INB V IN - V INB -1.5 to +1.5 V
Clock input voltage V CLK or V CLKB -1 to +1 V
Maximum difference between V CLK and V CLKB V CLK - V CLKB -1 to +1 V
Static input voltage VD GA/SDA -5 to +0.8 V
Digital input voltage VD SDAEN, DRRB,
B/GB, PGEB
-5 to +0.8 V
Digital output voltage VO VPLUSD -2.2 to VPLUSD +0.3 V
Maximum junction temperature T j +125 ° C
Storage temperature T stg -65 to +150 ° C
Lead temperature (soldering 10s) Tleads +300 ° C
Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat
sink is mandatory.
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Operating Procedures and Characteristics
3.5 Operating
Characteristics
Table 3-2. Electrical Operating Characteristics
Parameter Symbol
Positive supply voltage
(dedicated to TS83102G0B ADC only)
Positive supply current
(dedicated to TS83102G0B ADC only)
Positive supply voltage not used by default – installed
(dedicated to MC100EL16 differential receivers)
Positive supply current not used by default – installed
(dedicated to MC100EL16 differential receivers)
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The power supplies denoted by VCC, VEE, DVEE and VPLUSD are dedicated to the
TS83102G0B ADC.
The power supplies denoted VEET, VDD are dedicated to the optional MC100EL16 asynchronous
differential receivers.
Value
Min Typ Max
V CC 4.75 5 5.25 V
V PLUSD
–
ECL: -0.8
LVDS: 1.6
V EEA -5.25 -5 -4.75 V
V EED -5.25 -5 -4.75 V
–
Unit
I CC – 144 205 mA
I PLUSD – 164 – mA
I EEA – 514 630 mA
I EED – 170 180 mA
V EET -5.25 -5 -4.75 V
V DD -2.15 -2 -185 V
I EET – 180 – mA
I DD – 480 – mA
Nominal power dissipation (without receivers) PD – 4.6
5.1
(TJ = 125° C)
W
Analog input impedance ZIN – 50 – Ω
Full power analog input bandwidth (-3 dB) – – 3.0 – GHz
Analog input voltage range (differential mode) V IN -125 – 125 mV
Clock input impedance – – 50 – Ω
Clock input voltage compatibility (single-ended or
differential) (See Application Notes)
– ECL levels or 4 dBm (typ) into 50Ω –
Clock input power level into 50Ω termination resistor – -2 2 4 dBm
V
V

Section 4
Application Information
4.1 Introduction For this section, also refer to the product "Main features" (TS83102G0B Datasheet).
More particularly, refer to sections related to single-ended and differential input
configurations.
4.2 Analog Inputs The analog inputs can be entered in differential or single-ended mode without any high
speed performance degradation.
The board digitizes single-ended signals by choosing either input and leaving the other
input open, as the latter is on-board 50Ω terminated. The nominal in-phase inputs are
VIN (See Section 3).
4.3 Clock Inputs The clock inputs can be entered in differential or single-ended mode without any performance
degradation for a clock frequency up to 500 MHz. At higher rates, it is
recommended to drive the clock inputs differentially. Moreover, the typical in phase
clock input amplitude is 1V peak to peak, centered on 0V (Ground), or -1.3V (ECL) on
common mode.
As for the analog input, either clock input can be chosen (if the single-ended output
mode is used), leaving the other input open, as both clock inputs are on-chip 50Ω terminated.
The nominal in-phase clock input is CLK (Section 3).
4.4 Setting the
Digital Output
Data Format
For this section, refer to the Evaluation Board Electrical schematic and to the components
placement document (respectively Figure 6-2 on page 6-3 and Figure 6-8 on page
6-4).
Refer also to the TS83102G0B specification about digital output coding.
The TS83102G0B delivers data in natural binary code or in Gray code. If the B/GB input
is left floating or tied to GND the data format selected will be natural binary, if this input
is tied to VEE the data will follow the Gray code.
Use the jumper denoted B/GB to select the output data port format:
� If B/GB is left floating or tied to GND, the data output format is true binary.
� If B/GB is tied to V EE or driven with ECL low level, the data outputs are in the Gray
format.
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Application Information
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The VPLUSD positive supply voltage allows the adjustment of the output common mode
level from -1.05V (VPLUSD = -0.8V for ECL output compatibility) to +1.35V (VPLUSD = 1.6V
for LVDS output compatibility).
Each output voltage varies between -0.9V and -1.2V (respectively +1.2V and +1.5V),
leading to ±0.3V = 660 mV in differential for VPLUSD = -0.8V (respectively 1.6V).
4.5 ADC Gain Adjust The ADC gain is adjustable by the means of pin R9 (pad input impedance is 1 MΩ in
parallel with 2 pF). A jumper denoted GAIN has been foreseen in order to have access
to the ADC gain adjust pin.
The GAIN potentiometer is dedicated to adjusting the ADC gain from approximately
0.85 up to 1.15.
The gain adjust transfer function is given below.
4.6 SMA Connectors
and Microstrip
Lines Deembedding
Fixture
Figure 4-1. ADC Gain Adjust
ADC Gain
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
-600 -400 -200 0 200 400 600
Vgain (command voltage) (mV)
Attenuation in microstrip lines can be found by taking the difference in the log magnitudes
of the S21 scattering parameters measured on two different lengths of
meandering transmission lines.
Such a measurement also removes common losses such as those due to transitions
and connectors.
The S21 scattering parameter corresponds to the amount of power transmitted through
a two-port network.
The characteristic impedance of the microstrip meander lines must be close to 50Ω to
minimize impedance mismatch with the 50Ω network analyzer test ports.
Impedance mismatch will cause ripples in the S21 parameter as a function of both the
degree of mismatch and the length of the line.

4.7 Die Junction
Temperature
Monitoring
Application Information
Figure 4-2 and Figure 4-3 illustrate the recommanded implementation of the die junction
temperature monitoring function for the Revision B of the 10-bit 2 Gsps ADC.
The user has the choice between two possible configurations:
1. The ADC decimation test mode is NOT ALLOWED.
Because of the use of 1 internal diode-mounted transistors, the user has to implement
2 x 2 head-to-tail protection diodes to avoid potential reverse current flows to damage
the diode pin.
Note that Atmel usually recommends the use of 2 x 3 head-to-tail protection diodes but
in this particular case, it is necessary to have exactly 2 diodes in the A10 to ground
direction of conduction.
Figure 4-2. Recommended Die Junction Temperature Monitoring Function Implementation,
Test Mode Not Allowed
ADC Pin
A10
2. The ADC test mode can be allowed
In case the user wants to still be able to switch from the normal mode to the test mode or
to the die junction temperature monitoring, the protection diode configuration is slightly
different and takes into account the fact that the test mode can be activated by applying
VEE = -5V to the diode pin.
This explains why 7 protection diodes are needed in the other direction, as described in
Figure 4-3.
Figure 4-3. Recommended Diode Pin Implementation Allowing for Both Die Junction
Temperature Monitoring Function and Test Mode
TSEV83102G0B - Evaluation Board User Guide 4-3
GND
ADC Pin
A10
GND
IGND
Idiode
Vdiode
VGND
IGND
Idiode
Vdiode
VGND
V
V
1 mA
1 mA
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Application Information
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For Revision B, the VDIODE characteristic corresponds to a single diode characteristic
over temperature, thus starting at 0.9V, as illustrated in Figure 4-4, which is only an
interpolated VDIODE characteristic (to be confirmed by future measurements).
This modification in Revision B devices implies the modification of the processing of the
VDIODE characteristic if any but above all, it allows the user to implement a digital temperature
sensor to be interfaced with the ASIC (DSP, FPGA, etc...) loading the ADC.
Figure 4-4. Diode Pin Implementation in Test Mode
A typical configuration with a standard digital temperature sensor is depicted in
Figure 4-5.
Figure 4-5. Typical Configuration with a Digital Temperature Sensor
A10
GND
ADC Pin
A10
GND
DXT
DXN
Temperature
Sensor
VEE = -5V

4.8 Decimation
Function
4.9 Pattern
Generator
Enable
Application Information
The expected diode mounted transistors V DIODE value (including chip parasitic resistance)
versus junction temperature is given in Figure 4-6 (I DIODE = 1 mA).
Figure 4-6. Junction Temperature Versus Diode Voltage for I = 1 mA
Diode Voltage (mV)
940
930
920
910
900
890
880
870
860
850
840
830
820
810
800
790
-10 0 10 20 30 40 50 60 70 80 90 100 110
Junction Temperature (°C)
Note: The operating die junction temperature must be kept below 125° C; therefore, an adequate
cooling system has to be set up.
The decimation function can be used for debug of the ADC at initial stages. This function
indeed allows to reduce the ADC output rate by 32, thus allowing for a quick debug
phase of the ADC at maximum speed rate.
When active, this fuction makes the ADC output only 1 out of 32 data, thus resulting in a
data rate which is 32 times slower than the clock rate.
The TS83102G0B is able to generate by itself (without any analog input signal) a serie
of patterns. If the TEST input is left floating or tied to GND the TS83102G0B will digitize
the analog input signal according to B/GB. If this input is driven with ECL low level or
tied to VEE, TS83102G0B will generate Checker Board patterns.
Use the jumper denoted TEST for enabling the pattern generator.
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Application Information
4.10 Data Ready
Output Signal
Reset
4.11 Sampling Delay
Adjusting
Figure 4-7. Sampling Delay Adjust
Delay
400p
300p
200p
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A sub-screw connector is provided for the DRRB command.
The Data Ready signal is reset on the falling edge of the DRRB input command, on ECL
logical low level (-1.8V). DRRB may also be tied to VEE = -5V for Data Ready output signal
master reset. As long as DRRB remains at a logical low level, (or tied to VEE = -5V),
the Data Ready output remains at logical zero and is independent of the external free
running encoding clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps
typically.
TRDR is measured between the -1.3V point of the falling edge of the DRRB input command
and the zero crossing point of the differential Data Ready output signal (DR,
DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
The Data Ready output signal restarts on the DRRB command rising edge, ECL logical
high levels (-0.8V).
DRRB may also be grounded, or is allowed to float, for normal free running of the Data
Ready output signal.
One delay adjust, controlled by SDA potentiometer, is available in order to add a delay
to the input clock of the ADC. This allows the user to tune the instant of the internal sampling.
To enable this delay adjustment there is an SDAEN pin on the chip. In the current
revision, the SDAEN function corresponds to the OA labels (OA jumper and OA
potentiometer).
The OA potentiometer has been removed and short-circuited to VEE. Use the jumper denoted OA to enable the sampling delay adjustment:
� If OA is left floating or tied to GND, the SDA is disabled
� If OA is tied to V EE , the SDA is enabled
The SDA input varies from -0.5 to 0.5V, according to the SDA potentiometer position.
The variation of the delay around its nominal value as a function of the SDA voltage is
more or less linear, as shown in Figure 4-7 (simulation results).
: (cross(clip((VT("delop") - VT("delon")) 4e-10 2e-09) 0 2 "rising") - cross(clip((VT("delip") - VT("delin")) 2.5e-10 2e-09) 0 2 "rising")) (60°C)
Delay in the variable delay cell at 60°C
100p
-500m -400m -300m -200m -100m 0m
SDAVAL
100m
200m 300m 400m 500m
Note: The variation of the delay as a function of temperature is insignificant.

4.12 Test Bench
Description
Figure 4-8. Differential Analog and Clock Input Configuration
Synchro 10 MHz
Figure 4-9. Single-ended Analog and Clock Input Configuration
Synchro 10 MHz
RF Generator
-121 dBc/Hz at 1 KHz
offset from fc
RF Generator
-117 dBc/Hz at 20 KHz
offset from fc
GPIB
Data Acquisition
System
PC
Data Acquisition
System
GPIB
RF Generator
RF Generator
PC
0 − 180°
Hybrid
Application Information
0 − 180°
Hybrid
TSEV83102G0B - Evaluation Board User Guide 4-7
BPF
10 Data
BPF
10 Data
DR
CLKB CLK
TS83102G0B
ADC
Tunable delay line
(50Ω) CLKB CLK
DR
TS83102G0B
ADC
Tunable delay line
VINB
VIN
VINB (50Ω)
VIN
2166D–BDC–01/04

Application Information
4-8 TSEV83102G0B - Evaluation Board User Guide
2166D–BDC–01/04

5.1 TS83102G0B
Pinout
Figure 5-1. TS83102G0B Pinout of CBGA152 Package
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Section 5
Package Description
A B C D E F G H J K L M N P Q R
NC
GND
DVEE
VPLUSD
B/GB
DECB/
DIODE
GND GND VPLUSD VPLUSD VPLUSD GND DVEE DVEE GND VPLUSD VPLUSD VPLUSD GND GND
DVEE DVEE DVEE DVEE
VPLUSD VPLUSD GND VPLUSD
GND VPLUSD VPLUSD VPLUSD
GND VEE VPLUSD VEE
PGEB GND VEE VEE VEE
VEE
VCC
SDA
GND
VEE
GND
GND OR D0 D1 D2 D3 DR D4 D5 D6 D7 D8 D9 GND
GND ORB D0B D1B D2B D3B DRB D4B D5B D6B D7B D8B D9B GND
VEE VEE VCC VCC
VCC VCC GND GND
VCC
VEE
TS83102G0B
CBGA152
(cavity down)
VCC GND
VEE GND
VEE VEE GND GND GND
GND VEE GND GND GND GND VEEH VCCTH VCCTH VEE VEE GND VEE VEE VEE
NC GND GND GND GND GND GND VEEH VEEH VCCTH
VEE VEE GND
Note: If required, four NC balls can be electrically connected to GND to simplify PCB routing.
TSEV83102G0B - Evaluation Board User Guide 5-1
GND
GND
NC
GND
DVEE
VPLUSD
GND
VEE
GA
VCC
GND
VINb
VIN
GND GND NC
GND GND GND CLK CLKb GND VEEH VEEH VCCTH VEE GND DRRB SDAEN GND
A B C D E F G H J K L M N P Q R
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Rev. 2166D–BDC–01/04

Package Description
Table 5-1. TSEV83102G0B Pin Description
Symbol Pin Number Function
Power Supplies
V CC K1, K2, J3, K3, B6, C6, A7, B7, C7, P8, Q8, R8 +5V analog supply
GND
V EE
5-2 TSEV83102G0B - Evaluation Board User Guide
2166D–BDC–01/04
B1, C1, D1, G1, M1, Q1, B2, C2, D2, E2, F2,
G2, N2, P2, Q2, A3, B3, D3, E3, F3, G3, N3,
P4, Q4, R4, A5, P5, Q5, P6, Q6, P7, Q7, R7,
B9, B10, B11, R11, P12, A14, B14, C14, G14,
K14, P14, Q14, R14, B15, Q15, B16, Q16
H1, J1, L1, H2, J2, L2, M2, C3, H3, L3, M3, P3,
Q3, R3, A4, B4, C4, B5, C5, A8, B8, C8, C9,
P9, Q9, C10, Q10, R10
Analog ground
-5V analog supply
VPLUSD P10, C11, P11, Q11, A12, B12, C12, Q12,
R12, D14, E14, F14, L14, M14, N14
Digital positive supply
DVEE A13, B13, C13, P13, Q13, R13, H14, J14 -5V digital supply
Analog Inputs
V IN
V INB
Clock Inputs
R5
R6
CLK E1 In-phase (+) clock input
In-phase (+) analog input signal of the differential sample
and hold preamplifier
Inverted phase (-) analog input signal of the differential
sample and hold preamplifier
CLKB F1 Inverted phase (-) clock input
Digital outputs
D0, D1, D2, D3, D4,
D5, D6, D7, D8, D9
D0B, D1B, D2B, D3B,
D4B, D5B, D6B, D7B,
D8B, D9B
D16, E16, F16, G16, J16, K16, L16, M16, N16,
P16
D15, E15, F15, G15, J15, K15, L15, M15, N15,
P15
In-phase (+) digital outputs
D0 is the LSB. D9 is the MSB
Inverted phase (-) digital outputs
OR C16 In-phase (+) Out-of-Range output
ORB C15 Inverted phase (-) Out-of-Range output
DR H16 In-phase (+) Data Ready Signal output
DRB H15 Inverted phase (-) Data Ready Signal output
Additional Functions
B/GB A11
Binary or Gray select output format control
- Binary output format if B/GB is floating or connected to
GND
- Gray output format if B/GB is driven with ECL low level or
B/GB is connected to V EE

Table 5-1. TSEV83102G0B Pin Description (Continued)
Symbol Pin Number Function
DIODE A10
PGEB A9
5.2 Thermal
Characteristics
5.2.1 Thermal Resistance
from Junction to
Ambient: Rthja
Package Description
Decimation function enable or die junction temperature
monitoring:
- Decimation active when LOW (die junction temperature
monitoring NOT possible)
- Normal mode when HIGH or left floating
- Die junction temperature monitoring when current is
applied
Active low pattern generator enable
- Digitized input delivered at outputs according to B/GB if
PGEB is floating or connected to GND
- Checkerboard pattern delivered at outputs if PGEB is
driven with ECL low level or connected to V EE
DRRB N1 Asynchronous Data Ready Reset function
GA R9 Gain Adjust
SDA A6 Sampling delay adjust
SDAEN P1
Table 5-2. Thermal Resistance
Sampling delay adjust enable:
- inactive if floating or connected to GND
- active if ECL low or connected to V EE
Table 5-2 lists the converter’s thermal performance parameters of the device itself, with
no external heatsink added.
Air Flow (m/s)
Estimated ja Thermal
Resistance (° C/W)
0 45 Figure 5-2. Thermal Resistance from Junction to Ambient: Rthja
0.5 35.8
1 30.8
1.5 27.4
2 24.9
2.5 23
3 21.5
4 19.3
5 17.7
TSEV83102G0B - Evaluation Board User Guide 5-3
Rthja (°C/W)
50
40
30
20
10
0
0
1 2 3 4 5
Air flow (m/s)
2166D–BDC–01/04

Package Description
5.2.2 Thermal Resistance
from Junction to
Case: Rthjc
5-4 TSEV83102G0B - Evaluation Board User Guide
2166D–BDC–01/04
Maximum thermal Junction to Case resistance is 4.0° C/Watt.
This value does not include thermal contact resistance between the package and external
heatsink (glue, paste, or thermal foil interface for example).
As an example, we can take 2.0° C/W for 50 µm thickness of thermal grease.
5.2.3 Heatsink It is recommended to use a 50 mm x 50 mm x 30 mm heatsink (respectively L x l x H) in
case of natural convection cooling mode (with no air flow).
A fan heatsink or direct conduction cooling is recommended, due to high power dissipation
(4.7W).
A method should be chosen for cooling that allows less than 4.0° C/W for the case to
ambient thermal resistance (Rthca).
The thermal resistance of the board is a high value (within a range of 30° C/W); thus an
external heatsink is mandatory.
The heatsink must be fixed to the heatspreader which is at -5V. So the heatsink needs
to be electrically isolated; using adequate low Rth electrical isolation.
Example: 4.0° C/W Rthca (case to ambient) +2.0° C/W thermal grease resistance
+4.0° C/W Rthjc = 10.0° C/W total (Rthja).
The heatsink should make contact with the package on the side opposite to the balls, in
a 8.5 mm diameter circle:
Figure 5-3. CBGA152 Board Assembly
24.2
20.2
Note: The measures are given in mm.
50.5
Cooling system efficiency can be monitored using the Temperature Sensing Diodes,
integrated in the device.
8.5
31
Board
32.5

5.3 Ordering
Information
Package Description
Part Number Package Temperature Range Screening Level Comments
JTSX83102G0-1V1B Die Ambient Prototype
ON REQUEST ONLY
(Please contact Marketing)
TSX83102G0BGL CBGA 152 Ambient Prototype Prototype Version
TS83102G0BCGL CBGA 152
TS83102G0BVGL CBGA 152
“C” grade:
0° C < T C; T J < 90° C
“V” grade:
-20° C < T C ; T J < 110° C
Standard
Standard
TSEV83102G0BGL CBGA 152 Ambient Prototype
Evaluation Board
(delivered with heatsink)
TSEV83102G0B - Evaluation Board User Guide 5-5
2166D–BDC–01/04

Package Description
5-6 TSEV83102G0B - Evaluation Board User Guide
2166D–BDC–01/04

6.1 TSEV83102G0B
Electrical
Schematic
Section 6
Schematics
Figures 6-2 to Figures 6-8 shows the electrical schematic of the TSEV83102G0B.
The pinout used for the evaluation board has been translated from Atmel's pinout (refer
to page 5-1) to the JEDEC standard shown in Figure 6-1. This explains the discrepancies
between the pinout used on page 5-1 and the one given in the electrical schematic
in Figure 6-2.
TSEV83102G0B - Evaluation Board User Guide 6-1
Rev. 2166D–BDC–01/04

Schematics
Figure 6-1. TS83102G0B pinout in JEDEC Standard
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
6-2 TSEV83102G0B - Evaluation Board User Guide
2166D–BDC–01/04
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
NC
GND
DVEE
VPLUSD
B/GB
DECB/
DIODE
GND GND VPLUSD VPLUSD VPLUSD GND DVEE DVEE GND VPLUSD VPLUSD VPLUSD GND GND
DVEE DVEE DVEE DVEE
VPLUSD VPLUSD GND VPLUSD
GND VPLUSD VPLUSD VPLUSD
GND VEE VPLUSD VEE
PGEB GND VEE VEE VEE
VEE
VCC
SDA
GND
VEE
GND
GND OR D0 D1 D2 D3 DR D4 D5 D6 D7 D8 D9 GND
GND ORB D0B D1B D2B D3B DRB D4B D5B D6B D7B D8B D9B GND
VEE VEE VCC VCC
VCC VCC GND GND
VCC
VEE
TS83102G0B
CBGA152
(cavity down)
VCC GND
VEE GND
VEE VEE GND GND GND
GND VEE GND GND GND GND VEEH VCCTH VCCTH VEE VEE GND VEE VEE VEE
NC GND GND GND GND GND GND VEEH VEEH VCCTH
VEE VEE GND
GND
GND
NC
GND
DVEE
VPLUSD
GND
VEE
GA
VCC
GND
VINb
VIN
GND GND NC
GND GND GND CLK CLKb GND VEEH VEEH VCCTH VEE GND DRRB SDAEN GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A

Figure 6-2. TSEV83102G0B Electrical Schematic
XJ10
VEE
J7
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
CON2X48
BUF_PCb
BUF_PC
B17
TEST
1
BUF_D0b
BUF_D0
PTTEST
CAVALIER
NC
J10 2
2
Jumper
C13
VEE
10nF
1
1
1
C14
100pF
3
FICHE BANANE 2mm rouge
DVEE
VEE
3
BUF_D1b
BUF_D1
50 ohms impedance lines
same line length
1
N1
N2
N3
N14
N15
N16
P8
P9
A8
A9
A11
B8
B9
B11
B12
C3
C8
C11
C12
C14
C15
C16
D1
D2
D3
E2
E3
H1
H2
H3
J3
J14
J15
K3
K15
K16
BUF_D2b
BUF_D2
V1
B/GB
2
2
XJ1
1
PTB/GB
B1
NC
J1
1
FICHE BANANE 2mm rouge / B/GB Jumper
1
PCb
PC
D0b
3
BUF_D3b
BUF_D3
3
D1b
D1
D2b
D2
D3b
D3
DRb
DR
D4b
D4
D5b
D5
D6b
D6
D7b
D7
D8b
D8
D9b
D9
D0
BUF_DRb
BUF_DR
B2
1
FICHE BANANE 2mm noire
B3
BUF_D4b
BUF_D4
1
D1
ZENER
NC
DIODE
C129
100nF
NC
FICHE BANANE 2mm noire / V-GND
1
BUF_D5b
BUF_D5
2
BUF_D6b
BUF_D6
BUF_D7b
BUF_D7
Q3
R3
Q4
R4
Q5
R5
Q6
R6
Q7
R7
Q8
R8
Q9
R9
Q10
R10
Q11
R11
Q12
R12
Q13
R13
Q14
R14
PCb (ORb)
PC (OR)
D0b
D0
D1b
D1
D2b
D2
DVEE
DVEE
DVEE
DVEE
DVEE
DVEE
DVEE
DVEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
D3b
D3
DRb
DR
D4b
D4
D5b
D5
D6b
D6
D7b
D7
D8b
D8
D9b
D9
A2
A3
A4
A7
A12
A15
B1
B2
B3
B4
B5
B6
B7
B13
B14
B15
B16
C1
C2
C4
C5
C6
C7
C13
D14
D15
D16
E1
E14
E15
F14
F15
G14
G15
G16
J2
K2
L2
L16
M13
P1
P2
P3
P7
P10
P14
P15
P16
Q1
Q2
Q15
Q16
R2
R15
B5
1
BANANA JACK 2mm red / V-DIODE
B6
1
FICHE BANANE 2mm noire / I-GND
BUF_D8b
BUF_D8
CLK
CLKB
A5
A6
CLK
S2
BUF_D9b
BUF_D9
1
1
Clock
2
DRRB
50 ohms impedance lines
2
OA
A13
DRRB
A14
OA (SDAEN)
VIN
VINB
E16
VIN F16
VINB
CLKB
PTGAIN
PTSDA
PTOA
GAIN
SDA OA
NC NC NC
P2
P3
1K 25 turns
1K 25 turns
NC
XJ2
XJ8
XJ9
J2 2 GAIN J8 2 SDA J9 2 OA
2
R49
2
2
Jumper
3K9 1%
Jumper
R51 Jumper
CAVALIER
C55 C56
CAVALIER
C125 C126
0R 5% CAVALIER
C127 C128
10nF 100pF
10nF 100pF
10nF 100pF
Schematics
TSEV83102G0B - Evaluation Board User Guide 6-3
SDA
TEST
VIN
GAIN
DIODE
B/GB
F1
SDA
J1
TEST
J16
GAIN
K1
DIODE
L1
B/GB
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C26
100pF
C25
10nF
CAVALIER
B4
BANANA JACK 2mm red / I-DIODE
1
CLK
CLKB
1
1
ClockB
S3
2
2
1
1
VIN
S4
2
2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VPLUSD
VINB
1
1
VINB
S5
A10
B10
C9
C10
F2
F3
G1
G2
G3
H14
H15
H16
K14
L3
L14
L15
M1
M2
M3
M15
M16
P4
P5
P6
P11
P12
P13
TS83102G0
2
XS2
2
VPLUSD VCC
BOUCHON_SMA
VEE
VEE
VEE
XS3
1
1
CAL1
S7
2
R52
0R 5%
ST13
R50
3K9 1%
R54
3K9 1%
BOUCHON_SMA
XS4
2
2
1
2
BOUCHON_SMA
XS5
1
1
CAL2
2
P1
1K 25 turns
S8
1
1
1
1
1
1
BOUCHON_SMA
1
1
1
S1
CONN SMC FC / DRRB
3
3
3
R53
3K9 1%
DRRB
1
3
3 4
3 4
2
5
2 5
1
3
3
VCC
VCC
VCC
VEE VCC VPLUSD
DVEE
C17 C18 C27 C28 C35 C36A C36B
100pF 10nF 100pF 10nF 100pF 10nF 10nF
C29 C30A C30B C31 C32A C32B C21 C22A C22B C19 C20A C20B
100pF 10nF 10nF 100pF 10nF 10nF 100pF 10nF 10nF 100pF 10nF 10nF
C37 C38A C38B C41 C42A C42B C3 C4A C4B
100pF 10nF 10nF 100pF 10nF 10nF 100pF 10nF
10nF
C1 C2 C39 C40 C5 C6 C45 C46 C11 C12 C9 C10
100pF 10nF 100pF 10nF 100pF 10nF 100pF 10nF 100pF 10nF 100pF 10nF
2166D–BDC–01/04

Schematics
Figure 6-3. Component Side Description Figure 6-4. Metal Layer 2 and 4: Ground Planes
Figure 6-5. Metal Layer 3 and 3 bis: Power Supplies
and Ground Planes
Figure 6-7. TSEV83102G0B Evaluation Board: Top View
(Signal Side) without Heatsink
6-4 TSEV83102G0B - Evaluation Board User Guide
2166D–BDC–01/04
Figure 6-6. Metal Layer 5: Solder Side
Figure 6-8. TSEV83102G0B Evaluation Board:
Bottom View

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