User's Manual [PDF - 8.3MB]

VERSION 1.65
June 11, 2003

The DINI Group

The
Group
DN3000k10
User’s Manual
Version 1.65
June 11, 2003
DN3000k10 User’s Manual

The DINI Group

.
The
Group
The information contained within this manual and the accompanying software program are
protected by copyright; all rights are reserved by the DINI Group. Therewith, the DINI group
reserves a the right to make periodic modifications to this project without obligation to
notify any person or entity of such revision. Copying, duplicating, selling, or otherwise
distributing any part of this product without the prior written consent of an authorized
representative of the DINI Group is prohibited.
DN3000k10, DN3000k10S, DN5000k10, DN5000k10S, DN3000k10SD and
DNPCIEXT-S3 are trademarks of the DINI Group.
1010 Pearl Street, Suite #6
La Jolla, CA 92037-5165
www.dinigroup.com
info@dinigroup.com
(858) 454-3419
FAX: (858) 454-1728
Copyright ©2003 The DINI Group. All Rights Reserved.
DN3000k10 User’s Manual

The DINI Group

Table of Contents
Chapter 1
Getting Started
The DINI Group Technical Support . . . . . . . . . . . . . . . 1-1
Relevant Information . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Chapter 2
DN3000k10 Features, Overview and General
Description
DN3000k10 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
DN3000k10 Description . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Easy Configuration via SmartMedia . . . . . . . . . . . . . . . . 2-3
FPGA — VirtexII (U11, U12, U20, U21, U22—A, B,
D, E, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Flip-Flops and LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
I/O Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Bitstream Encryptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
What DES Is. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Programming Encrypted Bitstreams Using JTAG . . . . . . 2-8
Programming Encrypted Bitstreams Using SmartMedia . 2-9
The Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
µP and FPGA Configuration . . . . . . . . . . . . . . . . . . . . 2-9
The µP: Some Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
A/D: Analog to Digital Converter . . . . . . . . . . . . . . . . . . 2-11
J15: Unused µP Connections . . . . . . . . . . . . . . . . . . . . 2-12
ATmega128L JTAG Interface. . . . . . . . . . . . . . . . . . . . . 2-12
Programming the ATmega128L (U3). . . . . . . . . . . . . . . 2-14
Detailed Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
CPLD—XC95288XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Some Miscellaneous Notes on the CPLD . . . . . . . . . . . 2-18
Notes on Header J16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
SelectMAP Configuration Instructions . . . . . . . . . . . . . 2-20
Creating Bit Files for SelectMAP . . . . . . . . . . . . . . . . . . 2-20
Setting up the Serial Port (J30/J34 — RS232 Port) . . . . 2-21
Creating Main Configuration File main.txt . . . . . . . . . . . 2-23
Starting SelectMAP Configuration . . . . . . . . . . . . . . . . . 2-25
DN3000k10 User’s Manual
iii

Description of Main Menu Options . . . . . . . . . . . . . . . . . . 2-26
PC Bit File Sanity Check . . . . . . . . . . . . . . . . . . . . . . . . 2-27
SmartMedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Synthesis and Emulation Issues. . . . . . . . . . . . . . . . 2-29
Synthesis Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Chapter 3
PCI
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
PCI Mechanical Specifications . . . . . . . . . . . . . . . . . . . . 3-1
Some Notes on the DN3000k10 and PCI/PCI-X . . . . . . . 3-1
J33: Present Signals for PCI/PCI-X (Pins 1–2 and 5–6) . 3-5
J33: M66EN—66MHz Enable (Pins 7–8). . . . . . . . . . . . . 3-5
J33: PME–, Power Management Enable (Pin 3) . . . . . . . 3-5
J33: PCI/PCI-X Capability . . . . . . . . . . . . . . . . . . . . . . . . 3-6
J33—PCIXCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Chapter 4
Clocks and Clock Distribution
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Clock Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Orientation and Description. . . . . . . . . . . . . . . . . . . . . . . 4-3
Jumper Control for the Most Common Applications . . 4-4
Ribbon Cable: Providing an Off-Board Clock to the
DN3000k10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
RoboclockII PLL Clock Buffers . . . . . . . . . . . . . . . . . . 4-7
Jumper Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
General Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Feedback and Clock Multiplication . . . . . . . . . . . . . . . . 4-11
Clock Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Clock Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Differential Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Useful Notes and Hints. . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Customizing the Oscillators . . . . . . . . . . . . . . . . . . . . . . 4-14
DN3000k10 PCI_CLK Operation . . . . . . . . . . . . . . . . 4-16
PCI_CLK Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
BCLKOUT and FCLKOUT. . . . . . . . . . . . . . . . . . . . . . . . 4-17
Header Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
DCLK[7](R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
iv
The DINI Group

Chapter 5
Memories
SSRAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
SSRAM Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Pipeline, Flowthrough, ZBT . . . . . . . . . . . . . . . . . . . . . . . 5-9
SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Header Descriptions J19 and J18 . . . . . . . . . . . . . . . . . 5-13
User Notes — DCMs for Clock Management on
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Chapter 6
Power Supplies and Power Distribution
+3.3 V Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
+1.5 V Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Header J21: Off-Board Power . . . . . . . . . . . . . . . . . . . 6-3
Stand-Alone Operation. . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Chapter 7
Daughter Connections to DN3000k10SD—
Observation Daughter Card for 200-pin
Connectors
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Daughter Card LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Connector J8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Connector J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Unbuffered I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Connectors J3, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Connector J5, J6, J7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Buffered I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Passive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
DN3000k10 User’s Manual
v

Daughter Card I/O Connections . . . . . . . . . . . . . . . . . 7-8
Chapter 8
Reset Schemes, LEDs, Bus Bars and 200 Pin
Connectors
Reset Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
J29 — LED Signals Header . . . . . . . . . . . . . . . . . . . . . . . 8-4
Bus Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
The 200 Pin Connectors: J28, J25, J26. . . . . . . . . . . . 8-5
The Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Chapter 9
Utilities
PCI Debug—General Pontificating . . . . . . . . . . . . . . . 9-1
PC-Based—AETEST.EXE. . . . . . . . . . . . . . . . . . . . . . . 9-1
APPENDIX ABerg Connector Datasheets
AETEST Utility Installation Instructions . . . . . . . . . . . . . 9-2
Installation Instructions for DOS. . . . . . . . . . . . . . . . . . . . 9-2
Installation Instructions for Windows NT . . . . . . . . . . . . . 9-2
Installation Instructions for Windows 2000. . . . . . . . . . . . 9-2
Installation Instructions for LINUX . . . . . . . . . . . . . . . . . . 9-3
Installation Instructions for Solaris . . . . . . . . . . . . . . . . . . 9-3
Installation Instructions for Windows 98/ME. . . . . . . . . . . 9-4
AETEST Options: Description and Definitions . . . . . . . 9-4
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
AETEST Main Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
PCI Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Memory Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
vi
The DINI Group

List of Figures
List of Figures
FIGURE TITLE PAGE
2-1 DN3000k10 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2-2 General Slice Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-3 VirtexII Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-4 Dual-Port Data Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-5 Embedded Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-6 Block Diagram of ATmega128L and DN3000k10
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7 J20 Analog to Digital Connections . . . . . . . . . . . . . . . . . . . 2-11
2-8 AVCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-9 J15: Unused µP Connections . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-10 ATmega128L JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-11 J18 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-12 Location of J16 on the DN3000k10 . . . . . . . . . . . . . . . . . . . 2-17
2-13 J16 CPLD JTAG Configuration, FPGA Serial
Configuration and FPGA JTAG Configuration . . . . . . . . . . 2-18
2-14 J30/J34 Serial Port Locations . . . . . . . . . . . . . . . . . . . . . . . 2-22
2-15 Delkin 32 MB 3.3 V Smart Media Card. . . . . . . . . . . . . . . . . 2-29
3-1 FPGA Pin Connections for PCI Signals . . . . . . . . . . . . . . . 3-2
3-2 PCI/PCI-X Edge Connector. . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-3 DN3000k10 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-4 J33 PCI-X Present Header . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-5 PCI-X Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
4-1 Clock Distribution Block Diagram . . . . . . . . . . . . . . . . . . . . 4-2
4-2 Clock Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4-3 Common Clock Configurations . . . . . . . . . . . . . . . . . . . . . . 4-5
4-4 PECL Clock Input and Termination . . . . . . . . . . . . . . . . . . . 4-6
4-5 External Ribbon Cable Connections . . . . . . . . . . . . . . . . . . 4-7
4-6 Functional Diagram of RoboclockII 1 and
RoboclockII 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4-7 Header Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4-8 Clock OE Pin Jumper Settings . . . . . . . . . . . . . . . . . . . . . . 4-15
4-9 PCI_CLK DCM Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
5-1 FPGA Interconnect Block Diagram . . . . . . . . . . . . . . . . . . . 5-2
5-2 SSRAM AB (U8) Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5-3 SSRAM BD (U14) Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 5-4
5-4 SSRAM A2D (U9) Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 5-5
5-5 SSRAM FED (U23) Bus Signals (Page 1 of 2) . . . . . . . . . . . 5-6
5-6 SSRAM FED (U23) Bus Signals (Page 2 of 2) . . . . . . . . . . . 5-7
DN3000k10 User’s Manual
vii

List of Figures
List of Figures (Continued)
FIGURE TITLE PAGE
5-7 Syncburst FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5-8 Syncburst PL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5-9 Syncburst ZBT FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5-10 Syncburst ZBT PL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5-11 Syncburst and ZBT SSRAM Timing . . . . . . . . . . . . . . . . . . 5-10
5-12 SDRAM (U3) Bus Signals (Page 1 of 2) . . . . . . . . . . . . . . . . 5-12
5-13 SDRAM (U3) Bus Signals (Page 2 of 2) . . . . . . . . . . . . . . . . 5-13
6-1 Power Distribution DN3000k10 . . . . . . . . . . . . . . . . . . . . . . 6-1
6-2 Header J21—Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6-3 Molex Connector P1—Auxiliary Power . . . . . . . . . . . . . . . . 6-4
6-4 Example ATX Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 6-4
7-1 DN3000k10SD Daughter Card Block Diagram . . . . . . . . . . 7-2
7-2 DN3000k10 Daughter Card . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7-3 DN3000k10SD Daughter Card Assembly Drawing. . . . . . . 7-4
8-1 Reset Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8-2 DN3000k10 LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8-3 DN3000k10 LED Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8-4 J29 LED Signals Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8-5 91294-003 Pin Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8-6 200 Pin Connectors — Signal Connections . . . . . . . . . . . . 8-8
9-1 AETEST Startup Screen, DN3000k10 Recognized . . . . . . . 9-4
9-2 AETEST Startup Screen, No PCI Peripheral
Recognized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9-3 AETEST Main Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9-4 AETEST PCI Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9-5 AETEST Memory Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9-6 AETEST Write to Memory Test . . . . . . . . . . . . . . . . . . . . . . 9-10
9-7 AETEST Read Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9-8 AETEST Write/Read Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9-9 AETEST Memory Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9-10 AETEST Memory Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9-11 AETEST Write Memory Byte . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9-12 AETEST Read Memory Byte. . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9-13 AETEST Write/Read Memory Byte. . . . . . . . . . . . . . . . . . . . 9-13
A-1 Berg 91403-003 Datasheet Page 1 of 2 . . . . . . . . . . . . . . . . A-2
A-2 Berg 91403-003 Datasheet Page 2 of 2 . . . . . . . . . . . . . . . . A-3
A-3 Berg 91294-003 Datasheet Page 1 of 3 . . . . . . . . . . . . . . . . A-4
viii
The DINI Group

List of Figures
List of Figures (Continued)
FIGURE TITLE PAGE
A-4 Berg 91294-003 Datasheet Page 2 of 3 . . . . . . . . . . . . . . . . A-5
A-5 Berg 91294-003 Datasheet Page 3 of 3 . . . . . . . . . . . . . . . . A-6
DN3000k10 User’s Manual
ix

x
The DINI Group

List of Tables
List of Tables
TABLE TITLE PAGE
2-1 Signals and Connections to J16 . . . . . . . . . . . . . . . . . . . . . 2-17
2-2 FPGA Serial Configuration Header . . . . . . . . . . . . . . . . . . . 2-19
2-3 FPGA JTAG Configuration Header . . . . . . . . . . . . . . . . . . . 2-20
2-4 J17 Configuration Jumper Settings . . . . . . . . . . . . . . . . . . 2-25
2-5 VirtexII FPGA Approximate File Sizes. . . . . . . . . . . . . . . . . 2-28
3-1 Present Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-2 M66EN Jumper Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-3 PCIXCAP Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-4 M66EN and PCIXCAP Encoding . . . . . . . . . . . . . . . . . . . . . 3-7
4-1 Clock Grid Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . 4-3
4-2 Header Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4-3 Jumper Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4-4 Frequency Range Settings. . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4-5 Output Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4-6 Time Unit N-factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4-7 Clock Skew Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4-8 LVPECL Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . 4-13
4-9 Clock OE Pin Jumper Settings . . . . . . . . . . . . . . . . . . . . . . 4-15
5-1 Requirements for Non-Standard SSRAMs . . . . . . . . . . . . . 5-8
5-2 Syncburst and ZBT SSRAM Timing . . . . . . . . . . . . . . . . . . 5-11
6-1 Specification for +3.3 V Power. . . . . . . . . . . . . . . . . . . . . . . 6-2
6-2 Specification for +1.5 V Power. . . . . . . . . . . . . . . . . . . . . . . 6-2
7-1 Connector J8 Pins External Power . . . . . . . . . . . . . . . . . . . 7-5
7-2 DN3000k10SD Daughter Card I/O Interconnects . . . . . . . . 7-8
8-1 J29 Pin Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
DN3000k10 User’s Manual
xi

xii
The DINI Group

Chapter 1
Getting Started
The DN3000k10 is sensitive to static electricity, so treat the PWB accordingly.
The target market for this product is engineers that are familiar
with FPGAs and circuit boards, so a lecture in ESD really isn’t appropriate
(and wouldn’t be read anyway). However, we have sold some of these
units to people who are not as familiar with this issue. The following web
page has an excellent tutorial on the Fundamentals of ESD for those of
you who are new to ESD-sensitive products:
http://www.esda.org/basics/part1.cfm.
The DINI Group Technical Support
Relevant Information
The following means of technical support are available:
1. The DN3000k10 User’s Manual. This is the main source of technical
information. We strive to produce excellent documentation, and this
manual should contain most of the answers to your questions.
2. The DINI Group Web Page. The web page will contain the latest
manual, application notes, FAQ, articles, and any device errata and
manual addenda. Please visit and bookmark:
http://www.dinigroup.com/products/3000k10ns.html.
3. E-Mail to support@dinigroup.com. You may direct questions and
feedback to The DINI Group using this e-mail address.
4. Phone Support. We are happy to help. Call us at (858) 454-3419
during the hours of 8:00 A.M. to 5:00 P.M. Pacific Time. Some of us get
in early and stay late, so you might try us outside of these hours also.
5. Frequently Asked Questions. In the downloads section of our web
page you can find a document called DN3000k10/S Frequently Asked
Questions (FAQ). We will update this document occasionally with
information that may not be in the User’s Manual.
Information about PCI can be obtained from the following sources:
The PCI Special Interest Group has a web page that has lots of good stuff.
Copies of the latest PCI specification may be ordered here.
http://www.pcisig.com/
PCI Special Interest Group
2575 NE Kathryn St. #17
Hillsboro, OR 97124
FAX: (503) 693-8344
DN3000k10 User’s Manual 1-1

Getting Started
As of October 2001, the most current versions of the PCI Specifications are:
PCI Local Bus Specification, Revision 2.2
PCI Hot-Plug Specificadtion, Revision 1.0
PCI Power Management Interface Specification, Revision 1.1
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a
Other recommended specifications include:
PCIMG 2.0 Compact PCI Specification, Revision 2.1 (or greater)
PCI Industrial Computer Manufacturers Group (PICMG)
401 Edgewater Place, Suite 500
Wakefield, MA 01880, USA
TEL: 781-224-1100
FAX: 781-224-1239
http://www.picmg.org
The best book to get if you need an introduction to PCI is:
PCI System Architecture
Fourth Edition
MindShare, Inc.
Tom Shanley and Don Anderson
Ignore some of the ignorant statements made in the Customer Review
section at http://www.amazon.com/. This is an excellent book for PCI and
well worth the money.
The best book to get if you need an introduction to PCI-X is:
PCI-X System Architecture
MindShare, Inc.
Tom Shanely and Karen Gettman
You are going to need to know Verilog or VHDL to use the VirtexII FPGA. If
you need a reference, we recommend the following book for Verilog:
Verilog HDL: A Guide to Digital Design and Synthesis
Samir Palnitkar
ISBN: 0-13-451675-3
If you are one of those people that actually like VHDL, we feel sorry for
you. The following books may be helpful:
Essential VHDL: RTL Synthesis Done Right
Sundar Rajan
The IQ Booster: Improve Your IQ Performance Dramatically
Edwin Breecher
1-2 The DINI Group

Getting Started
Conventions
This manual uses the following conventions. An example illustrates each
convention.
• The term PCI-X will be used generically unless there is a specific
instance where PCI applies.
• This design guide generically refers to PCI-X protocol. When the
PCI-X HalfBridge core is in PCI mode, PCI protocol will be followed.
• Courier font denotes the following items:
– Signals on PCI Bus side of the PCI-X Interface
FRAME_IO (PCI-X Interface signal name)
FRAME# (PCI-X Bus signal name)
– Signals within the user application
BACK_UP, START
– Command line input and output
setenv XIL_MAP_LOC_CLOSED
– HDL pseudocode
assign question = to_be | !to_be;
assign cannot = have_cake & eat_it;
– Design file names
pcim_top.v, pcim_top.vhd
• Courier bold denotes the following items:
– Signals on the user side of the LogiCORE PCI-X Interface
ADDR_VLD
– Menu selections or button presses
FILE -> OPEN
• Italic font denotes the following items:
– Variables in statements which require user-supplied values
ngdbuild design_name
– References to other manuals
See the Libraries Guide for more information.
DN3000k10 User’s Manual 1-3

Getting Started
– Emphasis in text
It is not a bug, it is a feature.
• Dark shading indicates items that are not supported or reserved:
SDONE_I in/out Snoop Done signal. Not
Supported.
• Square brackets “[ ]” indicate an optional entry or a bus index:
ngdbuild [option_name] design_name
DATA[31:0]
• A vertical or horizontal ellipsis indicates repetitive material that
has been omitted.
A B C... X Y Z
• The use of “fn(SIG1. . . SIGn)” in an HDL pseudocode fragment
should be interpreted as “combinational function of signals
SIG1 through SIGn.
SUM = fn(A, B, Cin);
• The prefix “0x” or the suffix “h” indicate hexadecimal notation.
A read of address 0x00110373 returned 45524943h.
• A “#” an “_n” or a “–” means the signal is active low
INT# is active low.
fpga_inta_n is active low.
SRAMCS– is active low.
1-4 The DINI Group

DN3000k10 Features, Overview and General Description
Chapter 2
DN3000k10 Features, Overview and General
Description
DN3000k10 Features
The DN3000k10 features include:
• 32/64-bit, +3.3V, PCI/PCI-X-based PWB with up to five Xilinx VirtexII
FPGAs (FF1152 BGA).
– Initial availability: XC2V6000 and 2V4000 (2V8000 to follow
when available).
• ~3 million ASIC gates per PWB (with 2V6000 — LSI standard)
Device
Flip-Flops
18x18
Multipliers
Embedded
Memory — 18k
bit blocks
XC2V4000 46,080 120 120
XC2V6000 67,584 144 144
XC2V8000 93,184 168 168
• On-board battery supports VirtexII Data Encryption Standard
(DES) Bitstream Encryption
• Fast/Easy FPGA configuration via standard SmartMedia FLASH card
– Microprocessor controlled (ATmega128L)
– RS232 port for configuration/operation status and control
– Fastest possible configuration speed (via SelectMap)
– Partial reconfiguration supported
• 10A on-board linear regulator for +3.3V and +1.5V
– Standalone operation via separate power connector
– +3.3V not needed on backplane
• 6 low skew clocks distributed to all FPGA and test connectors:
– 2 CY7B993/4 RoboclockII PLLs
– 2 socketed oscillators
– PCI Clock
– 1 dividable clock via CPLD
• Direct support for Synplicity’s Certify TDM interconnect
multiplexing.
DN3000k10 User’s Manual 2-1

DN3000k10 Features, Overview and General Description
• Robust observation/debug with 487 connections for logic
analyzer observability or for pattern generator stimulus.
• Status LEDs.
DN3000k10 Description
• User-designed daughter PWB for custom circuitry and interfaces.
• Chipscope fully supported via JTAG interface.
Figure 2-1 shows a block diagram of the DN3000k10.
The DN3000k10 is a complete logic emulation system that enables ASIC or
IP designers a vehicle to prototype logic and memory designs for a fraction
of the cost of existing solutions. The DN3000k10 can be hosted in a 32/64-
bit PCI/PCI-X slot, or can be used as a stand-alone device. A single
DN3000k10 stuffed with five XC2V6000s can emulate up to 3 million gates
of logic as measured by LSI. High I/O-count, 1152-pin, flip-chip BGA packages
are employed. The FF1152 package has 824 I/Os, which allows for
abundant connections to daughter connectors and external memories. A
total of 437 test pins are provided on the top of the PWB via high-density
connectors for logic analyzer-based debugging, or for pattern generator
stimulus. Custom daughter cards such as the DN3k10SD can be mounted
to these connectors as a means of interfacing the DN3000k10 to
application-specific circuits. A reference 32-bit PCI target design and test
bench is provided in Verilog at no additional cost.
Smart Media
Card
16/32/64 Mbyte
(FPGA configuration
storage)
RS232
2
32kx8 SRAM
ATmega103L
Flash-based µP
FPGA
Configuration
Controller
95288XL
CPLD
20
FPGA
Configuration
+5V
Switching
Power
Supply
+3.3V (10A)
+1.5V (10A)
+5V
-12V
+12V
+3.3V
+1.5V
FB
SDRAM
(168 pin DIMM Module)
Up to 1GB x 64
ECLK
FPGA
A
XC2V6000
(FF1152)
145
AF
AB
127
FB
110
AE
MB [226:0]
115
FPGA
B
XC2V6000
(FF1152)
BE
89
70
A2D
74
FlowThrough/
Pipelined
SSRAM
512k x 36
ECLK
ECLK
FlowThrough/
Pipelined
SSRAM
512k x 36
70
176
BD
A2D
FlowThrough/
Pipelined
SSRAM
512k x 36
ECLK
AB
AE
BD
FB
MB
clocks
AHDR
BHDR
DHDR
EHDR
57
56
41
1
75
16
75
49
58
8
Top of PWB
Reset
Control
(test connectors)
FPGA
F
XC2V6000
(FF1152)
EF
102
FPGA
E
XC2V6000
(FF1152)
ED
152
FPGA
D
XC2V6000
(FF1152)
ACLK
BCLK
CCLK
DCLK
ECLK
config
Roboclock
PLL
1
Roboclock
PLL
2
Clock
Selection
Jumpers
or
External
Cable
OSC
X1
OSC
X2
92
32/64-Bit PCI/PCI-X
FED
84 70
ECLK
FlowThrough/
Pipelined
SSRAM
512k x 36
config
rev 5/30/03
Figure 2-1 DN3000k10 Block Diagram
2-2 The DINI Group

DN3000k10 Features, Overview and General Description
Easy
Configuration
via
SmartMedia
The configuration bit files for the FPGA are copied onto a 32-megabyte
SmartMedia FLASH card (provided) and an on-board microprocessor
controls the FPGA configuration process. Visibility into the configuration
process is enhanced with an RS232 port. Sanity checks are performed automatically
on the configuration bit files, helping to avoid the timeconsuming
process of debugging the configuration process. FPGA configuration
runs quickly at 48 MHz. Eight LEDs provide instant status and operational
feedback. Two of these LEDs are connected to the CPLD and can be
user-configured.
FPGA — VirtexII (U11, U12, U20, U21, U22—A, B, D, E, F)
The DN3000k10 contains two to five Virtex II FPGAs. They are called A, B,
D, E, and F. The package is a flip chip fine-pitch BGA with 1152 pins
(FF1152). The pitch on the pins is 1 mm. This isn’t important, but this pin
density makes the PWB a bitch to layout. Keep that in mind if you try to
make one of these at home. Most of the 824 I/O pins are utilized on the
FF1152 package. The DN3000k10 can be stuffed with any combination of
the 2V4000s, 2V6000s, and 2V8000s. The 2V3000 does come in an FF1152,
but since it has fewer I/O pins, it should not be used. The standard speed
grade we stuff is –4. We can use the –5 and –6 speed grades, but don’t fall
out of your chair when you get the price. Note that Xilinx has cancelled
plans for the 2V10000. Even though this part appears in some Xilinx literature,
we have been told that the 2V8000 is the largest part that the
process will handle. Don’t expect to see anything larger than the 2V8000
until the 2003 time frame.
What happened to C We struggled with the layout for many
months, which gave the buffoons in marketing time to rethink what they
asked for. As is normally the case with marketing, after a few drinks they
decided to change the requirements. The FPGA that originally was in the C
position was eliminated and replaced with the four SSRAMs and a SDRAM
DIMM. So much work had been done to that point that those of us in engineering
didn’t think it wise to re-label the FPGAs. That is why no FPGA_C
exists.
The following is a very brief overview of the VirtexII family. More information
can be gleaned from the Virtex II Datasheet
(VirtexII-Datasheet.pdf) and the VirtexII User’s Guide
(VirtexII-UserGuide.pdf). Both files are on the CD-ROM supplied with
the DN3000k10, but you are better off getting the latest versions from the
Xilinx Web page (http://www.xilinx.com/). Make sure to get the latest
errata sheet also.
Flip-Flops and
LUTs
Figure 2-2 shows what Xilinx calls a slice. Each slice contains 2 flip-flops. A
configurable logic block (CLB) contains 4 slices. The XC2V6000 is a 96 x 88
grid of CLBs. Therefore, the XC2V6000 contains 67,584 flip-flops. This flipflop
count does not include the six flip-flops contained in each I/O block.
Each flip-flop has a 4 x 1 look up table (LUT). An LUT can do any Boolean
function of the four inputs. The rest of the multiplexers allow for carry
chains and other functions. An overview of the VirtexII Architecture is
shown in Figure 2-3.
DN3000k10 User’s Manual 2-3

DN3000k10 Features, Overview and General Description
G
inputs
LUT
D
D Q
FF/LAT
CE
CLK
SR REV
YQ
BY
MUXF5
F5
X
LUT
F
inputs
D
DX
D Q
FF/LAT
CE
CLK
SR REV
XQ
BX
CE
CLK
SR
Figure 2-2 General Slice Diagram
Global Clock Mux
DCM DCM IOB
Configurable Logic
Programmable I/Os
CLB
Block SelectRAM
Multiplier
Figure 2-3 VirtexII Architecture Overview
2-4 The DINI Group

DN3000k10 Features, Overview and General Description
Embedded
Memory
VirtexII has boatloads of embedded memory. The XC2V6000 contains 144,
18-Kbit blocks. Each memory block can be configured as 16K x 1, 2K x 9,
8K x 2, 1K x 18, 4K x 4 or 512 x 36. Remember that unused LUTs may also
be used as memory. Xilinx refers to the embedded memory as Block
SelectRAM, and to the LUT-based memory as Distributed Memory. The
embedded memory is dual-ported and quite flexible. Virtually any type of
memory can be constructed—FIFOs, dual-port RAMs, single-port RAMs, etc.
The 18 Kb block SelectRAM dual-port memory consists of an 18 Kb storage
area and two completely independent access ports, A and B. The structure
is fully symmetrical, and both ports are interchangeable. See Figure 2-4
for a diagram of the memory.
18-Kbit Block SelectRAM
DIA
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
Port A
18 Kb
Memory
Array
Port B
DOA
DOPA
DOB
DOPB
Figure 2-4 Dual-Port Data Flows
Data can be written to or read from either port in almost any combination.
Each port is synchronous, with its own clock, clock enable, and write
enable. Note that the read operation is also synchronous and requires a
clock edge.
We have found that a functional description of the memory is sufficient
for the synthesis tools to recognize the memories and implement the
embedded blocks. More on the synthesis issues in “Synthesis and Emulation
Issues” on page 2-29.
Multipliers
VirtexII devices feature a large number of embedded 18-bit x 18-bit two’s
complement embedded multipliers (see Figure 2-5). The XC2V6000
contains 144 of these; the XC2V4000 contains 120. The embedded
multipliers offer fast, efficient means to create 18-bit by 18-bit signed
DN3000k10 User’s Manual 2-5

DN3000k10 Features, Overview and General Description
multipliers. The multiplier blocks share routing resources with the Block
SelectRAM memory, allowing for increased efficiency for many applications.
Cascading of multipliers can be implemented with additional logic
resources of VirtexII slices.
Applications such as signed-signed, signed-unsigned, and unsignedunsigned
multiplication, logical, arithmetic, and barrel shifters, two’s
complement and magnitude return are easily implemented.
We were surprised to find that the synthesis tools had no problem recognizing
multipliers in Verilog and VHDL. So it appears that functional RTL is
all that is necessary to use the embedded multipliers. More on the
synthesis issues in “Synthesis and Emulation Issues” on page 2-29.
18
A
18
P = A • B
36
P
B
MULT18X18
Figure 2-5 Embedded Multiplier
I/O Issues
Digitally Controlled Impedance (DCI) is supported on all pins. The resistors
used for VRN and VRP are 51.1 ohms 1%. The PWB impedance is 60 ohms.
So the Xilinx tools should be adjusted to reflect the fact that the reference
resistors match the board impedance (and NOT half the resistance of the
reference resistors). DCI is a very nice feature and we recommend you use
it on all I/O signals. The correct IOATTRIBUTE standard for the UCF file is
LVDCI_33.
All VCCO pins are connected to +3.3 V. The VREF pins are used as I/Os, so the
DN3000k10 does not support I/O standards that require VREF. No signals
have a V TT (Board Termination Voltage). So the I/O standards supported
are:
LVTTL — Low-Voltage TTL
The low-voltage TTL, or LVTTL, standard is a general-purpose EIA/JESDSA
standard for 3.3 V applications that use the LVTTL input buffer and a Push-
Pull output buffer. The standard requires a 3.3 V input and output source
voltage (V CCO ) but does not require the use of a reference voltage (V REF )
or a termination voltage (V TT ).
LVCMOS33 — 3.3 Volt Low-Voltage CMOS
This standard is an extension of the LVCMOS standard (JESD8. –5). It is used
in general-purpose 3.3 V applications. The standard requires a 3.3 V
input/output source voltage (V CCO ) but does not require the use of a reference
voltage (V REF ) or a termination voltage (V TT ).
PCI-X — Peripheral Component Interface
The PCI standard specifies support for 33 MHz, 66 MHz and 133 MHz PCI
2-6 The DINI Group

DN3000k10 Features, Overview and General Description
bus applications. It uses a LVTTL input buffer and a Push-Pull output buffer.
This standard does not require the use of a reference voltage (V REF ) or a
board termination voltage (V TT ); however, it does require 3.3 V input
output source voltage (V CCO ).
LVDS is supported on some pins to the 200–pin connectors. See “The 200
Pin Connectors: J28, J25, J26” on page 8–5.
Bitstream
Encryptions
VirtexII devices have on-chip decryption circuitry that can be enabled to
make the configuration bitstream (and thus the whole logic design)
secure. Ultimately, you will be able to encrypt the bitstream in the Xilinx
software, and the VirtexII chip will perform the reverse operation,
decrypting the incoming bitstream and internally recreating the intended
configuration. The DN3000k10 has a battery socket to support this
function.
Encrypting the bitstream is important if you want to use the DN3000k10
as a platform to demonstrate intellectual property (IP) but don’t want
anybody reverse engineering the bitstream in an attempt to steal the
design.
NOTE: It is possible to recreate a design from the configuration
bitstream!
This method provides a very high degree of design security. Without
knowledge of the encryption/decryption key or keys, potential pirates
cannot use the externally intercepted bitstream to analyze, or even to
clone the design. System manufacturers can be sure that their VirtexII
implemented designs cannot be copied and reverse engineered.
The VirtexII devices store the internal decryption keys in a few hundred
bits of dedicated RAM, backed up by a small externally-connected battery
(BTI on the circuit board). At less than100 nA per load, the endurance of
the battery is limited only by its shelf life.
The method used to encrypt the data is Data Encryption Standard (DES).
This is an official standard supported by the National Institute of Standards
and Technology (NIST) and the U.S. Department of Commerce. DES is
a symmetric encryption standard that utilizes a 56-bit key. Because of the
increased sophistication and speed of today’s computing hardware, single
DES is no longer considered to be secure. However, the Triple Data Encryption
Algorithm (TDEA), otherwise known as triple DES, is authorized for
use by U.S. federal organizations to protect sensitive data, and is used by
many financial institutions to protect their transactions. Triple DES has yet
to be cracked. Both DES and Triple DES are available in VirtexII devices.
What DES Is
DES and Triple DES are symmetric encryption algorithms. This means that
the key to encrypt and the key to decrypt are the same. The security of the
data is kept by keeping the key secret. This contrasts to a public key
system, like RSA or PGP. One thing to note is that VirtexII devices use DES in
Cipher Block Chaining mode. This means that each block is combined with
DN3000k10 User’s Manual 2-7

DN3000k10 Features, Overview and General Description
the previous encrypted block for added security. DES uses a single 56-bit
key to encrypt 64-bit blocks one at a time.
This section is being updated mid-March 2002. At this time, only the Xilinx
tools version 4.2 (or a patched 4.1.03) support the encryption function of
the Virtex II devices. There are various erratas, updates, and white papers
available at the Xilinx web site (http://www.xilinx.com). Also, our most
updated information regarding using Virtex II devices with encryption can
be found at our web site at:
http://www.dinigroup.com/products/3000k10ns.html.
As of now, encryption is fully supported using the JTAG chain programming
the parts. Encryption using SmartMedia programming will be
supported soon. We have found several undocumented features of the
Xilinx Virtex II parts with SelectMAP programming that we are now
working to accommodate.
Note that encryption and partial reconfiguration are mutually exclusive.
You can do one or the other, but not both. There is also a previous errata
on the sizes of bit files generated for Virtex II parts being larger than the
originally-intended size by approximately 10%. This does NOT apply to
encrypted bitstreams. The size of an encrypted bit file is the originallyintended
size.
For more detailed information regarding Virtex II parts and encryption,
see our Encrypted Bitstream documentation at:
http://www.dinigroup.com/products/3000k10ns.html.
Programming Encrypted Bitstreams Using JTAG
1. Creating the Encrypted Bitstreams
A new option has been added to the Xilinx “bitgen” utility for all
devices that support encryption. Add the “-g Encrypt:Yes” option
to the “bitgen” command line (see Xilinx User’s Guide) to create an
encrypted bitstream.
Two files will be created. The first is the encrypted bit file. the second
is a key file, “.nky” (which you can specify using the “-g Key-
File:” option). The key file contains the
encrypt/decrypt keys used to encrypt/decrypt the bit file.
2. Programming the Key File
Using the Xilinx iMPACT tool and a JTAG programmer, program the
key file “.nky” into the FPGA that will decrypt the encrypted bitstreams.
Make sure that a +3 V 2032-type lithium coin battery is
installed in BT1 prior to programming. The battery is required for
key-retention.
3. Programming the Encrypted Bitstreams
Using the Xilinx iMPACT tool and a JTAG programmer, program the
encrypted bitstreams into the FPGA. The FPGA will then decrypt the
bitstream using the previously-programmed decryption keys.
2-8 The DINI Group

DN3000k10 Features, Overview and General Description
Programming Encrypted Bitstreams Using SmartMedia
The procedure for this is very similar to the procedure for JTAG. However,
support for this is not complete and will be coming shortly. For more
detailed information, contact us directly or visit our web site at:
http://www.dinigroup.com/products/3000k10ns.html.
The Battery The DN3000k10 has a socket for a battery, BT1. The socket uses a +3 V,
2032 coin-style lithium battery. Don’t eat the battery. Most lithium
batteries are rated at about 200 mAh, so at 100 nA, the battery should last
for 5 years or so.
µP and FPGA Configuration
The DN3000k10 has an ATmega128L microprocessor (µP) that is used to
control the configuration process (U3). The amount of internal SRAM
(4 Kbytes) was not large enough to hold the FAT needed for SmartMedia,
so an external 32 k x 8 SRAM was added. The address latching function is
done via an LVX373 (U6).
The microprocessor has the following responsibilities:
• Reading the SmartMedia card
• Configuring the VirtexII FPGA
• Executing DN3000k10 self tests.
Other than FPGA configuration, the µP has no responsibilities. Less than
25% of the 128 Kbytes of FLASH is used for FPGA configuration and utilities,
so you are welcome to use the rest of the resources of the µP for your
own purposes. Instructions for customizing the µP are contained in the file
Custom_Atmega128L.pdf. This file is on the CD-ROM, or it can be downloaded
from the DINI Group web page.
REMEMBER: You can use the microprocessor for your own purposes!
We ship a programming cable for the ATmega128L with the DN3000k10.
Updates to the code will be posted on our web site. If you wish to do your
own development you will need the compiler, which we do not ship with
the product. The compiler is available from IAR (http://www.iar.com/).
The part number is EWA90PCUBLV150.
Note that if you are willing to program the FPGA with the JTAG or serial
cable, the CLPD and the µP have no function. In this case you can use all of
the resources of the µP for your own purposes.
The µP: Some
Details
The ATmega128L is gross overkill for the FPGA configuration function. The
datasheet and user’s manual are on the CD-ROM that was shipped with the
DN3000k10. The file names are ATmega128_UM.pdf and
atmega128_DS.pdf. But if you intend to use the µP for your own
purposes, you should check the Atmel web page to get a copy of the latest
user’s manual, datasheet, and erratas. The Atmel web page is
DN3000k10 User’s Manual 2-9

DN3000k10 Features, Overview and General Description
http://www.eu.atmel.com/atmel/. The ATmega128L is under the section
called “Flash Microcontroller, AVR 8-Bit RISC.” Most of the features are
unused. A variety of test headers allow for possible use of these features.
Each header and the various possible functions are described in the
sections that follow. Figure 2-6 is a block diagram of the ATmega128L and
its various interfaces on the DN3000k10.
+3.3V Noise
Conditioner
AREF
AVCC
A/D Inputs or
User I/O
µP
JTAG
J20
General
Purpose I/O
J15
CSF*
FWRTSM
DOUTBSYF
D [7:0]
CSA*
FPGA
F
(U22)
J30
RS232
Connector
J34
J2
Config.
Jumpers
top
bottom
Card
Inserted
JMPR [2:0]
RS232
Level
Translator
ICL3221
Programming
Header
J18
J16
Programming
Header
T x
R x
Smart
Media
Reset
Switch
Atmel AVR
ATmega128L
µP
128kbytes FLASH
4kbytes SRAM
4kbytes EEPROM
U3
32.768MHz
Crystal
TOD Y1
S1
A/D
+5V
+3.3V
+1.5V
WR*
RD*
ALE
µPADDR[14:8]
U2
Reset & Power
Threshold Detection
X3
SRAM
32kx8
U6
48MHz
Osc
µPAD[7:0]
µPADDR[7:0]
8 MHz
PWR RST-
XC95288XL
CPLD
U13
6
DOUTBSYA
CSB*
DOUTBSYB
CSD*
DOUTBSYD
CSE*
DOUTBSYE
LED[3:0]
4
LED4
U17
U19
FPGA
A
(U11)
FPGA
B
(U12)
FPGA
D
(U21)
FPGA
E
(U20)
LED5
LOCK1#
LOCK2#
Figure 2-6 Block Diagram of ATmega128L and DN3000k10 Interfaces
2-10 The DINI Group

DN3000k10 Features, Overview and General Description
A/D: Analog to
Digital
Converter
J20 connects to the A/D inputs of the ATmega128L. Header pins for AVCC
and AREF are also provided if you wish to use AVCC elsewhere, or want to
provide a cleaner AREF to the µP. The odd pins of J20 are grounded,
making for a clean connection with an IDC cable. The eight A/D pins
(UPADC[7:0]) may also be used as TTL I/O. UPADC[7:4] also may be used
to connect to the JTAG port of the ATmega128L (See “ATmega128L JTAG
Interface” on page 2–12.).
According to the Atmel documentation, the following features apply to
the A/D:
• 10-bit Resolution
• 0.5 LSB Integral Non-linearity
• ±2 LSB Absolute Accuracy
• 8 Multiplexed Single Ended Input Channels
• 7 Differential Input Channels
• 2 Differential Input Channels with Optional Gain of 10x and 200x
• Optional Left Adjustment for ADC Result Readout
• 0–VCC ADC Input Voltage Range
• Selectable Internal 2.56 V ADC Reference Voltage
• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceller
The J20 Connections are shown in Figure 2-7. The AVCC port connections
are shown in Figure 2-8.
+3.3 V is filtered via a 100µH (L2) inductor. The output is AVCC (analog
VCC). Inductor L2 is rated 120 ma. VREF is the result of a resistor division of
R13 and R7. The DN3000k10 is shipped with 30 ohm, 1% resistors (size
1210) in these locations, resulting in an AREF voltage of AVCC/2 or approximately
1.65 V. If you wish to supply your own AVCC and VREF voltages,
J20
1
3
5
7
9
11
13
15
17
19
HDR10X2
2
4
6
8
10
12
14
16
18
20
(TCK)
(TMS)
(TDO)
(TDI)
AVCC
AREF
UPADC0
UPADC1
UPADC2
UPADC3
UPADC4
UPADC5
UPADC6
UPADC7
+3.3V
61
60
59
58
57
56
55
54
52
21
PF0/ADC0
PF1/ADC1
PF2/ADC2
PF3/ADC3
PF4/ADC4/TCK
PF5/ADC5/TMS
PF6/ADC6/TDO
PF7/ADC7/TDI
VCC
VCC
µP
JTAG
Interface
U3
ATmega103L-4AC
Figure 2-7 J20 Analog to Digital Connections
DN3000k10 User’s Manual 2-11

DN3000k10 Features, Overview and General Description
AVCC
L2
100µH
+3.3V
U3
ALE
RD
WR
AREF
AGND
AVCC
AD0/PA0
AD1/PA1
AD2/PA2
43
34
33
62
63
64
51
50
49
ALE
RD-
WR-
AREF
AVCC
UPAD0
UPAD1
UPAD2
R13
30.0 1% 1210
R7
30.0 1% 1210
C27
0.1µF
Figure 2-8 AVCC Connections
remove L2, R13, and R7, and input your signals on J20 pins 18 and 20.
Remember that the ATmega128 also has an internal reference voltage of
2.56 V. If you use the internal 2.56 V reference, leave C27 stuffed. Atmel
documents state that externally decoupling AREF will improve the noise
performance of the A/D.
J15: Unused µP
Connections
J15 contains connections to the ATmega128L that were not used elsewhere.
These ten connections can be used for external TTL connections to
the µP, externally generated interrupts, or any other function that the
ATmega128L supports on these pins. Remember that the ATmega128L is
not +5 V tolerant, so if you attach external TTL signals to these pins, the
voltage level of these signals must not exceed +3.3 V.
The J15 schematic is shown in Figure 2-9.
ATmega128L JTAG Interface
The ATMega128L processor has a JTAG interface that can be used for onchip
debugging, real-time emulation, and programming of FLASH,
EEPROM, fuses, and Lock Bits. In order to take advantage of the JTAG interface,
you must have the Atmel AVR JTAG ICE kit (part number ATAVR-
JTAGICE) and AVR studio software that Atmel provides free at
www.atmel.com. The JTAG interface for the ATmega128L can be accessed
through four pins (TCK, TMS, TDO and TDI) on header J20 of the
DN3000k10 (see Figure 2-10).
2-12 The DINI Group

DN3000k10 Features, Overview and General Description
J15
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
HDR13X2
UPINT5
UPINT6
UPINT7
SS
SO
SI
SCK
SMCD-
SMWP1-
UP5
UP6
UP7
UP8
UP9
UP10
BRXD
BTXD
JMPR0
JMPR1
JMPR2
UPINT5
UPINT6
UPINT7
25
26
27
28
29
30
31
32
2
3
4
5
6
7
8
9
PD0/INT0
PD1/INT1
PD2/INT2
PD3/INT3
PD4/IC1
PD5
PD6/T1
PD7/T2
PE0/(PDI/RXD)
PE1/(PDO/TXD)
PE2/AC+
PE3/AC-
PE4/INT4
PE5/INT5
PE6/INT6
PE7/INT7
Figure 2-9 J15: Unused µP Connections
J20
1
3
5
7
9
11
13
15
17
19
HDR10X2
2
4
6
8
10
12
14
16
18
20
TCK
TMS
TDO
TDI
AVCC
AREF
Figure 2-10 ATmega128L JTAG Interface
DN3000k10 User’s Manual 2-13

DN3000k10 Features, Overview and General Description
Programming
the
ATmega128L
(U3)
A cable used to reprogram the ATmega128L is shipped with the
DN3000k10. You will need to reprogram the ATmega128L if we update
the code or you intend to use the processor for your own application. J18
is used for this purpose.
Figure 2-11 illustrates J18.
BRXD
PWRRST-
SCK
BTXD
J18
1
3
5
7
9
HDR5X2
2
4
6
8
10
+3.3V
Detailed Instructions
1. Download the latest update for the processor and CPLD at www.dinigroup.com
(file uP_CPLD.zip).
2. You will first need to reprogram the CPLD. Please see “CPLD—
XC95288XL” on page 2-16 for instructions (use the file
DNk10S_CPLD.jed that can be found in the downloaded zip file.
3. Next, you will program the processor (ATmetga128L). Connect the
AVR cable that was shipped with the DN3000k10 to header J18 with
the red/purple wire on the cable connected to pin 1 and connect the
other end to the serial port of your PC.
4. In order to program the processor, you will need to install AVR Studio
that is included on the Atmel CD that was shipped with the
DN3000k10. This software can also be downloaded at
www.atmel.com.
5. From the Windows START menu, choose PROGRAMS–>Atmel AVR Studio
x.xx (where x.xx is the version number).
6. Once AVR Studio is open, select TOOLS–>STK500/AVRISP/JTAG ICE and
a new window should appear with the title STK500. At the bottom of
the STK500 window, if you see:
Detecting…FAILED!
Figure 2-11 J18 Schematic
that means either there is no power on the DN3000k10, there is
another program open that is using the serial port, or the serial cable
connecting the AVR tool is not connected properly. If this happens,
you should close down the window titled STK500, correct the situation,
and then select TOOLS–>STK500/AVRISP/JTAG ICE again. You
will not be able to continue unless you see something very similar to
the following at the bottom of the STK500 window:
2-14 The DINI Group

DN3000k10 Features, Overview and General Description
Detecting…AVRISP found on COM1:
Getting revisions…HW: 0x01, SW Major: 0x01, SW
Minor: 0x07…OK
7. On the PROGRAM tab, select the ATmega128 under the DEVICE drop
down menu, and in the FLASH section where it says INPUT HEX FILE,
browse and select the file DN3000k10_128.a90 that can be found in
the downloaded zip file (uP_CPLD.zip) from the Dini Group website.
To program the device all you need to do is hit the PROGRAM button
in the FLASH section. When the programming is complete (it takes
about 45 seconds) you should see a message at the bottom of the
window that looks something like this:
Detecting…AVRISP found on COM1:
Getting revisions…HW: 0x01, SW Major 0x01, SW
Minor: 0x07…OK
Reading FLASH input file…OK
Setting device parameters, serial programming
mode…OK
Entering programming mode…OK
Erasing device…OK
Programming FLASH using block mode…100% OK
Leaving programming mode…OK
8. After programming the processor, close all AVR Studio windows and
setup the serial port according to the section titled “Setting up the
Serial Port (J30/J34 — RS232 Port)” on page 2-21. Please note that in
this situation, connecting the serial port is mandatory and the FPGA
cannot be configured via the SmartMedia card until you have completed
all the instructions in this section.
9. Reset the DN3000k10 by pressing S1. After about 10 seconds, you
should see the following in the HyperTerminal window:
**********NEED FPGA STUFFING INFORMATION*********
Enter number of FPGAs on Board (1–6):
Using the keyboard, enter the number of FPGAs on the board (should
be between 1 and 5 for the DN3000k10). After you have entered this,
you should see the following menu:
1) Virtex II 1000 (FG456)
2) Virtex II 6000 (FF1152)
3) Virtex II 4000 (FF1152)
4) Virtex II 3000 (FG676)
Please enter selection (1–4) for FPGA F:
Enter the type of FPGA that is stuffed on your DN3000k10. If you enter
the wrong type of FPGA or the incorrect number of FPGAs on the
board, then you will need to reprogram the processor and follow
these steps again.
DN3000k10 User’s Manual 2-15

DN3000k10 Features, Overview and General Description
10. The processor and the CPLD are now ready to configure the FPGA(s).
Please see the section titled “Starting SelectMAP Configuration” on
page 2-25 for further instructions.
CPLD—
XC95288XL
Some non-volatile logic is needed to handle the counters and state
machines associated with the high-speed interface to the SmartMedia
card. We used an XC95288XL CPLD from Xilinx for this function. The
datasheet is on the CD-ROM and is titled xc95288xl.pdf. Approximately
90% of the resources of this device are utilized, so 10% are available for
your own purposes. The Verilog source for the CPLD is provided on the CD–
ROM. The file name is CPLD.V.
The CPLD performs the following functions:
• Level Translation and logic inversion for LED[5:0], LOCK_N[2:1]
• µP SRAM Interface:
– µP upper/lower address latch for 32K x 8 SRAM (U5):
UPADDR[14:0]
– SRAMCS–
• Interface to ATmega128L µP
– Data Bus: UPAD[7:0]
– Control: ALE, RD–, WR–
– Clock: CPUCLK
• Interface to FPGA configuration signals
– PROG–, DOUTBSYF, INITF–, DONEF
– M[2:0]
– SelectMap Interface
+ Data Bus: {D[7:1], DIND0F}
+ Chip Select: CSF–
+ Read/Write: FWRTSM–
– JTAG: FTMS, FTDO, FTDI, FTCK
• Interface to SmartMedia Card
– Data Bus: SMRTMED[7:0]
– Control: SMCLE, SMALE, SMWE–, SMWP–, SMCE–, SMRE–,
RDYBUSY–
• Interface to Serial FPGA Configuration Cable:
– C_DONE, C_DIN, C_PROG–, C_INIT–, C_CCLK
We may periodically update the CPLD. The CPLD can be reprogrammed
using the Xilinx JTAG cable supplied with the DN3000k10. The connections
are on the 90° header on the top of the PWB labeled J16. The relevant
signals and the connections to J16 are listed in Table 2-1. Figure 2-12
shows the location of J16. With the exception of V CC and GND, you will find
that the signals are placed on the connector in the same order as the JTAG
cable. A schematic of J16 is shown in Figure 2-13.
2-16 The DINI Group

DN3000k10 Features, Overview and General Description
Table 2-1 Signals and Connections to J16
JTAG Cable Color J16 Signal Name J16 Pin
VCC Red +3.3 V 1, 2, 3, or 4
GND Black GND 5, 6, 17, 19, 21 or 24
TCK Yellow CPLD_TCK 8
TDO Purple CPLD_TDO 10
TDI White CPLD_TDI 12
TMS Green CPLD_TMS 14
J16
Figure 2-12 Location of J16 on the DN3000k10
DN3000k10 User’s Manual 2-17

DN3000k10 Features, Overview and General Description
+3.3V
C_CCLK
C_DONE
C_DIN
C_PROG-
C_INIT-
J16
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
HDR12x2 90 DEG M
+3.3V
CPLD_TCK
CPLD_TDO
CPLD_TDI
CPLD_TMS
FTCK
FTDO
FTDI
FTMS
Figure 2-13 J16 CPLD JTAG Configuration, FPGA Serial
Configuration and FPGA JTAG Configuration
Some Miscellaneous Notes on the CPLD
X3 is a 48 MHz oscillator. This part is soldered down to the PWB and is not
intended to be user-configurable. The 48 MHz is divided down to 8 MHz
in the CPLD to provide the clock for the ATmega128L µP. The processor
clock signal is labeled CPUCLK (and BCPUCLK) on the schematic, and may
have a note that describes the frequency as 4 MHz. Initially, we used an
ATmega103L instead of the ATmega128L. The ATmega103L maximum
frequency was 4 MHz.
The 48 MHz is used directly for the state machines in the CPLD for controlling
the interface to the SmartMedia card. The frequency of 48 MHz is
interesting because it is the closest frequency to 50 MHz that can be
divided by an integer to get 8 MHz. The frequency 50 MHz is the fastest
that the Xilinx VirtexII parts can be configured with SelectMap without
wait states. So FPGA configuration using SelectMap occurs at very nearly
the fastest theoretical speed.
Serial and JTAG configuration of the VirtexII FPGA are back off positions
only—that is why those signals are connected to the CPLD. Xilinx has a
long history of botching the configuration method in new FPGA families,
so we made sure we had all possible options available.
If you want to use 100% of the CPLD and µP for your own purposes, you
can configure the FPGA using the JTAG cable.
The 48 MHz clock can be divided down in the CPLD and used to drive the
PWB clock network. See Chapter 4 for a more detailed description of this
option.
2-18 The DINI Group

DN3000k10 Features, Overview and General Description
LOCK_N[2:1] are the logical invert of LOCK[2:1]. The lock LEDs should
go on when the respective RoboclockII PLLs are locked.
Notes on Header J16
SelectMap using the SmartMedia card is the best way to configure the
FPGA. Two other options exists if, for some reason, the SmartMedia media
method is not working.
1. Serial Programming Using the Cable. Header J16 has the 5 serial connections
that are used to configure the FPGA using the serial method.
Table 2-4 has the pinouts. Note that this is a back-off position to
SmartMedia and JTAG and should only be used in dire circumstances.
Note also that header J17 will need to change to reflect “slave-serial”
configuration.
Table 2-2 FPGA Serial Configuration Header
Name on
Schematic:
Name on
Cable
Cable Color
Header Pin
C_CCLK CCLK yellow J16.7
C_DONE D/P blue J16.9
C_DIN DIN green J16.11
C_PROG– PROG orange J16.13
C_INIT– (none) (none) J16.15
GND GND black J16.5, J16.17,
J16.19, J16.21,
J16.6, J16.24
VCC +3.3V red J16.1, J16.2,
J16.3, J16.4
2. JTAG Programming.
The JTAG connection can be used to configure the FPGA and can also
be used to connect the ChipScope ILA Logic Analyzer
(www.xilinx.com/xlnx/xil_prodcat_product.jsptitle=chipscope_ila)
or other solutions such as the Bridges2silicon system (see
www.bridges2silicon.com). The JTAG method of configuration should
be used if the SmartMedia method isn’t working. Remember that a
DN3000k10 User’s Manual 2-19

DN3000k10 Features, Overview and General Description
different bit file is necessary — the bit file must use the JTAG clock for
configuration. Table 2-3 has the pinouts.
Table 2-3 FPGA JTAG Configuration Header
Name on
Schematic
Name on
Cable
Cable Color
Header Pin
FTCK TCK yellow J16.16
FTDO TDO purple J16.18
FTDI TDI white J16.20
FTMS TMS green J16.22
GND GND black J16.5, J16.17,
J16.19, J16.21,
J16.6, J16.24
VCC +3.3V red J16.1, J16.2,
J16.3, J16.4
SelectMAP
Configuration
Instructions
The FPGA on the DN3000k10 can be configured in SelectMAP mode using
a Smart Media card. SelectMAP configuration is the easiest and quickest
way to configure the FPGA. The DN3000k10 is shipped with two 32 MB
Smart Media cards. One of these Smart Media cards contains a reference
design bit file produced for SelectMAP configuration, and a file main.txt
that sets options for the configuration process (for description of options,
see “Creating Main Configuration File main.txt” on page 2-23). This Smart
Media card has been marked as read-only by the silver, circular sticker on
the card. The other Smart Media card is empty and is for use with your
own designs. To configure the FPGA with the reference design, please skip
to “Starting SelectMAP Configuration” on page 2-25.
Creating Bit Files for SelectMAP
Create bit files with Xilinx 3.3i with service pack 8 or Xilinx ISE 4.x
• Use Xilinx 3.3i with service pack 8 and the patch for VirtexII (see
http://support.xilinx.com/techdocs/11805.htm) or Xilinx ISE 4.
For Xilinx 3.3i Design Manager:
• After creating a project in Xilinx, go to the menu
Design/Options and choose Edit Options for
Configuration and uncheck the box. Enable the Power Down
Status pin (Done pin) on the Configuration tab. Also
make sure that on the Startup tab, the Startup Clock is CCLK.
For Xilinx ISE 4.x Design Manager:
• After creating a project in Xilinx, go to the menu
Design/Options and choose Edit Options for Configuration
and go to the Startup tab and make sure the Startup
Clock is CCLK; on the Readback tab select SelectMap.
2-20 The DINI Group

DN3000k10 Features, Overview and General Description
For Xilinx ISE 4.x Project Navigator
• NOTE: All the bitgen options are set correctly by default; however,
you may want to double-check a few of the options. After
creating a project and adding your source file, right-click on Generate
Programming File in the Process View window.
Select the Startup Options tab and make sure that the Startup
Clock is set to CCLK. Select the Configuration Options
tab and make sure Configuration Pin Powerdown has a value
of Pull Up.
Setting up the Serial Port (J30/J34 — RS232 Port)
J30/J34 is for an RS232 connection to a terminal. An ICL3221 (U18)
provides voltage translation to RS232 levels. A cable that converts the
10-pin header to a DB9 is shipped with the DN3000k10. This cable comes
packaged with a bracket attached. Remove the bracket to eliminate the
possibility of it falling on the DN3000k10, which could short signals and
damage the board. After you have removed the bracket, plug the cable
into J30. J30 is not keyed—so make sure you get the orientation correct.
Pin 2 is clearly labeled. Pin 1 is opposite of Pin 2, and Pin 1 is identified
with a dot. Figure 2-14 is a cutout from the assembly drawing, and shows
the location of J30 and Pin 1, and J34. J34 on the back of the DN3000k10
can also be used for RS232 communication. This header is not normally
stuffed. J34 is useful is a daughter card is installed that obstructs access to
J30. J34 has the same pin out as J30.
A female-to-female RS232 cable is provided with the DN3000k10. This
cable will attach directly to the RS232 port of a PC. We get our cables from
Jameco (http://www.jameco.com).The part number is 132345. Male-tofemale
extension cables are part number 25700.
The RS232 port is configured with the following parameters:
Bits per second:9600
Data bits:8
Parity:None
Stop Bits:1
FLow control:None
Terminal Emulation:VT100
We use the Windows-based program HyperTerminal (Hypertrm.exe).
The configuration file DN3000k10.ht is supplied on the CD-ROM or can be
downloaded from our web page.
Users have the option of connecting the serial port if they wish to see any
messages during the configuration process.
NOTE: It is NOT mandatory to have the serial port connection in order to
configure the FPGA in SelectMAP mode. However, if an error occurs during
the configuration, then without a serial port connection the user will not
be able to see any error messages. In addition, without a serial port
connection, a user cannot select any Main Menu options after the configuration
process is complete.
DN3000k10 User’s Manual 2-21

DN3000k10 Features, Overview and General Description
T
O
P
S
IDE
V
IE
W
J30
Pin 1
J34
Pin 1
B
O
T
T
O
M
S
I
D
E
V
I
E
W
Figure 2-14 J30/J34 Serial Port Locations
2-22 The DINI Group

DN3000k10 Features, Overview and General Description
Creating Main Configuration File main.txt
To control which bit file on the Smart Media card is used to configure the
FPGA in SelectMAP mode a file named main.txt must be created and
copied to the root directory of the Smart Media card. The configuration
process cannot be performed without this file. Below is a description of
the options that can be set in the file, a description of the format this file
needs to follow, and an example of a main.txt file.
Options:
Verbose Level — During the configuration process, there are three
different verbose levels that can be selected for the serial port messages:
• Level 0:
– Fatal error messages
– Bit file errors (e.g., bit file was created for the wrong part, bit
file was created with wrong version of Xilinx tools, or bitgen
options are set incorrectly)
– Initializing message will appear before configuration
– A single message will appear once the FPGA is configured
• Level 1:
– All messages that Level 0 displays
– Displays configuration type (should be SelectMAP)
– Displays current FPGA being configured if the configuration
type is set to SelectMAP
– Displays a message at the completion of configuration for
each FPGA configured.
• Level 2:
– All messages that Level 1 displays
– Options that are found in main.txt
– Bit file names for each FPGA as entered in main.txt
– Maker ID, device ID, and size of Smart Media card
– All files found on Smart Media card
– If sanity check is chosen, the bit file attributes will be displayed
(part, package, date, and time of the bit file)
– During configuration, a “.” will be printed out after each
block (16 KB) has successfully been transferred from the Smart
Media to the current FPGA.
Sanity Check — The Sanity Check if enabled, verifies that the bit file was
created for the right part, the right version of Xilinx was used, and the
bitgen options were set correctly. If any of the settings found in the bit file
are not compatible with the FPGA, a message will appear from the serial
port, and the user will be asked whether or not they want to continue
with the bit file. Please see the section “Creating Bit Files for SelectMAP”
on page 2-20 for details on which bitgen options need to be changed
from the default settings. A PC version of the sanity check can be run on
your bit files before copying them onto the Smart Media card; see section
“PC Bit File Sanity Check” on page 2-27 for more details.
Format:
The format of the main.txt file is as follows:
DN3000k10 User’s Manual 2-23

DN3000k10 Features, Overview and General Description
• The first nonempty/uncommented line in main.txt should be:
Verbose level: X
where “X” can be 0, 1 or 2. If this line is missing or X is an invalid
level, then the default verbose level will be 2.
• The second nonempty/uncommented line in main.txt tells
whether or not to perform a sanity check on the bit files before
configuring an FPGA:
Sanity check: y
where “y” stands for yes, “n” for no. If the line is missing or the
character after the “:” is not “y” or “n” then the sanity check will
be enabled.
• For each FPGA that the user wants to configure, there should be
exactly one entry in the main.txt file with the following format:
FPGA F: example.bit
In the above format, the “F” following FPGA is to signal that this
entry is for FPGA F, and FPGA F would then be configured with the
bit file example.bit. The DN3000k10 has one to five FPGAs,
which are FPGA A, B, D, E and F. The example has only one FPGA,
which is FPGA F. There can be any number of spaces between the
“:” and the configuration file name, but they need to be on the
same line.
• Comments are allowed with the following rules:
1. All comments must start at the beginning of the line.
2. All comments must begin with //
3. If a comment spans multiple lines, then each line should start
with //
Commented lines will be ignored during configuration, and are
only for the user’s purpose.
• The file main.txt is NOT case sensitive.
IMPORTANT: All configuration file names have a maximum length of eight
(8) characters, with an additional three (3) for the extension. Do not name
your configuration bit files with long file names. In addition, all file names
should be located in the root directory of the Smart Media card—no
subdirectories or folders are allowed. Since the main.txt file controls
which bit file is used to configure the FPGA, the Smart Media card can
contain other bit files.
Example of main.txt:
//start of file “main.txt”
Verbose level: 2
Sanity check: y
2-24 The DINI Group

DN3000k10 Features, Overview and General Description
FPGA F: fpgaF.bit
//the line above configures FPGA F with the bit file
“fpgaF.bit”
//end of main.txt
Given the above example file:
• Verbose level is set to 2
• A sanity check on the bit files will be performed
• FPGA F will be configured with file fpgaF.bit.
Starting SelectMAP Configuration
If using the reference design SmartMedia card that came with the
DN3000k10 then no files need to be copied to the card. Otherwise, copy
your bit file and main.txt to the root directory of the SmartMedia card
using the FlashPath floppy adapter. Make sure the jumpers on J17 are set
for SelectMAP as shown in Table 2-4.
Table 2-4 J17 Configuration Jumper Settings
Pins 1 & 2 Pins 3 & 4 Pins 5 & 6 Configuration Mode
No Jumper Jumper No Jumper JTAG
Jumper No Jumper No Jumper SelectMAP
Set up the serial port connection as described above in “Setting up the
Serial Port (J30/J34 — RS232 Port)” on page 2-21. Next, place the Smart-
Media card in the SmartMedia socket on the DN3000k10 and turn on the
power (NOTE: the card can only go in one way). The SmartMedia card is
hot-swappable and can be taken out or put into the socket even when the
power is on. Once the power has been turned on, the configuration
process will begin as long as there is a valid SmartMedia card inserted
properly in the socket. If there is not a valid SmartMedia card in the
socket, then LED1 will be lit (see Figure 8-2 on page 8-3 for LED descriptions)
and the Main Menu will appear from the serial port. A SmartMedia
card is determined to be invalid if either the format of the card does not
follow the SSFDC specifications, or if it does not contain a file named
main.txt in the root directory. If the configuration was successful, a
message stating so will appear and the Main Menu will come up. Otherwise,
an error message will appear.
The LEDs on U19 and U17 give feedback during and after the configuration
process; see “LEDs” on page 8-3 for further details.
After the FPGA has been configured, the following Main Menu will appear
on the serial port:
1. Configure FPGA(s) using main.txt
2. Interactive FPGA configuration menu
3. Check Configuration status
4. Select file to use in place of main.txt
DN3000k10 User’s Manual 2-25

DN3000k10 Features, Overview and General Description
5. List files on SmartMedia
6. Memory test (BlockRAM, SSRAM, SDRAM)
Description of Main Menu Options.
1. Configure FPGAS Using “main.txt” as the Configuration File— By
selecting this option, the FPGA will configure in SelectMAP mode. You
can also press the reset button (S1) to reconfigure the FPGA in Select-
MAP mode.
2. Interactive FPGA configuration menu — This option takes you to a
menu titled “Interactive Configuration Menu” and allows the FPGA to
be configured through a set of menu options instead of using the
main.txt file. The menu options are described below.
Description of Interactive Configuration Menu options:
1. Select a bit file to configure FPGA(s) — This menu option
allows the user to select a bit file from a list of bit files found
on the SmartMedia card to use to configure the FPGA.
2. Set verbose level (current level = 2) — This menu option
allows the user to change the verbose level from the current
setting. Please note: if the user goes back to the main menu
and configures the FPGA(s) using main.txt, the verbose level
will be set to whatever setting is specified in main.txt.
3. Disable/Enable sanity check for bit files — This menu option
either allows the user to disable or enable the sanity check,
depending on what the current setting is. Please note: if the
user goes back to the main menu and configures the FPGA(s)
using main.txt, the sanity check will be set to whatever
setting is specified in main.txt.
M) Main menu — This menu option takes the user back to the
Main Menu described above.
3. Check Configuration status — This option checks the status of the
DONE pin and prints out whether or not the FPGA(s) have been configured
along with the file name that was used for configuration.
4. Select file to use in place of main.txt — By default, the processor
uses the file main.txt to get the name of the bit file to be used for
configuration as well as options for the configuration process. However,
a user can put several files that follow the format for main.txt
on the SmartMedia card that contain different options for the configuration
process. By selecting the main menu option 4, the user can
select a bit file from a list of files that should be used in place of
main.txt. After selecting a new file to use in place of main.txt, the
user should select Main Menu option 1 to configure the FPGA(s)
according to this new file. If the power is turned off or the reset button
(S1) is pressed, the configuration file is changed back to the
default, main.txt.
5. List files on SmartMedia — This option prints out a list of all the files
found on the SmartMedia card.
2-26 The DINI Group

DN3000k10 Features, Overview and General Description
6. Memory test (BlockRAM, SSRAM, SDRAM) — This option will only
appear if the FPGA is configured. In addition, the test will only be run
if the FPGA is configured with the reference bit file that was shipped
with the DN3000k10.
PC Bit File Sanity Check
A version of the sanity check has been compiled for use on a PC; the
executable is sanityCheck.exe, which can be found on the CD shipped
with the DN3000k10. This allows you to run the sanity check on bit files
before copying them onto the Smart Media card. This PC bit file sanity
check verifies that the right version of Xilinx tools was used and the bitgen
options have been set correctly. To run the sanity check from the
command line:
%sanityCheck –f fpga.bit –d –s
Command line options:
• The -f option is required and must be followed by the name of
the bit file to perform the sanity check on.
• The -d option is optional. It prints out a description of the different
bitgen options and their different values.
• The -s option is optional. It prints out the current bitgen settings
found in the file specified with the -f option.
Expected output:
• If the bit file passes the sanity check, you should see something
similar to:
$ sanityCheck -f fpga_sm.bit
** Performing Sanity Check on File: fpga_sm.bit **
DATE: 2001/10/01
TIME: 10:47:01
PART: 2V6000ff1152
FILE SIZE = 2470068 bytes
ALL BITGEN OPTIONS ARE SET CORRECTLY
• If the bit file does not pass, then a message stating why it didn’t
pass will print out. For example:
$ sanityCheck -f fpga_sm.bit
** Performing Sanity Check on File: fpga_sm.bit **
DATE: 2001/10/01
TIME: 10:47:01
PART: 2v6000ff1152
FILE SIZE = 2470068 bytes
DN3000k10 User’s Manual 2-27

DN3000k10 Features, Overview and General Description
ERROR: PowerDown status pin is enabled, you must
disable this option to configure the FPGA in
SelectMAP mode.
SmartMedia
The configuration bit file for the FPGA is copied to a SmartMedia card
using the SmartDisk FlashPath Floppy Disk Adapter. Note that several BIT
files can be put on a 32-megabyte card. We supply two 32-megabyte
SmartMedia cards with the DN3000k10. SmartMedia is a standard, so you
can get more SmartMedia cards if you want. The DN3000k10 requires a
+3.3 V card. Card sizes of 16, 32, 64 and 128 megabytes have been tested
on the DN3000k10. We have not seen 256 MB or larger cards for sale yet,
but when we do there will probably be an update to the CPLD and
processor on our website to support them.
We get our SmartMedia cards from http://www.computers4sure.com/. A
Delkin Devices 16-megabyte card (part number DDSMFLS2-16) sells for
about $15. A 32-megabyte card (part number DDSMFLS2-32) will set you
back about $20 (see Figure 2-15). New SmartMedia cards do not require
formatting before use.
NOTE: SmartMedia cards do not need to be formatted before they are
used. The Windows format command does not work—it is necessary to
use the FlashPath utility to format a SmartMedia card.
Figure 2-15 Delkin 32 MB 3.3 V Smart Media Card
Do not press down on the top of the SmartMedia Connector J31 if a
SmartMedia card is not installed. The metal case shorts to the +3.3 V
power supply and the case gets hot enough to burn your finger. We
suggest that you leave a SmartMedia card in the connector to prevent this
from occurring. A polyswitch fuse (F1) has been added so that the PWB
and the SmartMedia connector are protected if you do accidently press on
the top of the connector.
2-28 The DINI Group

DN3000k10 Features, Overview and General Description
NOTE: Do NOT press on the SmartMedia Connector J28
if a card is not installed!
WARNING:
Do NOT format a SmartMedia card using the default Windows format
program. All Smart Media cards come preformatted from the factory,
and files can be deleted from the card when they are no longer needed.
If for some reason you absolutely need to format a SmartMedia card, you
must use the format program that is included in the FlashPath (Smart-
Media floppy adapter) software.
Synthesis and Emulation Issues
We use the following tools for synthesis:
Synplicity Synplify (http://www.synplicity.com/)
Synopsys FPGA Express (http://www.synopsys.com/)
Synopsys FPGA Compiler II
Exemplar LeonardoSpectrum
(http://www.exemplar.com/products/leonardospectrum.html)
Of the four listed here, we find that Synplicity offers the best performance,
followed by Exemplar. The Synopsys products are not the easiest
products to use, and probably should be avoided until Synopsys decides
that they want to be in this market. It is generally not worth your time to
preserve your Synopsys ASIC compiler directives and scripts by using the
FPGA synthesis products from Synopsys. The time you save using Synopsys
products is offset by other hassles.
Synthesis
Notes
1. The FPGAs used on your DN3000k10 are either 2v4000s, 2v8000s, or
2v6000s in an FF1152 package. Unless you paid for a faster speed
grade, the –4 is what you will be getting.
2. Memories are best implemented by describing them behaviorally in
your RTL. All four synthesis products are sophisticated enough to map
your behavioral descriptions into the memory blocks. It is NOT necessary
to instantiate Xilinx memories manually. Make sure, however, to
check the report files to make sure that your memories were implemented
in memory blocks (if this is possible). Sometimes subtle
changes are needed to your RTL to get the synthesis programs to recognize
that you intended to use an embedded memory block.
3. Much to our surprise, the synthesis programs recognized RTL multiplier
code and used the embedded multipliers without any trouble.
So, like the memories, RTL description of your multipliers is all that is
necessary. Make sure to check the report files—multipliers that are
DN3000k10 User’s Manual 2-29

DN3000k10 Features, Overview and General Description
implemented using logic blocks (as opposed to the embedded memory
blocks) take huge amounts of FPGA resources.
4. Clocks are the biggest problem when converting ASIC code to FPGA
code. FPGAs only have a limited number of clock arrays. This is far too
complicated to describe here, so get the Virtex II User’s Manual and
read about the clocks.
2-30 The DINI Group

PCI
Chapter 3
PCI
Overview
The DN3000k10 can be hosted in a 32-bit or 64-bit PCI slot. PCI-X is also
supported. Stand-alone operation is described in “Stand-Alone Operation”
on page 6-3. A 2v6000-4, with care, should be able to support a 64-
bit, 66 MHz PCI or PCI-X controller. We have not tested the PWB at PCI-X
speeds of 100 MHz and 133 MHz. We suspect, but won’t guarantee, that
the DN3000k10 can support these high frequencies, provided the speed
grade of the FPGA is adequate. Figure 3-1 shows the FPGA pin connections
for the PCI signals. This data is provided on the CD-ROM in a UCF file titled
fpga.ucf, for your convenience.
The PCI/PCI-X edge connector is shown in Figure 3-2.
VirtexII parts cannot tolerate +5 V TTL signaling, so the DN3000k10 must
be plugged into a +3.3 V PCI slot. PCI-X, by definition, is +3.3 V signaling.
The PWB is keyed so that it is not possible to mistakenly plug the board
into a +5 V PCI slot. Do NOT grind out the key in the PCI host slot, and Do
NOT modify the DN3000k10 to get it to fit into the slot. If you need a
+3.3 V PCI slot, the DNPCIEXT-S3 Extender card can do this function. The
link is http://www.dinigroup.com/products/pciextender.html. This
extender also has the capability to slow the clock frequency of the PCI bus
by a factor of two—a function that is very useful when prototyping ASICs.
NOTE: +5 V Signaling on VirtexII parts causes them to smoke! This is quite
BAD! Do NOT Modify the Dn3000k10 board to fit into your PCI slot.
PCI Mechanical
Specifications
Some Notes
on the
DN3000k10
and PCI/PCI-X
The DN3000k10 is not a standard sized PCI card—it is too tall and slightly
too long. This is sometimes an issue in servers that have a bracket installed
over the top of the PCI cards. If you need to close the case on a DN3000k10,
some tower configurations may work. Figure 3-3 shows the exact dimensions
of the DN3000k10.
+3.3 V power is not needed on the host PCI connector. +3.3 V power is
derived from +5 V using an on-board 10 A switching regulator. Power
distribution for the DN3000k10 is described in “Power Supplies and Power
Distribution” on page 6-1.
LOCK# has a pull-up. This is technically a violation of the PCI specification,
but we have seen systems (from SUN!) that have the LOCK# pin floating.
Remember that the function of this pin was deleted in the 2.2 version of
DN3000k10 User’s Manual 3-1

PCI
FPGA F (U22)
AM16 AD[0] A58
AL16 AD[1] B58
AM15 AD[2] A57
AL15 AD[3] B56
AM14 AD[4] A55
AL14 AD[5] B55
AM13 AD[6] A54
AL13 AD[7] B53
AM12 AD[8] B52
AM11 AD[9] A49
AL11 AD[10] B48
AL10 AD[11] A47
AM9 AD[12] B47
AL9 AD[13] A46
AM8 AD[14] B45
AL8 AD[15] A44
AN14 AD[16] A32
AP13 AD[17] B32
AN13 AD[18] A31
AP12 AD[19] B30
AN12 AD[20] A29
AP11 AD[21] B29
AN11 AD[22] A28
AN10 AD[23] B27
AN8 AD[24] A25
AP7 AD[25] B24
AN7 AD[26] A23
AP6 AD[27] B23
AN6 AD[28] A22
AP5 AD[29] B21
AP4 AD[30] A20
AN5 AD[31] B20
PCI Pin (P2)
AL12 C/BE[0]# A52
AM7 C/BE[1]# B44
AP14 C/BE[2]# B33
AP9 C/BE[3]# B26
AN16 FRAME# A34
AJ18 IRDY# B35
AK19 PCLK B16
AL17 TRDY# A36
AL18 DEVSEL# B37
AP17 STOP# A38
AN9 IDSEL A26
AN4 REQ# B18
AP18 REQ64# A60
AN18 ACK64# B60
AP21 PAR64 A67
AM2 INTA# A6
AN17 PERR# B40
AM17 SERR# B42
AL6 RST A15
AP15 LOCK# B39
AM6 PAR A43
AN3 GNT# A17
AN32 AD[32] A91
AN31 AD[33] B90
AP31 AD[34] A89
AN30 AD[35] B89
AP30 AD[36] A88
AN29 AD[37] B87
AP29 AD[38] A86
AN28 AD[39] B86
AP28 AD[40] A85
AM29 AD[41] B84
AN27 AD[42] A83
AM28 AD[43] B83
AN26 AD[44] A82
AL27 AD[45] B81
AP26 AD[46] A80
AM27 AD[47] B80
AN25 AD[48] A79
AL26 AD[49] B78
AN24 AD[50] A77
AM26 AD[51] B77
AP24 AD[52] A76
AL25 AD[53] B75
AN23 AD[54] A74
AL24 AD[55] B74
AP23 AD[56] A73
AM24 AD[57] B72
AN22 AD[58] A71
AL23 AD[59] B71
AP22 AD[60] A70
AM23 AD[61] B69
AN21 AD[62] A68
AL22 AD[63] B68
PCI Pin (P3)
AM22 C/BE[4]# B66
AP20 C/BE[5]# A65
AM20 C/BE[6]# B65
AN19 C/BE[7]# A64
Figure 3-1 FPGA Pin Connections for PCI Signals
3-2 The DINI Group

PCI
DN3000k10 User’s Manual 3-3
GND
AD12
+VIO
GNT-
AD30
AD26
STOP-
+5V
IRDY-
AD21
PCLK
+5V
GND
AD18
GND
+5V
AD13
+5V
C/BE0-
AD23
+VIO
DCAP5
+12V
AD10
GND
C/BE3-
IDSEL
AD6
DCAP1
DCAP1
AD27
DCAP5
GND
AD8
AD14
DCAP5
INTA-
GND
FRAME-
AD15
PERR-
AD31
DCAP3
AD0
AD2
+5V
SERR-
AD29
RST-
GND
PAR
AD7
DCAP2
AD28
AD20
GND
+5V
GND
TDX
+5V
+VIO
DCAP4
DCAP2
AD1
AD5
C/BE1-
DEVSEL-
DCAP3
C/BE2-
DCAP4
AD24
GND
REQ64-
+VIO
+VIO
AD3
LOCK-
REQ-
GND
GND
ACK64-
DCAP2
AD19
+5V
AD4
AD25
-12V
PME-
GND
AD22
AD16
TRDY-
GND
GND
AD17
GND
TDX
AD11
AD9
PCIXCAP
GND
GND
GND
GND
PRSNT1-
PRSNT2-
M66EN
PME-
M66EN
+3.3V
J32
HDR3X2
1
2
3
4
5
6
J33
HDR4X2
1 2
3 4
5 6
7 8
C340
0.01uF
C331
0.01uF
R185
1M
KEYWAY
COMPONENT
SIDE
SOLDER
SIDE
P2
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B50
B51
A50
A51
C/BE0-
+3V
AD06
AD04
GND
AD02
AD00
+VIO
REQ64-
+5V
+5V
AD09
GND
AD11
AD13
+3V
AD15
PAR
GND
SBO-
SDONE
+3V
STOP-
GND
TRDY-
GND
FRAME-
+3V
AD16
AD18
GND
AD20
AD22
+3V
IDSEL
AD24
GND
AD26
AD28
+3V
AD30
RSVD
GND
GNT-
+VIO
RST-
RSVD
RSVD
+VIO
RSVD
+5V
INTC-
INTA-
+5V
TDI
TMS
+12V
TRST- -12V
TCK
GND
TDO
+5V
+5V
INTB-
INTD-
PRSNT1-
RSVD
PRSNT2-
RSVD
GND
CLK
GND
REQ-
+VIO
AD31
AD29
GND
AD27
AD25
+3V
C/BE3-
AD23
GND
AD21
AD19
+3V
AD17
C/BE2-
GND
IRDY-
+3V
DEVSEL-
GND
LOCK-
PERR-
+3V
SERR-
+3V
C/BE1-
AD14
GND
AD12
AD10
M66EN
AD08
AD07
+3V
AD05
AD03
GND
AD01
+VIO
ACK64-
+5V
+5V
GND
GND
GND
GND
R160 10k
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+VIO
+VIO
+VIO
+VIO
+VIO
+VIO
AD32
AD34
AD36
AD38
AD40
AD42
AD44
AD46
AD48
AD50
AD52
AD54
AD56
AD58
AD60
AD62
AD63
AD61
AD59
AD57
AD55
AD53
AD51
AD49
AD47
AD45
AD43
AD41
AD39
AD37
AD35
AD33
C/BE6-
C/BE4-
C/BE5-
C/BE7-
PAR64
GND
KEYWAY
P3
B94
B93
B92
B91
B90
B89
B88
B87
B86
B85
B84
B83
B82
B81
B80
B79
B78
B77
B76
B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
A94
A93
A92
A91
A90
A89
A88
A87
A86
A85
A84
A83
A82
A81
A80
A79
A78
A77
A76
A75
A74
A73
A72
A71
A70
A69
A68
A67
A66
A65
A64
A63
GND
RSVD
RSVD
GND
AD33
AD35
+VIO
AD37
AD39
GND
AD41
AD43
GND
AD45
AD47
+VIO
AD49
AD51
GND
AD53
AD55
GND
AD57
AD59
+VIO
AD61
AD63
GND
C/BE4-
C/BE6-
GND
RSVD
RSVD
GND
RSVD
AD32
GND
AD34
AD36
GND
AD38
AD40
+VIO
AD42
AD44
GND
AD46
AD48
GND
AD50
AD52
+VIO
AD54
AD56
GND
AD58
AD60
GND
AD62
PAR64
+VIO
C/BE5-
C/BE7-
GND
Figure 3-2 PCI/PCI-X Edge Connector

PCI
13.25 in. (336.2 mm) (AT Length)
7.75 in. (196.7 mm)
Figure 3-3 DN3000k10 Dimensions
the PCI Specification. The pull-up is 1M, which should not adversely impact
PCI functionality in any way.
The PCI JTAG signals TDI, TDO, TCK, TRST#, are not used. TDI and TDO are
connected together per the PCI Specification to maintain JTAG chain integrity
on the motherboard. The signals TMS, TCK, and TRST# are left unconnected.
The VirtexII FPGAs are not +5 V tolerant, so you must plug the DN3000k10
into a +3.3 V PCI slot. Do NOT modify the connector to get the board to fit.
If you need +5 V to +3.3 V PCI voltage translation, get one of our
extenders. The link is:
http://www.dinigroup.com/products/pciextender.html.
The FPGA is volatile, meaning it loses its brains when power is off. The
SmartMedia method takes about 1 second to configure a 2V6000 after
power is stable. It takes about 5 seconds to configure five 2V6000s. It is
likely that FPGA F will finish the configuration process before RST# is deasserted.
If your system has an unusually fast RST#, it is possible that the
FPGA will not be configured when RST# deasserts. A RST# that deasserts
before the FPGA has finished cannot properly configure the PCI/PCI-X mode
latch.
The signal 3.3Vaux is not connected.
The signals INTB#, INTC#, and INTD# are not connected.
3-4 The DINI Group

PCI
J33: Present Signals for PCI/PCI-X (Pins 1–2 and 5–6)
The present signals indicate to the system board whether an add-in card is
physically present in the slot and, if one is present, the total power
requirements of the add-in card.
The J33 PCI-X Present Header is shown in Figure 3-4.
J33
PRSNT2- 1 2
PME- 3 4
PRSNT1- 5 6
M66EN 7 8
HDR4X2
Figure 3-4 J33 PCI-X Present Header
Table 3-1 shows the Present Signal Definitions for PCI/PCI-X.
Table 3-1 Present Signal Definitions
PRSNT1# PRSNT2# Expansion Configuration
Open Open No expansion board present
Ground Open Expansion board present, 25W maximum
Open Ground Expansion board present, 15W maximum
Ground Ground Expansion board present, 7.5W maximum.
We have never seen the present signals ever used, but we have heard of
systems that will not PNP (Plug-and-Play) configure a PCI board if both the
present pins are left open. We recommend installing a jumper in location
1-2 (for PRSNT2-), or 5-6 (for PRSNT1-), or both.
J33: M66EN—66MHz Enable (Pins 7–8)
The 66MHZ_ENABLE pin (M66EN) indicates to the host whether the device
can operate at 66 MHz or 33 MHz. Section 7.5.1 in the PCI Specification 2.2
provides the gory details. For 33 MHz only FPGA designs, install a jumper
between pins 7 and 8. For 66 MHz capable designs, leave this jumper uninstalled.
Table 3-2 shows the jumper descriptions for M66EN.
Table 3-2 M66EN Jumper Descriptions
Jumper
Description
M66EN Installed 33 MHz
Uninstalled
66 MHz
J33: PME–, Power Management Enable (Pin 3)
This board does not have built-in support for PME– (power management
enable). Connecting PME– to an FPGA that is not powered is a bad idea—
DN3000k10 User’s Manual 3-5

PCI
B38
PCIXCAP
5
6
3
4
1
2
J33
HDR3X2
P2
C331
0.01uF
the system powers up as the board is installed. PME– is connected to pin 3
of J33. This header pin allows the user to connect external circuitry to
PME– if this functionality is desired.
J33: PCI/PCI-X Capability
Figure 3-5 shows the PCI-X Capabilities Header. Add in PCI-X boards tell the
system what speed they are capable of running by the correct setting of
this header.
Add-in cards indicate at which frequency they support PCI-X, using a pin
called PCIXCAP. If the card’s maximum frequency is 133 MHz, this pin is left
unconnected (except for a decoupling capacitor C331). If the card’s
maximum frequency is 66 MHz, it connects PCIXCAP to ground through a
resistor R160 (and decoupling capacitor C331). Conventional PCI cards
connect this pin to ground.
J33—PCIXCAP
R160
10k
Figure 3-5 PCI-X Capability Header
For PCI only (not PCI-X capable), jumper between pins 1 and 2.
For PCI-X 133 MHz capable, jumper between pins 3 and 4.
For PCI-X 66 MHz capable, jumper between pins 3 and 4 and pins 5 and 6.
3-6 The DINI Group

PCI
The PCIXCAP jumpers are detailed in Table 3-3.
Table 3-3 PCIXCAP Jumpers
PCIXCAP
Jumper(s) Installed
PCI Only 1–2
PCI-X 133 MHz 3–4
PCI-X 66 MHz 3–4, 5–6
The M66EN and PCIXCAP Encodings are shown in Table 3-4.
Table 3-4 M66EN and PCIXCAP Encoding
M66EN
PCIXCAP
Conventional
Device
Frequency
Capability
PCI-X Device
Frequency
Capability
Ground Ground 33 MHz Not Capable
Not
Connected
Ground 66 MHz Not Capable
Ground Pull-down 33 MHz PCI-X 66 MHz
Not
Connected
Pull-down 66 MHz PCI-X 66 MHz
Ground
Not
Connected
Not
Connected
Not
Connected
33 MHz PCI-X 133 MHz
66 MHz PCI-X 133 MHz
DN3000k10 User’s Manual 3-7

PCI
3-8 The DINI Group

Clocks and Clock Distribution
Chapter 4
Clocks and Clock Distribution
Functional Overview
The DN3000k10 ASIC emulation board has a flexible and configurable
clock scheme. Figure 4-1 is a block diagram showing the clocking
resources and connections.
The clocking structures for the DN3000k10 include the following features:
• 2 user-selectable socketed oscillators (X1, X2)
• 1 48 MHz oscillator (X3)
• 2 CY7B993 (or CY7B994) RoboclockII Multi-Phase PLL Clock
Buffers
• 2 FCT3807 Low-Skew Clock Buffers
The Clock Grid, J22–J24: a 5X3 0.1 in. header distributes clock signals to
two FCT3807 clock buffers and two RoboclockII PLL clock buffers
(CY7B993 or CY7B994). The clock outputs from the buffers are dispersed
throughout the board.
Two 3.3 V half-can oscillator sockets (X1 and X2) and the signal CLKOUT
from the CPLD provide on-board input clock solutions. The DN3000k10 is
shipped with both a 14.318 MHz (X1) and a 100 MHz (X2) oscillator.
Neither X1 nor X2 are used by the configuration circuitry, so the user is
free to stuff any standard 3.3 V half-can oscillator in the X1 and X2 positions
(more detail later in “Customizing the Oscillators” on page 4-14).
The Clock Grid can also accept a 5X2 ribbon cable. This cable can provide
input clocks to both of the RoboclockII’s and one of the 3807 buffers.
The FCT3807 clock buffer provides a high speed 1-to-10 buffer with low
skew (0.35 ns) allowing clocks A (ACLK[9:0]) and B (BCLK[9:0]) to be
distributed point-to-point. The two RoboclockII’s offer functional control
of clock frequency and skew, among other things. The two RoboclockII
PLL clock buffers (U24 and U25) are configured via header arrays (J2, J7,
J11), (J3, J8, J12), (J4, J9, J13) and (J5, J10, J14). The DN3000k10 comes from
the factory stuffed with CY7B994V, which can operate at frequencies from
24 MHz to 200 MHz. The “3V” and “4V” versions of the chip are available.
These chips operate from 12 MHz to 100 MHz and 24 MHz to 200 MHz
respectively. Each chip has 16 output clocks along with 2 feedback output
clocks. Two sets of eight output clocks are jumper selectable for each chip.
The feedback clocks are controlled separately.
The PLL clock buffers can accept either 3.3 V LVTTL or LV Differential
(LVPECL) reference inputs. The devices can operate at up to 12x the input
frequency while the output clocks can be divided up to 12x the operating
DN3000k10 User’s Manual 4-1

Clocks and Clock Distribution
ACLK
48
MHz
(x3)
X1
X2
CPLD
(U13)
CLOCKA
CLOCKB
CLKOUT
Clock
Selection
Grid
J22–J24
Roboclock1
(U24)
Roboclock2
(U25)
FCT3807
CCLK[7:0]
ECLK[15:0]
ACLK[9:0]
*no ACLK[5]
BCLK
CCLK
DCLK
ECLK
ACLK
BCLK
ECLK
ECLK
ACLK
BCLK
CCLK
DCLK
CON1
J25
CON2
J26
CON3
J28
FPGA
F
ACLK[9]
BCLK[9]
FCT3807
BCLK[9:0]
*no BCLK[5]
ECLK
4
ECLK
SDRAM
SSRAM1
ACLK
X2 stuffed at factory with 100 MHz
X1 stuffed at factory with 14.318 MHz
ACLK
ECLK
ECLK
ECLK
SSRAM2
SSRAM3
SSRAM4
BCLK
CCLK
DCLK
ECLK
ACLK
BCLK
CCLK
DCLK
ECLK
FPGA
U12
B
FPGA
U21
D
BCLK
CCLK
DCLK
ECLK
ACLK
BCLK
CCLK
DCLK
ECLK
FPGA
U11
A
FPGA
U20
E
PCI_CLK
ACLK
BCLK
CCLK
DCLK
ECLK
FPGA
U22
F
PCI
Connector
Figure 4-1 Clock Distribution Block Diagram
4-2 The DINI Group

Clocks and Clock Distribution
frequency. Phase adjustments can be made in 625 ps or 1300 ps steps up to
±10.4 ns. All adjustments are jumper selectable.
Clock Grid
Orientation
and
Description
The clock grid, J22–J24, gives the user the ability to customize the clock
scheme on the DN3000k10. A brief description of each pin is given in
Table 4-1. The physical orientation of the pins is diagrammed in
Figure 4-2.
.
Table 4-1 Clock Grid Signal Descriptions
CLKOUT
Signal
Description
Clock signal from CPLD. Typically 12 MHz.
PLL1A Input to RoboclockII #1
CLOCKA
Clock signal of oscillator #1 (X1)
BUFINB Clock input to 3807 #2
CLOCKB
Clock signal of oscillator #2 (X2)
PLL2B_PRE Secondary clock input to RoboclockII II #2.
Differential pair with PLL2BN_PRE.
PLL2BN_PRE Secondary clock input to RoboclockII II #2.
Differential pair with PLL2B_PRE.
BUFINA Clock input to 3807 #1
PLL1BN_PRE Secondary clock input to RoboclockII #1.
Differential pair with PLL1B_PRE.
PLL1B_PRE Secondary clock input to RoboclockII #1.
Differential pair with PLL1BN_PRE.
GND
Ground signals to provide signal integrity for
ribbon cables.
DN3000k10 User’s Manual 4-3

Clocks and Clock Distribution
J24
J23
J22
CLOCKA
1
BUFINA
1
GND
1
PLL1A
2
PLL2B_PRE
2
GND
2
CLOCKOUT
3
PLL2BN_PRE
3
GND
3
BUFINB
4
PLL1B_PRE
4
GND
4
CLOCKB
5
PLL1BN_PRE
5
GND
5
Figure 4-2 Clock Grid
Jumper
Control for the
Most Common
Applications
Three main configurations are the most common.
First, the grid may be jumpered as follows:
Configuration #1: CLKOUT PLL1A, CLOCKA BUFINA and
CLOCKB BUFINB
Both 3807s receive their inputs from the oscillators. RoboclockII #1
receives a clock input from the CPLD. Also, RoboclockII #2 can use DCLK7
from RoboclockII #1 as an input. This is explained in “RoboclockII PLL Clock
Buffers” on page 4-7. The common clock configurations are diagrammed
in Figure 4-3.
Second, the input clock distribution can be configured as:
Configuration #2: CLKOUT PLL2BN_PRE, CLOCKA PLL1A
and CLOCKB BUFINB
In this configuration, a 3807 #2 receives an oscillator input. RoboclockII #1
receives an oscillator input while RoboclockII #2 receives the CPLD output
clock signal. 3807 #1 is unused.
Finally, the grid may be configured as:
Configuration #3: CLKOUT BUFINB, CLOCKA BUFINA, and
CLOCKB PLL1BN_PRE
The 3807 #1 receives an oscillator input, and the 3807 #2 receives a CPLD
input. Meanwhile, RoboclockII #1 receives the other oscillator input. The
user can wire-wrap a clock to the unused driver(s) as needed. This enables
full use of the timing devices on the DN3000k10.
Also, the destination of the output clocks might dictate some other
configuration. This manual and other documentation should provide
more than enough information to satisfy the user’s needs (See Figure 4-4).
4-4 The DINI Group

Clocks and Clock Distribution
FCLKOUT
PCI
PCLK
ECLK[15:0]
PCLK
ACLK[0]
BCLK[0]
CCLK[0]
DCLK[0]
ECLK[0]
FHDR_CLK[1]
FHDR_CLK[2]
FPGA
F
(U22)
I/O
MBCK[7:0]
ACLK[9]
BCLK[9]
OSC
X3
CPLD
CLKOUT
PLL2B
PLL2BN
RoboClock
2
(U25)
ACLK[1]
BCLK[1]
CCLK[1]
DCLK[1]
ECLK[1]
AHDR_CLK[1]
AHDR_CLK[2]
FPGA
A
(U11)
MBCK8_NP
OSC
X1
OSC
X2
CLOCKA
CLOCKB
J24
J23 J22
BUFINA
BUFINB
PLL1B
PLL1BN
PLL1A
BCLKOUT
RoboClock
1
(U24)
BUFFER
1
(U15)
BUFFER
2
(U16)
CCLK[6:0]
DCLK[6:0]
DCLK[7]
ACLK[8:6], [5:0]
BCLK[8:6], [5:0]
ACLK[2]
BCLK[2]
CCLK[2]
DCLK[2]
ECLK[2]
ACLK[3]
BCLK[3]
CCLK[3]
DCLK[3]
ECLK[3]
BHDR_CLK[1]
ACLK[4]
BCLK[4]
CCLK[4]
DCLK[4]
ECLK[4]
DHDR_CLK[1]
FPGA
E
(U20)
FPGA
B
(U12)
FPGA
D
(U21)
I/O
ECLK[15:10]
DRAM
(U7)
ECLK[9]
SSRAM 4
(FED)
ECLK[8]
SSRAM 3
(BD)
ECLK[7]
SSRAM 2
(A2D)
ECLK[6]
SSRAM 1
(AB)
ACLK[6]
BCLK[6]
CCLK[6]
DCLK[6]
ECLK[15]
AHDR_CLK[2]
AHDR_CLK[1]
CON2
(J25)
MBCK[1]
ACLK[7]
BCLK[7]
CCLK[7]
ECLK[5]
ECLK[14]
DHDR_CLK[1]
BHDR_CLK[1]
CON3
(J26)
MBCK[2]
ACLK[8]
BCLK[8]
CCLK[5]
DCLK[5]
FHDR_CLK[0]
FHDR_CLK[1]
CON1
(J28)
MBCK[0]
Figure 4-3 Common Clock Configurations
DN3000k10 User’s Manual 4-5

Clocks and Clock Distribution
+3.3V
PLL2B_PRE
PLL2BN_PRE
PLL1B_PRE
PLL1BN_PRE
C176
0.1µF
C174
0.1µF
C28
0.1µF
C175
R47
NS
R46
NS
R43
NS
R42
NS
R14
NS
R15
NS
R44 68 1%
NS
PLL2B
PLL2BN
PLL1B
PLL1BN
R45
191 1%
NS
0.1µF
Figure 4-4 PECL Clock Input and Termination
NOTE: C175, C28, C174 and C176 are stuffed with 0-ohm resistors!
Note that the schematic shows capacitors in positions C175, C28, C174 and
C176. The DN3000k10 has 0-ohm resistors in these capacitor positions. The
termination resistors R14–R15 and R42–R47 are not stuffed.
Ribbon Cable:
Providing an
Off-Board
Clock to the
DN3000k10
The DN3000k10 gives the user a simple means to bring off-board clocks
onto the board. The user can attach 10-pin ribbon cable to J22 and J23 of
the Clock Grid. J23 consists of an input to 3807 #1 and differential pair
inputs to both RoboclockII’s. J22 consists of ground pins for signal integrity.
These signals are described in Table 4-1 on page 4-3. BUFINA is a standard
3.3 V TTL input.
Both differential pairs provide some flexibility. The user can provide a
single 3.3 V TTL input. It can be attached to either input. However, the
other input must be left open. The user can provide a differential clock
input to the pair. The differential clock inputs must obey the electrical
specifications listed in Table 4-8 on page 4-13.
4-6 The DINI Group

Clocks and Clock Distribution
While attaching a ribbon cable, the user can jumper oscillator signal
CLOCKB to BUFINB (3807 #2) on J24. This results in full use of all of the
timing devices on the DN3000k10 (See Figure 4-5).
J24 J23 J22
CLOCKA
1
BUFINA
1
GND
1
PLL1A
2
PLL2B
2
GND
2
CLKOUT
3
PLL2BN
3
GND
3
BUFINB
4
CLOCKB
5
PLL1B
4
PLL1BN
5
GND
4
GND
5
BUFINA Buffer A ACLK
BUFFINB Buffer B BCLK
PLL1A Roboclock1 CCLK, DCLK (PLLSEL1 low)
PLL1B Roboclock1 CCLK, DCLK (PLLSEL1 high)
PLL2B Roboclock2 ECLK (PLLSEL2 high)
Roboclock1 Roboclock2 with PLLSEL2 low, J27 installed, and FCKLOUT unused.
WITH 10-PIN RIBBON CABLE
Option (Connected to J21 and J22)
3 external
clocks
PLL1B, PLL2B and BUFINA are driven from cable. BUFINB can be
jumpered to CLKOUT or CLOCKB, or left undriven.
2 external
clocks
PLL2B and BUFINA are driven from cable, with PLL1A jumpered to
CLKOUT or CLOCKA. Same options as above for BUFINB.
PECL
clocks
The board can be set up for PECL inputs in PLL1B and PLL1BN, and in
PLL2B and PLL2BN. PECL-ready boards cannot function without the
cable except as in options 3 and 4 above.
Figure 4-5 External Ribbon Cable Connections
RoboclockII PLL Clock Buffers
Figure 4-6 is a functional diagram of RoboclockII 1 and RoboclockII 2.
Jumper Descriptions
Headers J2–J5 and J7–J14 are used to control the PLLs. The headers are
grouped in sets of three. Of the groups of three, one header consists of
GND pins. One consists of various PLL inputs. The final header consists of
+3.3 V pins. The layout of the headers is shown in Figure 4-7.
DN3000k10 User’s Manual 4-7

Clocks and Clock Distribution
Clock A
CPLD
FBKA
x
LOCK +5V
ROBOCLOCK1
X1
X2
Clock
Selection
Matrix
REFA+
REFA-
REFB+
REFB-
PLLSEL1
MODE1
x
x
x
x
Phase
Frequency
Detector
OUTPUT_MODE
FS
Filter
3
3
VCO
Control Logic
Divide and Phase
Generator
33
FEED-
BACK
BANK
FBF0
FBDS0
FBDS1
FBDIS
3
3
3
Divide and
Phase select
Matrix
QFA0
x QFA1
J2 J7 J11
1
2
3
4
5
6
7
8
+3.3V
INV2
INV1
FBDIS1
FBDIS2
J3 J8 J12
1
2
3
4
5
6
7
8
+3.3V
RBCF0
RBCF1
CDS0
CDS1
RBDF0
RBDF1
DDS0
DDS1
B
A
N
K
4
B
A
N
K
3
B
A
N
K
2
B
A
N
K
1
4F0
4F1
4DS0
4DS1
3F0
3F1
3DS0
3DS1
INV3
2F0
2F1
2DS0
2DS1
1F0
1F1
1DS0
1DS1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Divide and
Phase select
Matrix
Divide and
Phase select
Matrix
Divide and
Phase select
Matrix
Divide and
Phase select
Matrix
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
CCLK[7:0]
DCLK[7:0]
PLLSEL2
MODE1
Clock B
Duplicate of Clock A
See details above
FEED-
BACK
BANK
FBF0
FBDS0
FBDS1
FBDIS
3
3
3
Divide and
Phase select
Matrix
ROBOCLOCK2
QFA0
QFA1 x
J5 J10 J14
FS1
1
FBF01
2
FBDS01
3
FBDS11
4
FS2
5
6
7
8
9
10
+3.3V
1
2
3
4
5
6
7
8
J4 J9 J13
+3.3V
RBEF0
RBEF1
EDS0
EDS1
RBFF0
RBFF1
FDS0
FDS1
B
A
N
K
4
B
A
N
K
3
B
A
N
K
2
B
A
N
K
1
4F0
4F1
4DS0
4DS1
3F0
3F1
3DS0
3DS1
INV3
2F0
2F1
2DS0
2DS1
1F0
1F1
1DS0
1DS1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Divide and
Phase select
Matrix
Divide and
Phase select
Matrix
Divide and
Phase select
Matrix
Divide and
Phase select
Matrix
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
ECLK[15:0]
Figure 4-6 Functional Diagram of RoboclockII 1 and RoboclockII 2
4-8 The DINI Group

Clocks and Clock Distribution
1 GND
8
1 GND
8
PLLSEL1 PLLSEL2 MODE1 MODE2 INV1 INV2 FBDIS1 FBDIS2
J2
J7
J11
RBCF0 RBCF`1 CDS0 CDS1 RBDF0 RBDF1 DDS0 DDS1
J3
J8
J12
1 +3.3V
8
1 +3.3V
8
1 GND
8
1 GND
8
RBEF0 RBEF1 EDS0 EDS1 RBEF0 RBEF1 FDS0 FDS1
J4
J9
J13
FS1 FBF01 FBDS01 FBDS11 FS2 FBF01 FBDS02 FBDS12
J5
J10
J14
1 +3.3V
8
1 +3.3V
8
Figure 4-7 Header Layout
Note that the final two pins for headers J5, J10, and J14 have been
omitted from the layout diagram. The Header Classifications are shown in
Table 4-2.
Table 4-2 Header Classification
Controls GND Input Pins +3.3 V
Group I:
General Control
Group 2:
PPL1 Divider Control
Group 3:
PLL2 Divider Control
Group 4:
Feedback and f NOM Control
J2 J7 J11
J3 J8 J12
J4 J9 J13
J5 J10 J14
The input pins are either LVTTL or 3-level input pins. The LVTTL pins need
to be jumpered HIGH or LOW, which is achieved by connecting the input
pin to the neighboring +3.3 V or GND pin, using a jumper. The 3-level input
pins can be in a HIGH, MID, or LOW state. The HIGH and LOW states are
achieved in the same way as the LVTTL pins. The MID state is reached by
leaving the input pin unjumpered. The RoboclockII’s have internal
circuitry to bring the pin to 1.5 V when left open. The Jumper Definitions
are shown in Table 4-3.
DN3000k10 User’s Manual 4-9

Clocks and Clock Distribution
Table 4-3 Jumper Definitions
Name Type Default Description
PLLSEL2[1] LVTTL LOW Input Clock Select: If LOW, U25:DCLK7
(U24:PLL1A) is selected as the input clock. If
HIGH, the U25:PLL2B_N (U24:PLL1B_N) pair is
selected as the input clock.
MODE[2:1] 3-Level HIGH Output Mode: If HIGH, clock outputs disable to
high-Z state. If LOW, clock outputs disable to
“HOLD-OFF’ mode. If MID, clock outputs disable
to factory test mode.
INV2[1] 3-Level MID Invert Mode: When HIGH, clocks CCLK[3:0]
(ECLK[3:0]) are inverted. When MID, these
clock outputs are non-inverting. When LOW, the
pairs CCLK[1:0] and CCLK[3:2] (ECLK[1:0]
and ECLK[3:2]) will be complementary.
FBDIS[2:1] LVTTL LOW Feedback Disable: When HIGH, feedback is
disabled. When LOW, feedback is enabled.
RB[C-F]F[1:0] 3-Level MID Output Phase Function: Each pair controls the
phase function of the respective group of
outputs. See “Clock Skew” on page 4-12 for
more information.
[C-F]DS[1:0] 3-Level LOW Output Divider Function: Each pair controls the
divider function of the respective group of
outputs. See “Clock Division” on page 4-11 for
more information.
FS[2:1] 3-Level LOW Frequency Select: The input specifies the
operating range of the nominal frequency
(f NOM ). See “General Control” on page 4-11 for
more information.
FBF0[2:1] 3-Level LOW Feedback Output Phase Function: The input
controls the phase function of the feedback
outputs. See “Feedback and Clock
Multiplication” on page 4-11 for more
information.
FBDS[1:0][2:1] 3-Level MID Feedback Output Divider Function: Each pair
controls the divider function of the feedback
outputs. See “Feedback and Clock
Multiplication” on page 4-11 for more
information.
4-10 The DINI Group

Clocks and Clock Distribution
General
Control
FS[2:1] is a 3-Level input which determines the allowable range for the
operating frequency f NOM of the device. Depending on the chip grade, the
PLL can operate between 12–100 MHz or 24–200 MHz. The actual f NOM
frequency can be determined by setting all jumpers to their defaults.
Thus, f NOM will be seen on all of the “divide-by-one” clock outputs. The
user can set FS accordingly. The Frequency Range Settings are shown in
Table 4-4.
Table 4-4 Frequency Range Settings
FS[2:1]
CY7B993V
f NOM (MHz)
CY7B994V
f NOM (MHz)
MIN MAX MIN MAX
LOW 12 26 24 52
MID 24 52 48 100
HIGH 48 100 96 200
Feedback and
Clock
Multiplication
Clock Division
First of all, FBDIS[2:1] must be set LOW, enabling feedback. The feedback
output is looped back to the feedback input. When a divided output
is applied to the feedback input, the VCO (voltage controlled oscillator) of
the PLL aligns the feedback input with the original input clock. Thus, with
a 10 MHz input clock and the feedback outputs set to divide by 2, f NOM
must be 20 MHz. Consequently, 10 MHz is seen on the feedback output
clocks and can be aligned with the input clocks. The feedback clock divider
function actually serves as a clock multiplication mechanism for the operating
frequency f NOM . The divider function and the clock skew function
are set in the same manner for the feedback and the normal clock
outputs. See “Clock Division” on page 4-11 and “Clock Skew” on
page 4-12, respectively.
The three pairs of DS inputs per chip are used to control the two groups of
clock outputs and the feedback outputs of each PLL. The user can simply
follow the Divider Function Table to acquire the desired output frequency.
There are two things to remember. First, FS[2:1] must be set properly
according to fNOM. Second, the FBDS feedback inputs act as operating
clock frequency multipliers. The Output Divider Settings are shown in
Table 4-5.
DN3000k10 User’s Manual 4-11

Clocks and Clock Distribution
Table 4-5 Output Divider Settings
Input Signals
Output Divider Function
[C-fF]DS1 and
FBDS1[2:1]
[C-F]DS0 and
FBDS0[2:1]
Output Signals
Feedback
Output Signals
LOW LOW /1 /1
LOW MID /2 /2
LOW HIGH /3 /3
MID LOW /4 /4
MID MID /5 /5
MID HIGH /6 /6
HIGH LOW /8 /8
HIGH MID /10 /10
HIGH HIGH /12 /12
Clock Skew
Clock skew is controlled by the “F” inputs. The clock skew may be any
integer value from 0 to ±8 times the RoboclockII time unit t U . The time
unit value is derived from the operating frequency f NOM and the FS[2:1]
setting. The following equation yields the time unit t U .
t U =
1
f NOM • N
The possible values for N are given in Table 4-6. The available skew for
each RoboclockII derived clock is given in Table 4-7. Based on the
following information, the user will be able to adjust the skew for any of
the RoboclockII outputs.
Table 4-6 Time Unit N-factor
CY7B993V
CY7B994V
FS
f NOM (MHz)
f NOM (MHz)
N at which N at which
t U = 1 ns
t U = 1 ns
LOW 64 15.625 32 31.25
MID 32 31.25 16 62.5
HIGH 16 62.5 8 125
4-12 The DINI Group

Clocks and Clock Distribution
Table 4-7 Clock Skew Settings
Input Signals
Output Skew Function
RB[C-F]F1
RB[C-F]F0
and FBF0[2:1]
DCLK[3:0] or
ECLK[11:8]
DCLK[7:4] or
ECLK[15:12]
CCLK[3:0] or
ECLK[3:0]
CCLK[7:4] or
ECLK[7:4]
Feedback
Output
Signals
LOW LOW -4t U -4t U -8t U -8t U -4t U
LOW MID -3t U -3t U -7t U -7t U N/A
LOW HIGH -2t U -2t U -6t U -6t U N/A
MID LOW -1t U -1t U COL1* COL1* N/A
MID MID 0t U 0t U 0t U 0t U 0t U
MID HIGH +1t U +1t U COL2** COL2** N/A
HIGH LOW +2t U +2t U +6t U +6t U N/A
HIGH MID +3t U +3t U +7t U +7t U N/A
HIGH HIGH +4t U +4t U +8t U +8t U +4t U
*The clock skew is equivalent to the skew on DCLK[3:0] or ECLK[11:8]
**The clock skew is equivalent to the skew on DCLK[7:4] or ECLK[15:12]
Differential
Clocks
In addition to LVTTL clock signals, the RoboclockII clock buffers can handle
LV Differential (LVPECL) clocks. The user can cable in an acceptable differential
signal to PLL1B and PLL1BN, or PLL2B and PLL2BN through the
clock grid J22–J24. The signals must obey the specifications given in
Table 4-8. Onboard circuitry is available to center the signals about the
proper voltage, if needed.
Table 4-8 LVPECL Input Specifications
Description Min Max
Differential Voltage 0.4 3.3
Highest HIGH Voltage 1.0 3.3
Lowest LOW Voltage GND 2.9
Common Mode range
(crossing voltage)
0.8 3.3
The clock input of the RoboclockII can accept a superset of PECL. PECL
involves a 1 V swing about V CC /2. The RoboclockII clock input can accept a
swing of up to 3.3 V about V CC /2, which gives the user another dimension
of flexibility.
DN3000k10 User’s Manual 4-13

Clocks and Clock Distribution
The CY7B993V/4V can output LVTTL complementary (differential) signals,
too. Setting INV1 (INV2) LOW will result in clocks CCLK[1:0] and
CCLK[3:2] (ECLK[1:0] and ECLK[3:2]) becoming complementary
pairs. A network of series and parallel resistors could be used to reduce
the nominal swing of the clock signals.
Useful Notes
and Hints
The CYB993V consistently outputs ~32.5 MHz signals in cases of improper
settings or unacceptable clock inputs. This was observed when:
• The CY7B993V part was operating at a nominal frequency f NOM of
36.4 MHz with FS set LOW.
• Identical clocks were sent to PLL2B and PLL2BN.
For the CY7B994V part, the operating frequency can reach up to 200 MHz.
However, the maximum output frequency is 185 MHz. This means when
185 MHz ≤ f NOM ≤ 200 MHz, the output divider must be set to at least 2.
Otherwise, the RoboclockII’s will output garbage.
Customizing the Oscillators
The user can customize the frequency of the clock networks by stuffing
oscillators in X1 and X2. The DN3000k10 is shipped with a 14.318 MHz
oscillator in location X1 and a 100 MHz oscillator in X2. The RoboclockII’s
are not +5 V tolerant, so +3.3 V oscillators are necessary.
NOTE: If you stuff your own oscillators, +3.3 V CMOS outputs are necessary
since the RoboclockII’s are not +5 V signalling tolerant!
We get our oscillators from Digi-Key (http://www.digikey.com/). Of note
is an Epson line of oscillators called the SG-8002 Programmable Oscillators.
Any frequency between 1.00 MHz–106.25 MHz can be procured in
the normal Digi-Key shipping time of 24 hours. A half-can, +3.3 V CMOS
version is needed with a tolerance of 50 ppm. The part number for an
acceptable oscillator from this family would be:
SG-8002DC-PCB-ND
– package SG-531
– output enable
– 3.3 V CMOS
– 50 ppm
If the order is placed via the web page, the requested frequency to two
decimal places is placed in the Web Order Notes. The datasheet is on the
CD-ROM for this oscillator. The file name is SG8002DC.pdf.
4-14 The DINI Group

Clocks and Clock Distribution
Any polarity of output enable for each oscillator (on pin 1) is acceptable.
Make sure that you have the proper jumper settings at positions 9 and10
of J14, J15 and J16. See Figure 4-8 and Figure 4-9 for a description.
2 2 2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J5
1
2
3
4
5
6
7
8
9
10
HDR10x1
FS1
FBF01
FBDS01
FBDS11
FS2
FBF02
FBDS02
FBDS12
X1OE
X2OE
J10
1
2
3
4
5
6
7
8
9
10
HDR10x1
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
J14
1
2
3
4
5
6
7
8
9
10
HDR10X1
Figure 4-8 Clock OE Pin Jumper Settings
Table 4-9 Clock OE Pin Jumper Settings
Clock OE
Jumper Settings
Active High OE for X1 Jumper J10.9 to J14.9
Active Low OE for X1 Jumper J5.9 to J10.9
Active High OE for X2 Jumper J10.10 to J14.10
Active Low OE for X2 Jumper J5.10 to J10.10
DN3000k10 User’s Manual 4-15

Clocks and Clock Distribution
DN3000k10 PCI_CLK Operation
The DN3000k10 ASIC emulation board has the ability to run all FPGAs, all
SRAMs, and all the SDRAM off of PCI_CLK. PCI_CLK is a single destination
clock which is routed to FPGA F (U22) from the PCI connector. The user can
input PCI_CLK to one of the VirtexII Digital Clock Managers (DCM) in
FPGA F. The resulting DCM output can be sent to the Roboclocks via the
signal FCLKOUT. All of the aforementioned devices receive one of the
ECLK clock outputs from RoboclockII #2. Consequentially, the DN3000k10
can be clocked exclusively by PCI_CLK
PCI_CLK
Details
PCI_CLK (or PCLK) is connected to one of FPGA F’s global clock inputs from
the PCI connector. Then, a DCM must be instantiated. The DCM will require
a minimum of three connections. For further information on VirtexII
DCM operation, see the Xilinx website at http://www.xilinx.com. The
VirtexII Datasheet (VirtexII-Datasheet.pdf) and User’s Guide
(VirtexII_UserGuide.pdf), which can be found on the DN3000k10 CD-
ROM, also provide useful information on DCMs. PCI_CLK must be
connected to the “CLKIN” input of the DCM. The DCM output, “CLK[0]”
will be connected to the output signal FCLKOUT. One more connection
must be made to the DCM. This will come up later in this section.
The FCLKOUT signal is connected to one of the four input pins on
RoboclockII #2. FCLKOUT’s complementary input is DCLK[7](R). FCLKOUT
and DCLK[7](R) are both single ended TTL inputs. When either of them
is being used, the other one must be left open. For complete PCI_CLK
operation, jumper J27 must be unstuffed leaving DCLK[7](R) open.
If set to the default configuration, RoboclockII #2 will drive a one-to-one
PCI_CLK derived clock on its outputs. See “RoboclockII PLL Clock Buffers”
on page 4-7 for more information. RoboclockII #2 has 16 clock outputs
(ECLK[15:0]). Each FPGA (ECLK[4:0]), each SSRAM (ECLK[9:6]), and
the SDRAM (ECLK[13:10]) receive ECLK signals.
To complete this setup, a feedback signal must be connected to the DCM in
FPGA F. RoboclockII #2 sends ECLK[0] to FPGA F. ECLK[0] needs to be
connected to the “CLKFB” input signal of the DCM. Using ECLK[0] as
feedback allows the DCM to properly synchronize the DN3000k10
PCI_CLK network which completes the setup (see Figure 4-9 for a
diagram of the PCI_CLK DCM circuit).
The DN3000k10 can be run off any single-ended TTL clock signal which is
sent to the RoboclockIIs. The ECLK distribution provides the DN3000k10
this flexibility. PCI_CLK has special implications for DN300k10 PCI operation.
4-16 The DINI Group

Clocks and Clock Distribution
FPGA F
(U22)
DCM
PCI
PCI_CLK
CLKIN
CLK[0]
FCLKOUT
Roboclock
#2
CLKFB
ECLK[0]
Figure 4-9 PCI_CLK DCM Circuit
BCLKOUT and
FCLKOUT
Header Clocks
BCLKOUT and FCLKOUT are both FPGA I/O signals which are connected to
the DN3000k10’s RoboclockII chips. BCLKOUT, which comes from FPGA B, is
connected to RoboclockII #1, while FCLKOUT is connected to RoboclockII
#2 from FPGA F. Clock signals can be sent out on these lines through the
use of a VirtexII DCM. Then, the RoboclockIIs can drive these signals onto
the CCLK[7:0] and DCLK[7:0] and/or ECLK[15:0] clock outputs.
BCLKOUT and FCLKOUT give the user further flexibility in the board’s clock
schemes. See the section “DN3000k10 PCI_CLK Operation” on page 4-16
for an example.
Six signals from the 200-pin headers are connected to a GCLK buffer on
particular FPGAs. Two “Header Clocks” go to FPGA A and F each while
FPGAs B and D receive one each. As inputs, clock signals can be used for
clocking in their respective FPGAs. They can also be distributed to other
chips via the MBCK bus. Using the I/Os BCLKOUT and FCLKOUT, the FPGA B
and F signals can be sent to the RoboclockIIs and distributed to the rest of
the board too. As outputs, clock signals can be driven to a daughter card
from the FPGAs through these connections. The Header Clocks provide
another avenue to input or output clocks to/from the DN3000k10.
See “BCLKOUT and FCLKOUT” section for more information.
DCLK[7](R)
The signal DCLK[7](R) is routed from one of the RoboclockII #1 outputs
to one of the RoboclockII #2 inputs. Jumper J27 lies along this connection
route. J27 must be installed in order to utilize DCLK[7}(R). DCLK[7](R)s
complementary input on RoboclockII #2 is FCLKOUT. DCLK[7](R) and
FCLKOUT are both single-ended TTL inputs. When either of them is being
used, the other one must be left open. Thus, FCLKOUT must be unutilized
on FPGA F for DCLK[7](R) to operate.
DCLK[7](R) provides two useful results. First, any clock signal or some
derivation sent to RoboclockII #1 can be driven onto RoboclockII #2 for full
distribution.
DN3000k10 User’s Manual 4-17

Clocks and Clock Distribution
Second, running a clock through RoboclockII #1 to #2 gives the user more
divide and multiply options for the clock frequencies. Here is an example.
If you have a 40MHz input clock, the user cannot output a 30MHz clock
with a single RoboclockII’s multiply and divide options. However, the user
can input a 40MHz to RoboclockII #1 and divide it by 4. By installing the
J27 jumper, a 10MHz clock will be driven onto RoboclockII #2. Setting
RoboclockII #2’s feedback outputs to divide by 3, the operating frequency
will become 30MHz. Thus, a 30MHz could be driven onto the
RoboclockII #2 output signals.
NOTE: The signal FCLKOUT must be left open in order to utilize
DCLK[7](R)
4-18 The DINI Group

Memories
Chapter 5
Memories
The DN3000k10 has five external memories: four, 36-bit SSRAMs, and one
72-bit SDRAM DIMM. The four SSRAMS are referred to as SSRAM AB (U8),
SSRAM BD (U14), SSRAM A2D (U9), and SSRAM FED (U23).
SSRAMs
SSRAM Notes
The SSRAMs can be stuffed with ZBT, non-ZBT, pipeline, or flowthrough
parts. We believe we have anticipated the additional address lines for the
1 M x 36 and 2 M x 36 parts when they are available. The DN3000k10 is
stuffed at the factory with 512 K x 36-bit Synchronous Pipeline Burst
SRAM. Samsung K7A163600M-QC1400 are probably the parts you will
have stuffed into your DN3000k10. The datasheet is on the CD-ROM in the
file DS_K7A1636(18)00M.pdf. The SSRAMs are tested at 100 MHz.
SSRAMs AB and A2D share some I/Os with the 200 pin connectors. See
Figure 5-1 to figure out which ones.
SSRAM AB is clocked by ECLK.
SSRAM BD is clocked by ECLK.
SSRAM A2D is clocked by ECLK.
SSRAM FED is clocked by ECLK.
The signal connections for SSRAM AB are shown in Figure 5-2.
The signal connections for SSRAM BD are shown in Figure 5-3.
The signal connections for SSRAM A2D are shown in Figure 5-4.
The signal connections for SSRAM FED are shown in Figure 5-5 and
Figure 5-6.
Flowthrough SSRAMs are functionally the closest to ASIC-style memories.
Pipeline SSRAMs can be clocked at faster frequencies. ZBT SSRAMs are typically
one generation behind in density. The subtle differences between
the styles of memories are described in the next section.
DN3000k10 User’s Manual 5-1

Memories
SSRAM
(U8)
SSRAM
(U9)
A2D[69:0]
70
FPGA
A
(U11)
70
SDRAM
(U7)
110
AB[125:56]
FB[109:0]
FPGA
B
(U12)
BD[175:106]
70
SSRAM
(U14)
FPGA
F
(U22)
FPGA
E
(U20)
FPGA
D
(U21)
70
FED[69:0]
SSRAM
(U23)
ACLK
BCLK
CCLK
DCLK
HEADER
(J28)
ACLK
BCLK
CCLK
DCLK
ECLK
35
AHDR
[68:34]
6
56
A2D[48]
A2D
AB
AE[114:59]
1
HEADER
(J25)
40 51 50 MB
AHDR
[33:0],
[74:69]
MB
FPGA
A
(U11)
AE
AB
1
FB[31]
MB
154–161, 163–164,
172–174, 177,
181–184, 186–188,
190–205, 207–214,
219–220, 223–224,
226
AB
63–66, 68,
73–81, 83–99,
102, 104,
106–118,
121–4, 126
AB
69, 70, 103,
105, 120,
125
MB
8
EHDR[7:0]
HEADER
(J26)
49 MB 28
152–153, 161–162,
164–171, 175–176, MB
178–180, 185, 198,
206, 215–218,
221–222, 225–226
BHDR[48:0]
FPGA
B
(U12)
MB
58
ACLK
BCLK
CCLK
ECLK
DHDR[57:0]
38 A2D
A2D
5–8, 10, 15–17, 20–23,
26–27, 33, 36–37,
39–40, 42–43. 47,
49–50, 52, 56–57, 59,
61–62, 65–66, 68–73
FPGA
F
(U22)
FPGA
E
(U20)
FPGA
D
(U21)
Figure 5-1 FPGA Interconnect Block Diagram
5-2 The DINI Group

Memories
FPGA A (U11)
SSRAM AB (U8)
G9 AB[125] CE# AB[125] G11
K13 AB[123] CE2# AB[123] H9
A6 AB[56] ADV# AB[56] A29
B6 AB[57] ADSP# AB[57] B29
A5 AB[58] ADSC# AB[58] A30
B5 AB[59] OE# AB[59] B30
A4 AB[60] BWE# AB[60] A31
B4 AB[61] GW# AB[61] B31
G15 AB[82] BWA# AB[82] G9
F13 AB[83] BWB# AB[83] J10
H12 AB[84] BWC# AB[84] H10
F10 AB[85] BWD# AB[85] G10
K22 AB[122] MODE AB[122] K24
H15 AB[124] ZZ AB[124] F22
G11 AB[63] SA0 AB[63] H26
H19 AB[64] SA1 AB[64] G26
G23 AB[65] SA2 AB[65] H25
J22 AB[66] SA3 AB[66] J23
H22 AB[67] SA4 AB[67] K23
H14 AB[68] SA5 AB[68] H24
J8 AB[69] SA6 AB[69] K12
H9 AB[70] SA7 AB[70] F11
B7 AB[71] SA8 AB[71] B28
A7 AB[72] SA9 AB[72] A28
K14 AB[73] SA10 AB[73] K22
G22 AB[74] SA11 AB[74] H12
F11 AB[75] SA12 AB[75] G12
F21 AB[76] SA13 AB[76] G13
G26 AB[77] SA14 AB[77] H14
G19 AB[78] SA15 AB[78] H15
F25 AB[79] SA16 AB[79] G15
K24 AB[80] SA17 AB[80] H23
F22 AB[81] SA18 AB[81] J22
C33 AB[62] SA19 AB[62] C2
G13 AB[86] D0 AB[86] J17
K23 AB[87] D1 AB[87] H18
J13 AB[88] D2 AB[88] H19
K21 AB[89] D3 AB[89] F20
G25 AB[90] D4 AB[90] G20
J20 AB[91] D5 AB[91] H20
F24 AB[92] D6 AB[92] F21
K19 AB[93] D7 AB[93] H21
F14 AB[94] D8 AB[94] G24
K16 AB[95] D9 AB[95] F24
J14 AB[96] D10 AB[96] F25
J17 AB[97] D11 AB[97] G23
G10 AB[98] D12 AB[98] G25
H20 AB[99] D13 AB[99] G22
B8 AB[100] D14 AB[100] B27
A9 AB[101] D15 AB[101] A26
K15 AB[102] D16 AB[102] J12
H10 AB[103] D17 AB[103] J15
G16 AB[104] D18 AB[104] F13
H11 AB[105] D19 AB[105] F15
H18 AB[106] D20 AB[106] J13
H13 AB[107] D21 AB[107] K14
J15 AB[108] D22 AB[108] H13
F20 AB[109] D23 AB[109] J14
H25 AB[110] D24 AB[110] K16
H24 AB[111] D25 AB[111] K15
F15 AB[112] D26 AB[112] K13
K12 AB[113] D27 AB[113] G19
K20 AB[114] D28 AB[114] K19
G12 AB[115] D29 AB[115] J20
J21 AB[116] D30 AB[116] K20
H21 AB[117] D31 AB[117] J21
H23 AB[118] PAR0 AB[118] K17
B9 AB[119] PAR1 AB[119] B26
J10 AB[120] PAR2 AB[120] G16
K17 AB[121] PAR3 AB[121] K21
Control Pins Address Pins
Data Pins
Figure 5-2 SSRAM AB (U8) Bus Signals
FPGA B (U12)
DN3000k10 User’s Manual 5-3

Memories
FPGA B (U12)
SSRAM BD (U14)
L33 BD[125] CE# BD[125] AD33
G34 BD[126] CE2# BD[126] AH34
D34 BD[127] ADV# BD[127] AL34
E33 BD[128] ADSP# BD[128] AK33
E34 BD[129] ADSC# BD[129] AK34
F33 BD[130] OE# BD[130] AJ33
F34 BD[131] BWE# BD[131] AJ34
G33 BD[132] GW# BD[132] AH33
H33 BD[133] BWA# BD[133] AG33
J33 BD[134] BWB# BD[134] AF33
J34 BD[135] BWC# BD[135] AF34
K33 BD[136] BWD# BD[136] AE33
AG26 BD[137] MODE BD[137] J27
P25 BD[138] ZZ BD[138] AB26
AD27 BD[106] SA0 BD[106] M26
AD26 BD[107] SA1 BD[107] M25
AE27 BD[108] SA2 BD[108] L27
AE26 BD[109] SA3 BD[109] L26
AF26 BD[110] SA4 BD[110] K27
AF25 BD[111] SA5 BD[111] K26
M33 BD[112] SA6 BD[112] AC33
L34 BD[113] SA7 BD[113] AD34
D33 BD[114] SA8 BD[114] AL33
C33 BD[115] SA9 BD[115] AM33
AB26 BD[116] SA10 BD[116] P25
AB27 BD[117] SA11 BD[117] P26
AA25 BD[118] SA12 BD[118] R25
AA26 BD[119] SA13 BD[119] R26
Y26 BD[120] SA14 BD[120] T25
Y27 BD[121] SA15 BD[121] T27
Y25 BD[122] SA16 BD[122] U25
AC26 BD[123] SA17 BD[123] N27
AC25 BD[124] SA18 BD[124] N26
AH20 BD[175] SA19 BD[175] G20
V25 BD[139] D0 BD[139] V25
V26 BD[140] D1 BD[140] W25
U25 BD[141] D2 BD[141] Y25
T27 BD[142] D3 BD[142] Y27
T25 BD[143] D4 BD[143] Y26
R26 BD[144] D5 BD[144] AA26
R25 BD[145] D6 BD[145] AA25
P26 BD[146] D7 BD[146] AB27
N27 BD[147] D8 BD[147] AC26
N26 BD[148] D9 BD[148] AC25
M26 BD[149] D10 BD[149] AD27
M25 BD[150] D11 BD[150] AD26
L27 BD[151] D12 BD[151] AE27
L26 BD[152] D13 BD[152] AE26
K27 BD[153] D14 BD[153] AF26
K26 BD[154] D15 BD[154] AF25
N33 BD[155] D16 BD[155] AB33
N34 BD[156] D17 BD[156] AB34
AD19 BD[157] D18 BD[157] J17
AE19 BD[158] D19 BD[158] K19
AG21 BD[159] D20 BD[159] K20
AJ21 BD[160] D21 BD[160] J20
AJ27 BD[161] D22 BD[161] G26
AH26 BD[162] D23 BD[162] G25
AJ26 BD[163] D24 BD[163] F25
AH25 BD[164] D25 BD[164] G24
AJ25 BD[165] D26 BD[165] F24
AH24 BD[166] D27 BD[166] H23
AJ24 BD[167] D28 BD[167] G23
AG23 BD[168] D29 BD[168] G22
AH23 BD[169] D30 BD[169] F22
AH22 BD[170] D31 BD[170] H21
W25 BD[171] PAR0 BD[171] V26
J27 BD[172] PAR1 BD[172] AG26
M34 BD[173] PAR2 BD[173] AC34
AJ22 BD[174] PAR3 BD[174] F21
Figure 5-3 SSRAM BD (U14) Bus Signals
Control Pins Address Pins
Data Pins
FPGA D (U21)
5-4 The DINI Group

Memories
FPGA A (U11)
SSRAM A2D (U9)
AC3 A2D[67] CE# A2D[67] V31
R3 A2D[68] CE2# A2D[68] T24
J3 A2D[21] ADV# A2D[21] T30
H5 A2D[22] ADSP# A2D[22] T31
F4 A2D[23] ADSC# A2D[23] T32
W3 A2D[24] OE# A2D[24] U29
V11 A2D[25] BWE# A2D[25] U30
U5 A2D[26] GW# A2D[26] U31
N3 A2D[27] BWA# A2D[27] U24
AH5 A2D[28] BWB# A2D[28] V24
AF5 A2D[29] BWC# A2D[29] W24
AD5 A2D[30] BWD# A2D[30] V29
AG3 A2D[0] MODE A2D[0] AG30
AD4 A2D[1] ZZ A2D[1] L32
AA5 A2D[2] SA0 A2D[2] AG28
AC4 A2D[3] SA1 A2D[3] AH29
AE4 A2D[4] SA2 A2D[4] AH32
U4 A2D[5] SA3 A2D[5] AF30
T5 A2D[6] SA4 A2D[6] AG32
P5 A2D[7] SA5 A2D[7] AG31
M3 A2D[8] SA6 A2D[8] W29
AA4 A2D[9] SA7 A2D[9] V30
L3 A2D[10] SA8 A2D[10] R32
Y3 A2D[11] SA9 A2D[11] R31
W4 A2D[12] SA10 A2D[12] AF32
V4 A2D[13] SA11 A2D[13] F31
T11 A2D[14] SA12 A2D[14] F32
T3 A2D[15] SA13 A2D[15] G29
P3 A2D[16] SA14 A2D[16] G30
N5 A2D[17] SA15 A2D[17] G32
AG5 A2D[18] SA16 A2D[18] H30
W11 A2D[19] SA17 A2D[19] AF31
F3 A2D[20] SA18 A2D[20] AE30
AG6 A2D[69] SA19 A2D[69] AG29
AD3 A2D[31] D0 A2D[31] H32
AB4 A2D[32] D1 A2D[32] J30
P4 A2D[33] D2 A2D[33] J31
J9 A2D[34] D3 A2D[34] J32
W5 A2D[35] D4 A2D[35] K30
H3 A2D[36] D5 A2D[36] K31
K4 A2D[37] D6 A2D[37] L30
AA3 A2D[38] D7 A2D[38] L31
N4 A2D[39] D8 A2D[39] N32
R4 A2D[40] D9 A2D[40] N31
U10 A2D[41] D10 A2D[41] P30
F5 A2D[42] D11 A2D[42] N30
J4 A2D[43] D12 A2D[43] P31
AB3 A2D[44] D13 A2D[44] M32
AC6 A2D[45] D14 A2D[45] P32
AE5 A2D[46] D15 A2D[46] M31
L5 A2D[47] D16 A2D[47] W32
G5 A2D[48] D17 A2D[48] AA30
L4 A2D[49] D18 A2D[49] W31
G3 A2D[50] D19 A2D[50] AA31
V5 A2D[51] D20 A2D[51] W30
U6 A2D[52] D21 A2D[52] AA32
AH3 A2D[53] D22 A2D[53] Y32
AF4 A2D[54] D23 A2D[54] Y31
AB5 A2D[55] D24 A2D[55] AB31
M4 A2D[56] D25 A2D[56] AB30
G6 A2D[57] D26 A2D[57] AC32
AF9 A2D[58] D27 A2D[58] AC31
T4 A2D[59] D28 A2D[59] AC29
Y4 A2D[60] D29 A2D[60] AD32
M6 A2D[61] D30 A2D[61] AD31
K5 A2D[62] D31 A2D[62] AD30
AF3 A2D[63] PAR0 A2D[63] H31
AG4 A2D[64] PAR1 A2D[64] M29
J5 A2D[65] PAR2 A2D[65] AB32
H4 A2D[66] PAR3 A2D[66] AE31
Figure 5-4 SSRAM A2D (U9) Bus Signals
Control Pins Address Pins
Data Pins
FPGA D (U21)
DN3000k10 User’s Manual 5-5

Memories
FPGA E (U20) FPGA F (U22) SSRAM FED
(U23)
AM20 FED[19] AL15
AH26
CE#
AK13 FED[20] AL22
AK25
CE2#
AH18 FED[21] AL17
AK22
ADV#
AD17 FED[22] AD17
AJ22
ADSP#
AH17 FED[23] AJ18
AJ23
ADSC#
AL16 FED[24] AM19
AH23
OE#
AL15 FED[25] AM20
AK24
BWE#
AK14 FED[26] AL21
AJ24
GW#
AJ23 FED[27] AL23
AJ25
BWA#
AL24 FED[28] AK11
AK26
BWB#
AL23 FED[29] AJ12
AJ26
BWC#
AL22 FED[30] AK13
AK27
BWD#
AK11 FED[31] AL24
AH9
MODE
AD16 FED[32] AE19
AH22
ZZ
Control Pins
FPGA D (U21)
AE16 FED[0] AF20
AH12
SA0
AJ15 FED[1] AH20
AK11
SA1
AJ14 FED[2] AJ22
AJ11
SA2
AH13 FED[3] AG23
AK10
SA3
AJ11 FED[4] AJ25
AJ10
SA4
AH10 FED[5] AH26
AJ9
SA5
AJ18 FED[6] AH17
AE25
SA6
AM19 FED[7] AL16
AE24
SA7
AH19 FED[8] AM16
AK21
SA8
AJ19 FED[9] AM15
AL21
SA9
AJ20 FED[10] AH15
AG9
SA10
AG21 FED[11] AF15
AE10
SA11
AH23 FED[12] AJ13
AH10
SA12
AH24 FED[13] AG12
AF11
SA13
AJ26 FED[14] AJ10
AG11
SA14
AL10 FED[15] AK24
AE12
SA15
AJ10 FED[16] AJ26
AG12
SA16
AG19 FED[17] AE17
AF10
SA17
AD19 FED[18] AE18
AJ12
SA18
AJ23 FED[69] AM11
AJ16
SA19
Address Pins
Figure 5-5 SSRAM FED (U23) Bus Signals (Page 1 of 2)
5-6 The DINI Group

Memories
FPGA E (U20) FPGA F (U22) SSRAM FED
(U23)
AF15 FED[33] AG21
AF14
D0
AH15 FED[34] AJ20
AG14
D1
AF20 FED[35] AE16
AE16
D2
AG23 FED[36] AH13
AE15
D3
AJ25 FED[37] AJ11
AD19
D4
AG11 FED[38] AH25
AE20
D5
AH12 FED[39] AJ24
AH20
D6
AG16 FED[40] AG20
AG21
D7
AE19 FED[41] AD16
AG22
D8
AH22 FED[42] AG14
AH24
D9
AJ24 FED[43] AH12
AF24
D10
AJ17 FED[44] AD18
AD18
D11
AH16 FED[45] AL18
AE18
D12
AM13 FED[46] AK21
AG19
D13
AM12 FED[47] AK22
AM19
D14
AM23 FED[48] AL12
AL20
D15
AM24 FED[49] AL11
AJ19
D16
AM11 FED[50] AJ23
AL19
D17
AM14 FED[51] AL20
AH18
D18
AJ16 FED[52] AL19
AF20
D19
AJ27 FED[53] AG9
AF25
D20
AH25 FED[54] AG11
AH25
D21
AJ21 FED[55] AG15
AF23
D22
AG20 FED[56] AG16
AG23
D23
AG15 FED[57] AJ21
AJ21
D24
AG14 FED[58] AH22
AG20
D25
AG9 FED[59] AJ27
AH19
D26
AH26 FED[60] AH10
AE19
D27
AJ22 FED[61] AJ14
AE17
D28
AH20 FED[62] AJ15
AG16
D29
AE18 FED[63] AD19
AF15
D30
AE17 FED[64] AG19
AE14
D31
AG12 FED[65] AH24
AF13
PAR0
AM22 FED[66] AL13
AJ20
PAR1
AM21 FED[67] AL14
AM21
PAR2
AJ13 FED[68] AH23
AH13
PAR3
FPGA D (U21)
Figure 5-6 SSRAM FED (U23) Bus Signals (Page 2 of 2)
Data Pins
DN3000k10 User’s Manual 5-7

Memories
Pin 14 of each SSRAM may be pulled high, pulled low, or left unconnected.
Table 5-1 has the details of each SSRAM.
Table 5-1 Requirements for Non-Standard SSRAMs
Pin 14 Pin 16 Pin 66
ZBT Pipeline
AB
A2D
BD
+3.3 V
Install Resistor
R55
R48
R49
R90
R182
+3.3 V
Short to Pin 15
+3.3 V
Short to Pin 65
ZBT
Flowthrough
AB
A2D
BD
FED
GND
Install Resistor
R56
R50
R51
R98
R181
+3.3 V
Short to Pin 15
GND
Short to Pin 67
Syncburst
Flowthrough
or Pipeline
NC
No Resistors
NC
No Short
NC
No Short
5-8 The DINI Group

Memories
Pipeline,
Flowthrough,
ZBT
Syncburst FT (Flowthrough) (Figure 5-7) is the most straightforward type
of SSRAM available for the DN3000k10. Write data may be accepted on the
same clock cycle as the activation signal and address, and read data is
returned one clock cycle after it is requested. Syncburst is designed to
allow two controllers to access the same SSRAM, using two activation
signals, ADSC# and ADSP#; an activation with ADSP# requires data and
byte enables one clock cycle after the address and activation. Syncburst PL
(Pipelined) (Figure 5-8) is identical except for registered outputs, which
delay read data an additional clock cycle but may be necessary for highspeed
designs.
Zero-Bus-Turnaround (ZBT) SSRAMs are designed to eliminate wait states
between reads and writes by synchronizing data. Thus, ZBT FT SSRAMs
Write
Control
Logic
Address
Register
[18:2]
Burst
Control
[1:0]
Memory
Block
Input
Reg
DQ
Output
Buffers
Read
Control
Logic
Figure 5-7 Syncburst FT
Write
Control
Logic
Address
Register
[18:2]
Burst
Control
[1:0]
Memory
Block
Input
Reg
DQ
Output
Reg
Output
Buffers
Figure 5-8 Syncburst PL
Read
Control
Logic
DN3000k10 User’s Manual 5-9

Memories
(Figure 5-9) accept and return data one clock cycle after the address
phase, and ZBT PL SSRAMs (Figure 5-10) accept and return data two clock
cycles after the address phase. This allows the user to begin a write burst
immediately after the last word of a read burst, because read data will be
returned before the first write data is required. The timing is illustrated in
Figure 5-11 and Table 5-2.
Write Control &
Data Coherency
Address
Register
[18:2]
Burst
Control
[1:0]
Write
Address
Register
Memory
Block
Data Steering
Input
Reg
Output
Buffers
DQ
Figure 5-9 Syncburst ZBT FT
Read
Control
Logic
Write Control &
Data Coherency
Input
Reg 1
Address
Register
[18:2]
Burst
Control
[1:0]
Write
Addr
Reg 1
Write
Addr
Reg 2
Memory
Block
Output
Reg
Data Steering
Input
Reg 0
Output
Buffers
DQ
Figure 5-10 Syncburst ZBT PL
Read
Control
Logic
Clock
Address
Phase
Setup
Hold
Write
Phase
Syncburst
(ADSC#)
Syncburst
(ADSP#)
ZBT FT
ZBT PL
Read
Phase
Flowthrough
Pipelined
Figure 5-11 Syncburst and ZBT SSRAM Timing
5-10 The DINI Group

Memories
Table 5-2 Syncburst and ZBT SSRAM Timing
Address Phase
Syncburst
CE#, CE2#, CE
ADSC#, or ADSP#
address
or
ADV# 1
ZBT
CE#, CE2#, CE
R/W#, LD# 2 , BWx#
address
or
ADV 2 , BWx# 3
Write Phase BWE#, BWx#, or GW# 4
data
data
Read Phase Valid Data Valid Data
1 To continue a burst.
2 ADV/LD# is low to load a new address, high to continue bust.
3 For write access only.
4 Writes to all four bytes.
SDRAM
The DN3000k10 has a socket for a +3.3 V 168-pin SDRAM DIMM. Either
registered or unbuffered modules fit in the socket (U7). The same
PC100/PC133 SDRAM modules that you put into your PC are used here. Your
DN3000k10 will be stuffed and tested with a 1 Gbyte PC133 SDRAM DIMM,
unless otherwise requested.
All DIMM pins are connected to the FPGA and the pins are shown in
Figure 5-12 and Figure 5-13. We aren’t quite sure what the largest size
SDRAM DIMM is that will work in the DN3000k10, but here is the math as
best we understand it:
14 Address lines A[13:0]
(multiplexed between RAS* and CAS*, address 10 not used
for CAS*) 27
2 bank address BA[1:0] 2
4 chip selects (S[3:0]*) used in pairs 1
So, we think that there are 29 address bits (27 + 2) and 2 possible chips
selects, which add one more address bit. This totals 30 address bits — 1 G
of 72-bit long words, which is 8 Gbytes. Please tell us if this math is wrong.
SDRAM modules require 4 clocks — CK[3:0]. These clocks are driven by
the RoboclockII 2 and the signal names are ECLK.
The CD-ROM has a datasheet of an acceptable 1 Gbyte SDRAM module
from Micron. The file name is SDF36C64_127x72G_B.pdf.
DN3000k10 User’s Manual 5-11

Memories
FPGA F (U22)
SDRAM (U7)
N8 FB[99] CKE0 FB[99] N29
Y3 FB[100] CKE1 FB[100] L31
M4 FB[101] SO* FB[101] V29
AB9 FB[102] S1* FB[102] AC27
J4 FB[103] S2* FB[103] T32
N6 FB[104] S3* FB[104] P27
R6 FB[105] BA0 FB[105] M27
J3 FB[106] BA1 FB[106] U29
N4 FB[107] WE* FB[107] W29
V8 FB[108] CAS* FB[108] AB29
L9 FB[109] RAS* FB[109] AD29
M6 FB[64] A0 FB[64] W24
R8 FB[65] A1 FB[65] AD28
L3 FB[66] A2 FB[66] V24
U7 FB[67] A3 FB[67] AE29
L4 FB[68] A4 FB[68] U24
P8 FB[69] A5 FB[69] K29
L5 FB[70] A6 FB[70] T24
T6 FB[71] A7 FB[71] L28
K4 FB[72] A8 FB[72] U31
T7 FB[73] A9 FB[73] L29
K5 FB[74] A10 FB[74] U30
R7 FB[75] A11 FB[75] M28
P6 FB[76] A12 FB[76] N28
M8 FB[77] A13 FB[77] U26
AF3 FB[78] SDA FB[78] K28
AF4 FB[79] SCL FB[79] J29
AF5 FB[80] SA0 FB[80] J28
AG3 FB[81] SA1 FB[81] H29
AG4 FB[82] SA2 FB[82] H28
P5 FB[83] CB0 FB[83] W31
N3 FB[84] CB1 FB[84] W32
H4 FB[85] CB2 FB[85] R32
H5 FB[86] CB3 FB[86] R31
V7 FB[87] CB4 FB[87] AA29
V6 FB[88] CB5 FB[88] AA27
L6 FB[89] CB6 FB[89] AE28
L7 FB[90] CB7 FB[90] AF29
N5 FB[91] DQMB0 FB[91] V30
M3 FB[92] DQMB1 FB[92] V31
J5 FB[93] DQMB2 FB[93] T31
H3 FB[94] DQMB3 FB[94] T30
Y8 FB[95] DQMB4 FB[95] AB28
AD9 FB[96] DQMB5 FB[96] AC28
N7 FB[97] DQMB6 FB[97] P29
M7 FB[98] DQMB7 FB[98] R28
AF9 FB[0] DQ0 FB[0] AE31
W11 FB[1] DQ1 FB[1] AD30
V11 FB[2] DQ2 FB[2] AD31
U10 FB[3] DQ3 FB[3] AD32
T11 FB[4] DQ4 FB[4] AC29
J9 FB[5] DQ5 FB[5] AC31
U4 FB[6] DQ6 FB[6] AC32
U5 FB[7] DQ7 FB[7] AB30
U6 FB[8] DQ8 FB[8] AB31
T3 FB[9] DQ9 FB[9] AB32
T4 FB[10] DQ10 FB[10] AA30
T5 FB[11] DQ11 FB[11] AA31
R3 FB[12] DQ12 FB[12] AA32
R4 FB[13] DQ13 FB[13] Y31
P3 FB[14] DQ14 FB[14] Y32
P4 FB[15] DQ15 FB[15] W30
AB3 FB[16] DQ16 FB[16] P32
AA5 FB[17] DQ17 FB[17] P31
AA4 FB[18] DQ18 FB[18] N31
AA3 FB[19] DQ19 FB[19] M32
Y4 FB[20] DQ20 FB[20] L32
Figure 5-12 SDRAM (U3) Bus Signals (Page 1 of 2)
Control Pins Address Pins EEPROM Parity Bits Byte Enables
Data Pins
FPGA B (U12)
5-12 The DINI Group

Memories
FPGA F (U22)
SDRAM (U7)
(CONTINUED) (CONTINUED) (CONTINUED)
W5 FB[21] DQ21 FB[21] L30
W4 FB[22] DQ22 FB[22] K30
W3 FB[23] DQ23 FB[23] J30
V5 FB[24] DQ24 FB[24] H32
V4 FB[25] DQ25 FB[25] H30
G3 FB[26] DQ26 FB[26] AG32
G5 FB[27] DQ27 FB[27] G30
G6 FB[28] DQ28 FB[28] G29
F3 FB[29] DQ29 FB[29] F32
F4 FB[30] DQ30 FB[30] F31
F5 FB[31] DQ31 FB[31] D32 J25.52
AF7 FB[32] DQ32 FB[32] R29
AF6 FB[33] DQ33 FB[33] T28
AE7 FB[34] DQ34 FB[34] T29
AE6 FB[35] DQ35 FB[35] R27
AD7 FB[36] DQ36 FB[36] U28
AD6 FB[37] DQ37 FB[37] U27
AC8 FB[38] DQ38 FB[38] L25
AC7 FB[39] DQ39 FB[39] N25
AB7 FB[40] DQ40 FB[40] AD25
AB6 FB[41] DQ41 FB[41] AB25
AA8 FB[42] DQ42 FB[42] V28
AA6 FB[43] DQ43 FB[43] V27
Y7 FB[44] DQ44 FB[44] W28
Y6 FB[45] DQ45 FB[45] W27
W7 FB[46] DQ46 FB[46] Y29
W6 FB[47] DQ47 FB[47] Y28
AC4 FB[48] DQ48 FB[48] P30
AC3 FB[49] DQ49 FB[49] N32
AB5 FB[50] DQ50 FB[50] N30
AB4 FB[51] DQ51 FB[51] M31
AC6 FB[52] DQ52 FB[52] M29
AD3 FB[53] DQ53 FB[53] K31
AD4 FB[54] DQ54 FB[54] J32
AD5 FB[55] DQ55 FB[55] J31
AE4 FB[56] DQ56 FB[56] H31
AE5 FB[57] DQ57 FB[57] G32
K6 FB[58] DQ58 FB[58] AF28
K7 FB[59] DQ59 FB[59] AG29
J6 FB[60] DQ60 FB[60] AF27
J7 FB[61] DQ61 FB[61] AF32
H6 FB[62] DQ62 FB[62] AF31
J8 FB[63] DQ63 FB[63] H22
Figure 5-13 SDRAM (U3) Bus Signals (Page 2 of 2)
Data Pins (Continued)
FPGA B (U12)
Header
Descriptions
J19 and J18
Header J1 is connected to the WP (Write Protect) input of the SDRAM
EEPROM, and to ground. A pull-up resistor keeps the WP signal high when
the header is unconnected; adding a jumper between the two pins drives
the signal low. The default configuration is no jumper.
The EEPROM holds data describing the size, configuration, and timing
characteristics of the SDRAM. The data is write-protected when the WP
signal is high. There should be little or no reason to want to overwrite the
EEPROM data. Some SDRAM manufacturers simply connect the WP pin of
the EEPROM chip to the power supply of the SDRAM, in which case J1 has
no effect whatsoever.
Header J6 is connected to the REGE (Register Enable) input of the SDRAM
and to ground. A pull-up resistor keeps the REGE signal high when the
header is unconnected; adding a jumper between the two pins drives the
signal low. The default configuration is no jumper.
DN3000k10 User’s Manual 5-13

Memories
On some SDRAMs, the REGE input may be used to select Registered or Non-
Registered behavior. If REGE is high, the control signals will go through
registers before being sent to the individual DRAMs, delaying access by
one clock cycle but improving fanout; if it is low, the signals will be passed
directly to the DRAMs.
The 1 GB SDRAM module shipped as part of the package is affected by
both J1 and J6, i.e., its EEPROM is connected to the WP input and it can be
configured for Registered or Non-Registered behavior.
User Notes —
DCMs for
Clock
Management
on Memories
All external memory chips on the DN3000k10 run on ECLK. Each FPGA uses
an internal digital clock manager (DCM) in the reference design to reduce
skew. All SSRAMs have been tested successfully with deskewing DCMs at
speeds up to 100 MHz and faster for certain ones (BD, for example, is much
closer to both connecting FPGAs than the other SSRAMs). The SDRAM has
been successful up to 90 MHz.
DCMs can also be used for synchronizing clocks. For example, the PCI clock
signal can be driven by FCLKOUT and used to drive ECLK to all FPGAs and
memory chips. This introduces a delay, but using the output of a DCM to
drive FCLKOUT gives the user control over phase and skew issues. If the PCI
clock is used as the DCM input, and ECLK is connected to the feedback
input, the DCM should synchronize ECLK with the PCI clock, allowing a
design with no clock domain changes required.
Some examples of phase shift control are given in the DN3000k10S documentation,
available on our website. For more information about DCMs,
please consult the VirtexII datasheet available at www.xilinx.com.
5-14 The DINI Group

Power Supplies and Power Distribution
Chapter 6
Power Supplies and Power Distribution
The DN3000k10 can be hosted in a +3.3 V PCI slot, or it can be used standalone.
Figure 6-1 shows the various supplies used on the DN3000k10 and
the connections of these supplies on the circuit board. The supply, +5 V,
from the PCI connector (or P1) supplies the basic power to the DN3000k10.
The +3.3 V power from the PCI connector is not used, nor is it connected to
any circuitry on the DN3000k10.
Molex
P1
+5 V
+12 V
U10
10A
Switcher
U1
10A
Switcher
+5 V
+3.3 V
+1.5 V
+12 V
–12 V
J28
20 pin
IDC
Header
J21
+5 V
+3.3 V 3.3 V
+1.5 V 1.5 V
+12 V
–12 V
+5 V
+3.3 V
+1.5 V
+12 V
–12 V
J25
200 pin
Micropax
Connectors
VCCO
PCI-X
Connector
P2, 3
+5 V
+12 V
–12 V
VCCAUX
FPGA
A, B, D, E, F
1.5 V
VCCINT
+5 V
+3.3 V
+1.5 V
SDRAM
+12 V
SSRAM AB
–12 V
SSRAM BD
SSRAM AE
SSRAM FED
Figure 6-1 Power Distribution DN3000k10
J26
The DN3000k10, when plugged into a PCI slot, has the following different
power rails:
• +5 V
• +3.3 V
DN3000k10 User’s Manual 6-1

Power Supplies and Power Distribution
• +1.5 V
• –12 V
• +12 V
The power rails +3.3 V and +1.5 V are created using a switching regulator
with +5 V as the input. +3.3 V from the PCI fingers is not used. U10 is for
+3.3 V and U1 is for +1.5 V. Heat is not an issue with this style of switching
regulator. Each regulator should be able to supply the minimum 10 A of
current without strain. The most demanding application of the
DN3000k10 should fit within the 10 A budget on these two power rails.
+3.3 V Power
The specification for the +3.3 V power is shown in Table 6-1. The +3.3 V
supply is used by the following components on the DN3000k10:
• VirtexII FPGA I/O (U11, U12, U20, U21, U22)
• RoboclockII’s U24, U25
• 2 Clock buffers U5, U6
• CPLD (U13)
• Microprocessor (U3)
• Microprocessor SRAM (U5)
• 4SSRAMs (U8, U9, U14, U23)
• SDRAM DIMM (U7)
• 3 Oscillators X1, X2, X3
We do run +3.3 V a little hot. At worst case for all components, the +3.3 V
power supply should never fall below +3.30 V.
Table 6-1 Specification for +3.3 V Power
Minimum Typical Maximum
Voltage +3.35 V +3.39 V +3.44 V
Current N/A N/A 12 A
+1.5 V Power
The specification for the +1.5 V power is shown in Table 6-2. The +1.5 V
supply is used by the following component on the DN3000k10:
• VirtexII FPGA V cc INT (U11, U12, U20, U21, U22)
We also run +1.5 V a little hot. At worst case for all components, the
+1.5 V power supply should never fall below +1.50 V.
Table 6-2 Specification for +1.5 V Power
Minimum Typical Maximum
Voltage +1.55 V +1.56 V +1.58 V
Current N/A N/A 12 A
6-2 The DINI Group

Power Supplies and Power Distribution
If you use the DN3000k10 in a lab environment, the VirtexII FPGA will
never see worst case power and temperature—so you can use typical,
commercial timing.
NOTE: In a lab environment, the FPGA never sees the worst-case temperature
and power. You can use typical, commercial timing!
Header J21: Off-Board Power
J21 is a power header. A standard IDC cable can be attached to this header
and is useful for providing power to other circuits that may be attached to
the DN3000k10. This header is not keyed and the signals are not fused, so
make sure you get pin 1 in the correct location—putting a cable on this
header incorrectly will cause lots and lots of damage.
All the power rails are on this connector: +12 V, –12 V, +1.5 V, +5 V and
+3.3 V. The 0.25 pins on this header are rated at more than the 3 A per pin
so the cable probably limits the amount of power that you can get from
this header. We did not intend for this connector to provide the power to
the DN3000k10, so don’t use it for that purpose. The J21 Power Header is
shown in Figure 6-2.
J21
1
3
5
7
9
11
13
15
17
19
HDR10X2
2
4
6
8
10
12
14
16
18
20
+5V
+3.3V
+1.5V
+12V
-12V
+5V
+3.3V
+1.5V
+12V
-12V
Stand-Alone Operation
Figure 6-2 Header J21—Power
The DN3000k10 can be used stand-alone, meaning it doesn’t have to be
plugged into a PCI slot. Connector P1 is used to provide power to the
DN3000k10 in this configuration. P1 is a Molex drive power connector and
will connect to any standard ATX power supply (see Figure 6-3). The power
supply that we used is shown in Figure 6-4, but any ATX or AT style power
supply will work. We use a 250-watt ATX supply. Since the DN3000k10 does
not draw enough current to meet the minimums required by the supply,
we plug an old disk drive into another one of the Molex connectors. The
current drawn by the disk drive sinks enough current to make the
switchers in the power supply happy.
DN3000k10 User’s Manual 6-3

Power Supplies and Power Distribution
Figure 6-4 Example ATX Power Supply
The P1 connector is rated to 13 A, far more current than the DN3000k10
can use.
The DN3000k10, when used stand-alone, has the following different
power rails:
• +5 V
• +3.3 V
• +1.5 V
• +12 V
P1
1
2
3
4
+12V
+5V
Figure 6-3 Molex Connector P1—Auxiliary Power
6-4 The DINI Group

Power Supplies and Power Distribution
The power rail –12 V, if needed by a daughter card, can be supplied to the
DN3000k10 using the Power Header J21.
NOTE: If you use the DN3000k10 stand-alone with an ATX power supply,
the DN3000k10 may not draw enough current to meet the minimum
current required by the switchers in the supply. Connecting a disk drive
to another connector will solve this problem!
By specification, a PCI board may consume a maximum of 25 watts from
the fingers of the PCI connector. This power limit is below that the
DN3000k10 is capable of consuming, even if daughter cards and/or large
SDRAM banks are installed. The P1 connector can be used to augment the
power obtained from the PCI fingers. P1 can be used provided that the
+5 V and +12 V power rails on the connector are supplied by the same
power source as the PCI fingers.
DN3000k10 User’s Manual 6-5

Power Supplies and Power Distribution
6-6 The DINI Group

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Chapter 7
Daughter Connections to DN3000k10SD—
Observation Daughter Card for 200-pin
Connectors
The traditional approach to experiment with new devices involving wiring
together some ICs on a breadboard is fast becoming impractical and ineffective.
Instead, designers using new high-density devices need custom PC
boards representing a substantial investment of time and money.
Prototype boards from manufacturers can meet this demand for experimentation
while eliminating the expense and time involved with custom
PC boards. Additionally, such prototype boards facilitate the understanding
and advantages of new device features.
Purpose
Features
The DN3000k10SD daughter card allows external connection to the
signals present on the DN3000k10 series ASIC prototyping boards. The
DN3000k10 allows logic emulation with Virtex devices prior to committing
to using them for specific applications. It allows designers to try
Virtex features such as BlockRAM, DLLs, and SelectI/O resource, with an
off-the-shelf resource.
The DN3000k10 Daughter Card has the following features:
• Buffered I/O, Passive and Active Bus Drivers
• Unbuffered I/O
• Differential LVDS pairs (Note: Not available on DN3000k10 ASIC
prototyping board)
• Headers for Test Points
The daughter card contains headers that may be useful with certain types
of oscilloscope probes, or when wiring pins to prototype areas.
Figure 7-1 is a block diagram of the DN3000k10SD Daughter Card.
The DN3000k10SD Daughter Card is pictured in Figure 7-2.
Figure 7-3 shows the assembly drawing of the DN3000k10SD Daughter
Card.
The DN3000k10SD Daughter Card provides 16 differential pairs, 48 buffered
(passive/active) I/O, and 66 unbuffered I/O signals. The
DN3000k10 User’s Manual 7-1

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
J3, J4, J5, J6, J7- 50 PIN IDC HEADER
J5
ACLK1
BCLK1
CCLK1
ECLK1
MBCK6
UNBUFFERED I/O 0..17
DIFF CLOCK
DIFFERENTIAL
CONNECTOR
J2
J6 UNBUFFERED I/O 0..23
DIFF PAIR A0..A15
LINEAR REGULATOR
12VDC TO 3.3V/
3.9VDC
J7 UNBUFFERED I/O 0..23
50 PIN MINI D
RIBBON CABLE
CONNECTOR
J1
POWER
INDICATORS
BUFFERED I/O 0..15
U1
UNBUFFERED I/O 0..15
+3.3V +5.0V
+12.0V
J3
BUFFERED I/O 0..7
U2 UNBUFFERED I/O 0..15
text
POWER
HEADER
J4
BUFFERED I/O 0..7
BUFFERED I/O 0..15
U3 UNBUFFERED I/O 0..15
+1.5V
+3.3V
+5.0V
+12.0V
-12.0V
J6
GND
74LVC16245APA/
74FST163245PA
U1, U2, U3 - BUFFERS OR LEVEL TRANSLATORS
200 PIN MICROPAX
(BOTTOM OF PWB)
20 PIN IDC
HEADER
Figure 7-1 DN3000k10SD Daughter Card Block Diagram
7-2 The DINI Group

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Figure 7-2 DN3000k10 Daughter Card
DN3000k10 User’s Manual 7-3

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Figure 7-3 DN3000k10SD Daughter Card Assembly Drawing
IDT74FST163245 chips are used as bus switches in the passive mode, and
the IDT74LVC16245A chips are used as bus transceivers in the active mode.
The DN3k10SD has separate enable/direction signals for each driver.
NOTE: Availability of these I/O signals depends on the location of the
daughter card with respect to the development board.
Daughter Card
LEDs
Power Supply
The LEDs act as visual indicators, representing the active power sources.
• D1 — LED indicating +3.3 V present
• D2 — LED indicating +5.0 V present
• D3 — LED indicating +12 V present
Under normal operating conditions, all LEDs should be on.
A linear power supply (U4) is present to provide level shift/translation
functions when the board is populated with bus switches.
7-4 The DINI Group

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Options
Resistors R10 and R11 can be used to select different voltage sources, +5 V
or +3.3 V, respectively. When used, U4 must be removed in order to
prevent contention.
NOTE: Never populate R10/R11 simultaneously: this will result in a
shorted power supply.
Power Rating • +5 V power supply is rated for 1 A.
• +3.3 V power supply is rated for 1 A.
• +1.5 V power supply is rated for 1 A.
• +12 V power supply is rated for 0.5 A.
• –12 V power supply is rated for 0.5 A.
Connector J8 Table 7-1 shows the connections of J8.
Table 7-1 Connector J8 Pins External Power
Pin Function Pin Function
1 GND 11 GND
2 +5 V 12 +1.5 V
3 GND 13 GND
4 +5 V 14 +12 V
5 GND 15 GND
6 +3.3 V 16 +12 V
7 GND 17 GND
8 +3.3 V 18 –12 V
9 GND 19 GND
10 +1.5 V 20 –12 V
DN3000k10 User’s Manual 7-5

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
LVDS
Low-voltage differential signaling (LVDS) is a signaling method used for
high-speed transmission of binary data over copper. It is well recognized
that the benefits of balanced data transmission begin to outweigh the
costs over single-ended techniques when the signal transmission times
approach 10 ns. This represents signaling rates of about 30 Mbps or clock
rates of 60 MHz (in single-edge clocking systems) and above. LVDS is
defined in the TIA/EIA-644 standards.
NOTE: Not available on the DN3000k10 ASIC prototyping board.
Connector J2 This is a Mini D Ribbon (MDR) connector (50 pin) manufactured by 3M,
used specifically for high speed LVDS signaling. The connector mates with
a standard off-the-shelf 3M-cable assembly:
P/N 14150-EZBB-XXX-0LC
where XXX is:
050 = 0.5 m
150 = 1.5 m
300 = 3.0 m
500 = 5.0 m
Unbuffered I/O
Please contact 3M for further details: http://www1.3m.com/.
The DN3000k10SD Daughter Card provides 66 unbuffered I/O signals,
including 5 single ended clock signals. The function of these signals is
position dependent.
NOTE: SIgnals P4NX7 and P4NX6 are also used for direction select and
output enable on U2 and U3 respectively.
Connectors J3,
J4
Connector J5,
J6, J7
J3, J4— Buffered Interface header
IDC headers (50 pin) providing 48 buffered I/O signals.
See Table 7-2 on page 7-8.
J5, J6, J7 — Unbuffered Interface Header
IDC headers (50 pin) providing 66 buffered I/O signals.
See Table 7-2 on page 7-8.
7-6 The DINI Group

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Buffered I/O
The DN3000k10SD Daughter Card provides 48 buffered I/O signals. The
function of these signals is position dependent. U1, U2, and U3 allow for
different populating options, and devices can be active or passive.
Active
The LCV162245A is used for asynchronous communication between data
buses. It allows data transmission from the A to the B or from the B to the
A bus, depending on the logic level at the direction-control (DIR) input.
The output-enable (OE#) input can be used to disable the device so that
the busses are effectively isolated.
Passive
The FST163245 bus switches are used to connect or isolate two ports
without providing any current sink or source capabilities. Thus, they
generate little or no noise of their own while providing a low resistance
path for an external driver. The output-enable (OE#) input can be used to
disable the device so that the busses are effectively isolated.
Test Interface
Connector J1
The DN3000k10SD Daughter Card provides a 200-pin connector to interface
to one of three test connectors on the DN3000k10 ASIC prototyping
board: J25, J26 and J28.
J1—Test Interface Connector
Micropax connector (200 pin) used as a standard interface to all the DINI
Group development boards. This connector has a specified current rating
of 0.5 amps per contact. See Table 7-2 on page 7-8.
DN3000k10 User’s Manual 7-7

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Daughter Card I/O Connections
Daughter Card
Connections
Table 7-2 shows the DN3000k10SD Daughter Card I/O Interconnects to
connectors J25, J26 and J28.
Table 7-2 DN3000k10SD Daughter Card I/O Interconnects
J25,
J26, or
J28 Pin
No.
J1 Signal Conn Signal
DN3000k10 I/O Connec tor
J25 J26 J28
FPGA
Pin
Signal
FPGA
Pin
Signal
1 +12 V 1 +12 V +12 V +12 V
2 GND 2 GND GND GND
3 ACLK[1] J5.1 3 ACLK[6] ACLK[7] ACLK[8]
4 +5 V 4 +5 V +5 V +5 V
5 BCLK[1] J5.3 5 BCLK[6] BCLK[7] BCLK[8]
6 +5 V 6 +5 V +5 V +5 V
7 CCLK[1] J5.5 7 CCLK[6] CCLK[7] CCLK[5]
8 GND 8 GND GND GND
9 +3.3 V 9 +3.3 V +3.3 V +3.3 V
10 P2N[3] J3.1 10 ECLK[15] ECLK[5]
11 GND 11 GND GND GND
12 P2N[2] J3.3 12 MB[161]
13 P2N[1] J2.8 13 MB[167]
14 P2N[0] J2.9 14 MB[162]
15 P2NX[7] J3.5 15 MB[168]
16 P2NX[6] J3.7 16 MB[164]
17 P2NXP5[ J3.9 17 MB[152]
18 P2NX[4] J3.11 18 MB[175]
19 P2NX[1] J2.10 19 MB[226]
20 P2NX[0] J2.11 20 MB[153]
21 P3NX[9] J2.40 21 MB[177] MB[176]
22 GND 22 GND GND GND
23 P3NX[8] J2.41 23 MB[188] MB[185]
24 P3NX[5] J3.13 24 MB[207] MB[189]
25 P3NX[4] J3.15 25 MB[199] MB[206]
26 P3N[89] J3.17 26 MB[190] MB[225]
FPGA
Pin
7-8 The DINI Group

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Daughter Card
Connections
Table 7-2 DN3000k10SD Daughter Card I/O Interconnects
J25,
J26, or
J28 Pin
No.
J1 Signal Conn Signal
DN3000k10 I/O Connec tor
27 P3N[88] J3.19 27 MB[186] MB[222]
28 P3N[87] J3.21 28 MB[193] MB[218] AHDR[68] U11-H6
29 P3N[86] J3.23 29 MB[200] MB[216]
30 P3N[83] J3.25 30 MB[191] MB[221] AHDR[67] U11-J6
31 P3N[82] J3.27 31 MB[187] MB[217]
32 P3N[77] J3.29 32 MB[194] MB[215] AHDR[66] U11-K7
33 GND 33 GND GND GND
34 P3N[76] J3.31 34 MB[201] MB[180] AHDR[65] U11-K6
35 P3N[75] J3.33 35 MB[192] MB[171] AHDR[64] U11-L9
36 P3N[74] J3.35 36 MB[223] MB[166]
37 P3N[69] J2.42 37 MB[172] MB[170] AHDR[63] U11-M7
38 P3N[68] J2.43 38 MB[179]
39 P3N[67] J3.37 39 AHDR[62] U11-N6
40 P3N[66] J3.39 40 MB[165]
41 P3N[63] J3.41 41 AHDR[61] U11-R6
42 P3N[62] J3.43 42 MB[178]
J25 J26 J28
FPGA
Pin
Signal
FPGA
Pin
43 P3N[57] J3.45 43 MB[169] AHDR[60] U11-V6
44 GND 44 GND GND GND
45 P3N[56] J3.47 45 AHDR[74] U11-H28 DHDR[44] U21-H28 AHDR[59] U11-W6
46 P3N[55] 46 AHDR[73] U11-H26 DHDR[45] U21-H29
47 P3N[54] 47 AHDR[72] U11-G24 DHDR[46] U21-K28 AHDR[58] U11-AA6
48 P3N[49] J4.1 48 AHDR[71] U11-J23 DHDR[47] U21-M28
49 P3N[48] J4.3 49 AHDR[70] U11-J12 DHDR[49] U21-P29 A2D[15] U11-T3
50 P3N[47] J2.19 50 AHDR[69] U11-J11 DHDR[48] U21-N28 A2D[52] U11-U6
51 P3N[46] J2.20 51 A2D[48] U11-G5 DHDR[54] U21-W28
52 P3N[43] J4.5 52 FB[31] DHDR[50] U21-R29 AHDR[57] U11-AJ4
53 P3N[42] J4.7 53 DHDR[55] U21-W27
Signal
54 P3N39 J4.9 54 AB[90] U11-G25 DHDR[51] U21-T29 AHDR[56] U11-AK4
55 GND 55 GND GND GND
FPGA
Pin
56 P3N[38] J4.11 56 AB[79] U11-F25 DHDR[52] U21-U26 AHDR[43] U11-AD9
DN3000k10 User’s Manual 7-9

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Daughter Card
Connections
Table 7-2 DN3000k10SD Daughter Card I/O Interconnects
J25,
J26, or
J28 Pin
No.
J1 Signal Conn Signal
DN3000k10 I/O Connec tor
J25 J26 J28
FPGA
Pin
Signal
FPGA
Pin
57 P3N[35] J4.13 57 AB[92] U11-F24 DHDR[56] U21-AA29 AHDR[52] U11-AC8
58 P3N[34] J4.15 58 AB[118] U11-H23 DHDR[53] U21-V28 AHDR[54] U11-AD7
59 P3N[29] J4.17 59 DHDR[57] U21-AB29 A2D[70] U11-AE6
60 P3N[28] J4.19 60 AB[77] U11-G26 DHDR[0] U21-H26 A2D[71] U11-AE7
61 P3N[27] J4.21 61 AB[110] U11-H25 DHDR[1] U21-J29 AHDR[55] U11-AF6
62 P3N[26] J4.23 62 AB[74] U11-G22 DHDR[2] U21-J28
Signal
63 P3N[23] J2.21 63 AB[65] U11-G23 DHDR[3] U21-K29 A2D[72] U11-AF7
64 P3N[22] J2.22 64 AB[111] U11-H24 DHDR[4] U21-L29 A2D[73] U11-AF8
65 P3N[19] J4.25 65 AB[81] U11-F22 DHDR[5] U21-L28 AHDR[34] U11-L7
66 GND 66 GND GND GND
67 P3N[18] J4.27 67 AB[87] U11-K23 DHDR[6] U21-M27 AHDR[35] U11-M8
68 P3N[15] J4.29 68 AB[117] U11-H21 DHDR[7] U21-N29 AE[114] U11-AL6
69 P3N[14] J4.31 69 AB[122] U11-K22 DHDR[8] U21-P27 AE[113] U11-AM6
70 P3N[9] J2.23 70 AB[76] U11-F21 DHDR[9] U21-N25 AE[112] U11-AM7
71 P3N[8] J2.24 71 AB[109] U11-F20 DHDR[10] U21-R28 AE[108] U11-AJ9
72 P3N[7] J4.33 72 AB[99] U11-H20 DHDR[11] U21-R27 AE[107] U11-AL9
73 P3N[6] J4.35 73 AB[89] U11-K21 DHDR[12] U21-T28 AE[59] U11-AM9
74 P3N[3] J4.37 74 AB[116] U11-J21 DHDR[13] U21-U28 AE[63] U11-AL11
75 P3N[2] J4.39 75 AB[78] U11-G19 DHDR[14] U21-U27 AE[64] U11-AM11
76 P4N27 J4.41 76 AB[114] U11-K20 DHDR[15] U21-V27 AE[65] U11-AJ12
77 GND 77 GND GND GND
FPGA
Pin
78 P4N[26] J4.43 78 AB[66] U11-J22 DHDR[16] U21-Y29 AE[69] U11-AL13
79 P4N[21] J4.45 79 AB[91] U11-J20 DHDR[17] U21-Y28 AE[70] U11-AM13
80 P4N[20] J4.47 80 AB[80] U11-K24 DHDR[18] U21-AA27 AE[71] U11-AK14
81 P4N[19] 81 AB[93] U11-K19 DHDR[19] U21-AB28 AE[76] U11-AJ16
82 P4N[18] 82 AB[64] U11-H19 DHDR[20] U21-AB25 AE[77] U11-AL16
83 P4N[13] 83 AB[124] U11-H15 DHDR[21] U21-AC28 AE[78] U11-AM16
84 P4N[12] 84 AB[123] U11-K13 DHDR[22] U21-AC27 AE38 U11-AD17
85 P4N[11] 85 AB[106] U11-H18 DHDR[23] U21-AD29 AE[84] U11-AD18
86 P4N[10] 86 AB[112] U11-F15 DHDR[24] U21-AD28 AE[85] U11-AH18
7-10 The DINI Group

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Daughter Card
Connections
Table 7-2 DN3000k10SD Daughter Card I/O Interconnects
J25,
J26, or
J28 Pin
No.
J1 Signal Conn Signal
DN3000k10 I/O Connec tor
J25 J26 J28
FPGA
Pin
Signal
FPGA
Pin
Signal
87 P4N[7] 87 AB[97] U11-J17 DHDR[25] U21-AD25 AE[86] U11-AJ18
88 GND 88 GND GND GND
89 P4N[6] 89 AB[121] U11-K17 DHDR[26] U21-AF24 AE[90] U11-AL19‘
90 P4N[3] 90 AB[94] U11-F14 DHDR[27] U21-AF23 AE[91] U11-AJ19
91 P4N[2] 91 AB[104] U11-G16 DHDR[28] U21-AJ32 AE[92] U11-AM20
92 P4NX[11] 92 AB[68] U11-H14 DHDR[29] U21-AJ31 AE[93] U11-AL20
93 +1.5 V 93 +1.5 V +1.5 V +1.5 V U22-N14
94 P4NX[10] 94 AB[108] U11-J15 DHDR[30] U21-AK32 AE[97] U11-AM22
95 P4NX[7] J7.45 95 AB[115] U11-G12 DHDR[31] U21-AK31 AE[98] U11-AL22
96 P4NX[6] J7.47 96 AB[73] U11-K14 DHDR[32] U21-AL32 AE[99] U11-AK22
97 P4NX[5] 97 AB[63] U11-G11 DHDR[33] U21-AF13 AE[100] U11-AM23
98 P4NX[4] 98 AB[113] U11-K12 DHDR[34] U21-AG13 AE[101] U11-AL23
99 GND 99 GND GND GND
100 –12 V 100 –12 V –12 V -12 V
101 GND 101 GND GND GND
102 MBCK[1] J2.27 102 ADIFF[1] U11-H17 BDIFF[1] U21-AF18 FDIFF[1] U22-AF18
103 +1.5 V 103‘ +1.5 V +1.5 V +1.5 V
104 MBCK[0] J2.28 104 ADIFF[0] U11-H16 BDIFF[0] U12-J18 FDIFF[0] U22-AF17
105 +3.3 V 105 +3.3 V +3.3 V +3.3 V
106 MBCK[6] J5.9 106 DCLK[6] ECLK[14] DCLK[5]
107 GND 107 GND GND GND
108 ECLK[1] J5.7 108 MBCK[1] MBCK[2] MBCK[0]
109 GND 109 GND GND GND
110 GND 110 GND GND GND
FPGA
Pin
111 P2N[5] J5.15 111 MB[181] BHDR[25] U12-A22 AB[105] U11-H11
112 P2N[4] J5.17 112 MB[195] BHDR[26] U12-B22 AB[125] U11-G9
113 P2NX[11] J2.2 113 MB[202] BHDR[27] U12-A23 AB[103] U11-H10
114 P2NX[10] J2.1 114 MB[210] BHDR[28] U12-B23 AB[70] U11-H9
115 P2NX[9] J5.19 115 MB[224[ BHDR[29] U12-A24 AB[230] U11-J10
116 P2NX[8] J5.21 116 MB[211] BHDR[30] U12-B24 AB[69] U11-J8
DN3000k10 User’s Manual 7-11

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Daughter Card
Connections
Table 7-2 DN3000k10SD Daughter Card I/O Interconnects
J25,
J26, or
J28 Pin
No.
J1 Signal Conn Signal
DN3000k10 I/O Connec tor
J25 J26 J28
FPGA
Pin
Signal
FPGA
Pin
Signal
117 P2NX[3] J5.23 117 MB[173] BHDR[31] U12-B25 A2D[42] U11-F5
118 GND 118 GND GND GND
119 P2NX[2] J5.25 119 MB[182] BHDR[24] U12-B21 A2D[23] U11-F4
120 P3NX[11] J2.29 120 MB[196] BHDR[23] U12-A21 A2D[50] U11-G3
121 P3NX[10] J2.30 121 MB[203] BHDR[22] U12-A20 A2D[20] U11-F3
122 P3NX[7] J2.31 122 MB[219] BHDR[21] U12-B19 A2D[22] U11-H5
123 P3NX[6] J2.32 123 B[220] BHDR[20] U12-B18 A2D[66] U11-H4
124 P3NX[3] J5.27 124 MB[174] BHDR[19] U12-A18 A2D[21] U11-J3
125 P3NX[2] J5.29 125 MB[183] BHDR[18] U12-C18 A2D[62] U11-K5
126 P3NX[1] J5.31 126 MB[197] BHDR[17] U12-A17 A2D[43] U11-J4
127 P3NX[0] J5.33 127 MB[204] BHDR[16] U12-B17 A2D[57] U11-G6
128 P3N[85] J5.35 128 MB[212] BHDR[15] U12-B16 A2D[49] U11-L4
129 GND 129 GND GND GND
130 P3N[84] J5.37 130 MB[208] BHDR[14] U12-A15 A2D[36] U11-H3
131 P3N[81] J5.39 131 MB[213] BHDR[13] U12-A14 A2D[10] U11-L3
132 P3N[80] J5.41 132 MB[184] BHDR[12] U12-B14 A2D[37] U11-K4
133 P3N[79] J2.3 133 MB[198] BHDR[11] U12-A13 A2D[61] U11-M6
134 P3N[78] J2.4 134 MB[205] BHDR[10] U12-B13 A2D[17] U11-N5
135 P3N[73] J2.6 135 MB[214] BHDR[9] U12-A12 A2D[39] U11-N4
136 P3N[72] J2.7 136 MB[209] BHDR[8] U12-B12 A2D[27] U11-N3
137 P3N[71] J2.33 137 MB[154] BHDR[7] U12-A11 A2D[56] U11-M4
138 P3N[70] J2.34 138 MB[155] BHDR[6] U12-B11 A2D[65] U11-J5
139 P3N[65] J5.43 139 MB[156] BHDR[5] U12-B10 A2D[47] U11-L5
140 GND 140 GND GND GND
FPGA
Pin
141 P3N[64] J5.45 141 MB[157] BHDR[4] U12-A9 A2D[7] U11-P5
142 P3N[61] J5.47 142 MB[158] BHDR[3] U12-B9 A2D[16] U11-P3
143 P3N[60] J5.49 143 MB[159] BHDR[2] U12-B8 A2D[40] U11-R4
144 P3N[59] J6.1 144 MB[160] BHDR[1] U12-A7 A2D[68] U11-R3
145 P3N[58] J6.3 145 MB[161] BHDR[0] U12-B7 A2D[8] U11-M3
146 P3N[53] J6.5 146 DHDR[35] U21-AE12 A2D[6] U11-T5
7-12 The DINI Group

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Daughter Card
Connections
Table 7-2 DN3000k10SD Daughter Card I/O Interconnects
J25,
J26, or
J28 Pin
No.
J1 Signal Conn Signal
DN3000k10 I/O Connec tor
J25 J26 J28
FPGA
Pin
Signal
FPGA
Pin
Signal
147 P3N[52] J6.7 147 MB[163] DHDR[36] U21-AF12 A2D[33] U11-P4
148 P3N[51] J2.17 148 MB[164] DHDR[37] U21-AF11 AWD[26] U11-U5
149 P3N[50] J2.18 149 MB[226] DHDR[38] U21-AA10 A2D[5] U11-U4
150 P3N[45] J6.9 150 AB[126] U11-A29 DHDR[39] U21-Y10 A2D[59] U11-T4
151 GND 151 GND GND GND
152 P3N[44] J6.11 152 AHDR[33] U11-B28 DHDR[40] U21-W10 AHDR[36] U11-N8
153 P3N[41] J6.13 153 AHDR[32] U11-A28 DHDR[41] U21-AA9 AHDR[39] U11-P8
154 P3N[40] J6.15 154 AHDR[31] U11-B27 DHDR[42] U21-Y9 AHDR[37] U11-R7
155 P3N[37] J6.17 155 AHDR[30] U11-B26 DHDR[43] U21-W8 AHDR[38] U11-T7
156 P3N[36] J6.19 156 AHDR[29] U11-A26 BHDR[32] U12-AE30 AHDR[40] U11-U7
157 P3N[33] J6.21 157 AHDR[28] U11-B25 BHDR[33] U12-AF30 AHDR[41] U11-R8
158 P3N[32] J6.23 158 AHDR[27] U11-B24 BHDR[34] U12-AG28 AHDR[42] U11-AB9
159 P3N[31[ J2.44 159 AHDR[26] U11-A24 BHDR[35] U12-AG30 AHDR[44] U11-Y8
160 P3N[30] J2.45 160 AHDR[25] U11-B23 BHDR[36] U12-AG31 AHDR[45] U11-V8
161 P3N[25] J6.25 161 AHDR[24] U11-A23 AHDR[46] U11-V7
162 GND 162 GND GND GND
163 P3N[24] J6.27 163 AHDR[23] U11-B22 BHDR[38] U12-AH29 AHDR[47] U11-Y6
164 P3N[21] J6.29 164 AHDR[22] U11-A22 BHDR[39] U12-AH32 HDR[48] U11-Y7
165 P3N[20] J6.31 165 AHDR[21] U11-B21 BHDR[40] U12-AJ31 AHDR[49] U11-AA8
166 P3N[17] J6.33 166 AHDR[20] U11-A21 BHDR[41] U12-AJ32 AHDR[50] U11-AB7
167 P3N[16] J6.35 167 AHDR[19] U11-A20 BHDR[42] U12-AK31 AHDR[53] U11-AD6
168 P3N[13] J6.37 168 AHDR[18] U11-B19 BHDR[43] U11-AK32 AHDR[51] U11-AC7
169 P3N[12] J639 169 AHDR[17] U11-B18 BHDR[44] U12-J24 A2D[69] U11-AG6
170 P3N[11] J2.47 170 AHDR[16] U11-A18 BHDR[45] U12-F14 AE[111] U11-AH9
171 P3N[10] J2.48 171 AHDR[15] U11-C18 BHDR[46] U12-H11 AE[110] U11-AL8
172 P3N[5] J6.41 172 AHDR[14] U11-A17 BHDR[47] U12-J11 AE[109] U11-AM8
173 GND 173 GND GND GND
FPGA
Pin
174 P3N[4] J6.43 174 AHDR[13] U11-B17 BHDR[48] U12-F10 AE[60] U11-AK10
175 P3N[1] J6.45 175 AHDR[12] U11-B16 BHDR[37] U12-H7 AE[61] U11-AL10
176 P3N[0] J6.47 176 AHDR[11] U11-A15 EHDR[0] U20-Y29 AE[62] U11-AK11
DN3000k10 User’s Manual 7-13

Daughter Connections to DN3000k10SD—Observation Daughter Card for 200-pin Connectors
Daughter Card
Connections
Table 7-2 DN3000k10SD Daughter Card I/O Interconnects
J25,
J26, or
J28 Pin
No.
J1 Signal Conn Signal
DN3000k10 I/O Connec tor
J25 J26 J28
FPGA
Pin
Signal
FPGA
Pin
Signal
177 P4N[25] J7.1 177 AHDR[10] U11-A14 EHDR[1] U20-W28 AE[66] U11-AL12
178 P4N[24] J7.3 178 AHDR[9] U11-B14 EHDR[2] U20-W27 AE[67] U11-AM12
179 P4N23 J7.5 179 AHDR[8] U11-A13 EHDR[3] U20-Y28 AE[68] U11-AK13
180 P4N[22] J7.7 180 AHDR[7] U11-B13 EHDR[4] U20-Y27 AE[72] U11-AL14
181 P4N[17] J7.9 181 AHDR[6] U11-A12 EHDR[5] U20-AA29 AE[73] U11-AM14
182 P4N[16] J7.11 182 AHDR[5] U11-B12 EHDR[6] U20-AA27 AE[75] U11-AM15
183 P4N[15] J7.13 183 AHDR[4] U11-A11 EHDR[7] U20-H7 AE[74] U11-AL15
184 GND 184 GND GND GND
185 P4N[14] J7.15 185 AHDR[3] U11-B11 AE[79] U11-AH16
186 P4N[9] J7.17 186 AHDR[2] U11-B10 AE[80] U11-AH17
187 P4N[8] J7.19 187 AHDR[1] U11-B3 AE[81] U11-AL17
188 P4N[5] J7.21 188 AHDR[0] U11-C2 AE[82] U11-AJ17
189 P4N[4] J7.23 189 AB[95] U11-K16 AE[87] U11-AL18
190 P4N[1] J7.25 190 AB[83] U11-F13 AE[88] U11-AH19
191 P4N[0] J7.27 191 AB[86] U11-G13 AE[89] U11-AM19
192 P4NX[13] J7.29 192 AB[102] U11-K15 AE[94] U11-AM21
193 P4NX[12] J7.31 193 AB[96] U11-J14 AE[95] U11-AL21
194 P4NX[9] J7.33 194 AB[84] U11-H12 AE[96] U11-AK21
195 GND 195 GND GND GND
FPGA
Pin
196 P4NX[8] J7.35 196 AB[75] U11-F11 AE[102] U11-AJ23
197 P4NX[3] J7.37 197 AB[88] U11-J13 AE[103] U11-AM24
198 P4NX[2] J7.39 198 AB[107] U11-H13 AE[105] U11-AL24
199 P4NX[1] J7.41 199 AB[98] U11-G10 AE[105] U11-AK24
200 P4NX[0] J7.43 200 AB[85] U11-F10 AE[106] U11-AL[25]
7-14 The DINI Group

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
Chapter 8
Reset Schemes, LEDs, Bus Bars and 200 Pin
Connectors
Reset Schemes
A LTC1326 chip from Linear Technology controls reset functionality for the
DN3000k10. Figure 8-1 shows the distribution of the reset signal PWRRST-.
In addition to controlling the reset, the power supplies rails +5 V, +3.3 V,
and +1.5 V are threshold detected by the LTC1326. Undervoltage conditions
will case the assertion of the reset signal.
The LTC1326 has a push-button. Momentarily depressing this button
causes a 200 ms reset pulse on the signal PWRRST-. If the push-button is
depressed for 2 seconds and held, PWRRST- is asserted continuously. LED5,
when lit, means that reset is asserted, so if you press and hold S1, you
should see LED5 illuminate after a few seconds. If LED5 illuminates for any
reason during normal operation, this indicates that PWRRST- is active and
that something is wrong. Note that if you press S1 and release it quickly,
you probably won’t see LED5 since the 200 ms reset pulse is not strong
long enough for the eye to observe.
Depressing the push-button S1 causes the following sequence of events:
1. Reset of the CPLD and µP
2. FPGA configuration is cleared
3. If the jumpers on J17 are set for SelectMAP and there is a
valid SmartMedia card inserted into the socket, then the FPGA
will be configured. A SmartMedia card is valid if it complies
with the SSFDC specification and contains a file named
main.txt in the root directory. If the card is invalid or there is
no card present, then the FPGA will not be configured.
4. The Main Menu will appear.
The identical sequence of events occurs at power-up.
DN3000k10 User’s Manual 8-1

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
+3.3 V
Reset
Button
U2
S1
Reset
Control
PST
LT1326
+5 V
+3.3 V
+1.5 V
Power
Supply
Monitor
SRRST
PWRRST
CPLD
U13
LED
J18
µP
Programming
Header
µP
ATmega128
U3
Figure 8-1 Reset Functionality
8-2 The DINI Group

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
LEDs
The DN3000k10 has eight LEDs that are used to visually communicate the
status of circuitry (Figure 8-2).
Figure 8-2 DN3000k10 LEDs
From left to right, the LEDs are labeled: LED0, LED1, LED2, LED3, LED4, LED5,
LOCK1, LOCK2 (see Figure 8-3).
U19
U17
LOCK for Roboclock II 2
LED0 LED1 LED2 LED3 LED4 LED5 LOCK for Roboclock II 1
Figure 8-3 DN3000k10 LED Diagram
The LEDs have the following functions:
LED0
LED[3:1]
Lights when the configuration process from the SmartMedia
was successful.
These three LEDs have multiple meanings:
• When all 3 LEDs are blinking, then the µP has been reprogrammed
and is waiting for the user to enter FPGA stuffing
information via serial port or there is not a valid SmartMedia
card present and the FPGA has been configued.
DN3000k10 User’s Manual 8-3

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
LED4
LED5
LOCK1
LOCK2
• During configuration, the combination of LEDs lit tells the
user which FPGA is currently being configured (LED3, LED2,
LED1):
— off, off, on = FPGA F
— off, on, off = FPGA A
— off, on, on = FPGA E
— on, off, off = FPGA B
— ON, OFF, ON = FPGA D
lights when any of the FPGAs are NOT configured
lights when reset is asserted (PWRRST-)
lights when the PLL in RoboclockII 1 is LOCKED
lights when the PLL in RoboclockII 2 is LOCKED
You are free to reprogram the CPLD to use any or all of the LEDs for your
own purposes.
J29 — LED
Signals Header
The header J29 (Figure 8-4) contains the LED signals for oscilloscope observations
and debugging. You can also route FPGA signals through the CPLD
to this header for debug purposes.
+5V
1
2
3
4
U19
FRONT
ANODE1
ANODE2
ANODE3
ANODE4
CATHODE1
CATHODE2
CATHODE3
CATHODE4
555-4003
Status LEDs
8
7
6
5
LED0
LED1
LED2
LED3
J29
1 2
3 4
5 6
7 8
HDR4X2
1
2
3
4
U17
FRONT
ANODE1
ANODE2
ANODE3
ANODE4
CATHODE1
CATHODE2
CATHODE3
CATHODE4
8
7
6
5
LED4
LED5
LOCK_N1
LOCK_N2
555-4003
Figure 8-4 J29 LED Signals Header
The Pin Outs for J29 are shown in Table 8-1.
Table 8-1 J29 Pin Outs
Pin
Signal
1 LED0
2 LOCK_N2
3 LED1
4 LOCK_N1
8-4 The DINI Group

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
Table 8-1 J29 Pin Outs
Pin
Signal
5 LED2
6 LED5
7 LED3
8 LED4
Bus Bars
The two bus bars, B1 and B2, are installed to prevent flexing of the PWB
and serve no other purpose. They are connected quite solidly into the
ground plane of the DN3000k10 at every hole, and you can use the metal
bars to ground-test equipment such as oscilloscopes and pattern generators.
Be careful not to short any power rails or signals to these metal
bars—they can carry a lot of current. The PCI bracket, BRK1, is also
connected to the ground plane at each of the screw mounts.
The 200 Pin Connectors: J28, J25, J26
The DN3000k10 contains three 200-pin connectors, J28, J25 and J26.
Daughter cards of any sort may be plugged into these connectors. The
relative pin location of the powers, grounds, and signals is identical for
each of the three connectors, which means that the same daughter card
can be plugged into any of the three slots. A hole that can be used to
attach a standoff is located at the same relative position from each
connector Figure 8-5. This hole is grounded on the DN3000k10, so connect
this mounting hole to digital ground on your daughter card.
The mechanical position of the 200-pin connectors on the DN3000k10 is
shown in Figure 8-5. The 200-pin connector used on the DN3000k10 is a
Berg Electronics 91294-003 in the Micropax family. This link will take you
to the Berg website: http://www.berg.com/. This Berg connector was
chosen because of its high pin density, performance, and availability. The
part number for the mating connector is 91403-003. We stock the mating
connector at our offices in La Jolla, CA, so if you are designing a daughter
card and are having trouble getting this part, call us. We would be happy
to send you a few at our cost. Appendix A contains a mechanical
datasheet for both the Berg 91403-003 and 91294-003 connectors.
This style of connector has four mounting holes—two screw holes at each
end and two alignment holes between pins 50–51 and after pin 100 (see
Figure 8-5). These mounting holes are part of the metal shell of the
connector and make an important connection to the mating connector.
All four of these mounting holes are connected to digital ground on the
DN3000k10—therefore, the shell of the connector is grounded.
We used the pin numbering shown in Figure 8-5 for the 200-pin,
91294-003 connectors.
The Signals
Each of the three 200-pin connectors has the following:
DN3000k10 User’s Manual 8-5

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
• 162 signals connected to the FPGA
– All 162 are connected to the FPGA
– A subset of the 162 are also connected to the memories
• 7 clocks
• The following power rails:
– +12V (1 pin)
– -12V (1 pin)
– +5V (2 pins)
– +3.3V (2 pins)
– +1.5V (2 pins)
– GND (23 pins + case)
Regarding the amount of current that the power pins can carry, the
following text is lifted directly from the specification for the Micropax
family of connectors:
1
101
Mounting Holes
50 150
51
151
100
200
Figure 8-5 91294-003 Pin Numbering
8-6 The DINI Group

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
6.1 Current Rating. Current rating shall be evaluated in still air at
25°C ambient temperature. Under the following conditions, the
temperature rise shall be no greater than 30°C:
All contacts powered at 0.5 amp
One contact powered at 3.0 amps
Most of the signals are TTL (or some low current variation such as LVDS), so
you can reasonably expect to get up to 3 amps per power pin through this
connector. Remember that the +3.3V and +1.5V power supplies are
limited to 5 amps total—the memories, the FPGA and the clock circuitry on
the DN3000k10 consume +3.3V. The FPGA only consumes +1.5V.
If you need more power, consider using a cable connecting J21 to your
daughter card in addition to the pins on the 200-pin connectors. See
“Header J21: Off-Board Power” on page 6–3. for more detail.
If you use the DN3000k10 stand-alone (meaning that it is not plugged into
a PCI slot), the auxiliary power connector has +5V and +12V, but does not
have –12V. So unless you provide –12V to the DN3000k10 via another
connection, –12V will not be available for use by a daughter card.
NOTE: –12V is not required by the DN3000k10. The DN3000k10 will
operate normally without a –12V power supply.
Some of the interconnect with the 200-pin connectors is shared with the
memories. See Figure 5-1 on page 5-2 to see which signals are shared. J25
(CON1) has no signals that are shared (Figure 8-6).
Notes:
• Be careful with the control signals for the SSRAMs that are shared
with J25 and J28. If the OE is active, the SSRAM drives its data bus.
If the CEs are active, a write may occur.
• The signals designated “MBCK” where “” is 0, 1, 2, 3, 4, 5, 6, 7 or
8 are connected only between the 200-pin connectors and the
FPGA. These signals are connected to a clock input pin on the
FPGA, and therefore can be used as a method to externally clock
the FPGA. Also, some of MBCK’s may be combined to provide differential
I/Os.
DN3000k10 User’s Manual 8-7

Reset Schemes, LEDs, Bus Bars and 200 Pin Connectors
8-8 The DINI Group
con1 con2 con3
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
+3.3V
-12V
+12V
ACLK8
BCLK8
DCLK5
GND
GND
+3.3V
+1.5V
+1.5V
CCLK5
GND
-12V
+5V
BCLK6
DCLK6
ACLK6
+1.5V
CCLK6
+3.3V
GND
GND
+12V
GND
GND
GND
GND
GND
GND
+1.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3.3V
GND
GND
GND
GND
GND
GND
+5V
-12V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+1.5V
GND
GND
+5V
GND
BCLK7
GND
ACLK7
GND
+12V
+3.3V
GND
+1.5V
GND
GND
GND
+3.3V
GND
CCLK7
+5V
GND
GND
GND
+5V
GND
GND
GND
GND
GND
GND
ECLK14
MBCK0 MBCK1 MBCK2
FDIFF1
FDIFF0
ADIFF1
ADIFF0
BDIFF1
BDIFF0
ECLK5
BHDR25
BHDR26
BHDR28
BHDR27
BHDR30
BHDR29
BHDR31
BHDR1
BHDR0
BHDR6
BHDR7
BHDR5
BHDR9
BHDR10
BHDR8
BHDR12
BHDR13
BHDR11
BHDR16
BHDR17
BHDR15
BHDR19
BHDR20
BHDR22
BHDR23
BHDR21
BHDR24
BHDR14
BHDR4
BHDR2
BHDR3
BHDR18
ECLK15
AHDR33
AHDR32
AHDR31
AHDR30
AHDR27
AHDR29
AHDR28
AHDR26
AHDR21
AHDR23
AHDR22
AHDR20
AHDR17
AHDR19
AHDR18
AHDR16
AHDR11
AHDR13
AHDR12
AHDR10
AHDR7
AHDR9
AHDR8
AHDR6
AHDR1
AHDR3
AHDR2
AHDR0
AHDR5
AHDR4
AHDR15
AHDR14
AHDR25
AHDR24
AE114
AE113
AE112
AE108
AE107
AE63
AE64
AE59
AE69
AE71
AE76
AE70
AE77
AE83
AE84
AE78
AE90
AE92
AE93
AE91
AE97
AE99
AE100
AE98
AE101
AE85
AE86
AE65
AE81
AE82
AE79
AE80
AE89
AE94
AE87
AE88
AE104
AE105
AE102
AE103
AE62
AE66
AE60
AE61
AE72
AE73
AE67
AE68
AE111
AE110
AE109
AE75
AE74
AE95
AE96
AE106
MB161
MB167
MB162
MB168
MB226
MB175
MB152
MB164
MB225
MB206
MB189
MB185
MB221
MB216
MB218
MB222
MB153
MB176
MB217
MB215
MB166
MB180
MB179
MB171
MB170
MB169
MB165
MB178
DHDR46
DHDR44
DHDR49
DHDR45
DHDR47
DHDR50
DHDR48
DHDR51
DHDR54
DHDR55
DHDR53
DHDR52
DHDR56
DHDR57
AHDR43
AHDR52
AHDR54
A2D70
AHDR55
A2D71
A2D72
A2D73
AHDR34
AHDR35
AB105
AB125
AB103
AB70
AB69
AB120
A2D42
A2D20
A2D50
A2D22
A2D23
A2D62
A2D21
A2D43
A2D66
AHDR51
AHDR53
A2D69
AHDR50
AHDR45
AHDR44
AHDR46
AHDR42
AHDR40
AHDR38
AHDR41
AHDR37
A2D5
A2D26
A2D59
A2D33
A2D8
A2D68
A2D6
A2D40
A2D37
A2D10
A2D61
A2D36
A2D27
A2D39
A2D56
A2D17
A2D49
A2D57
A2D47
A2D65
A2D16
A2D7
AHDR39
AHDR36
AHDR48
AHDR47
AHDR49
MB177
MB188
MB207
MB199
MB190
MB193
MB200
MB191
MB186
MB192
MB223
MB172
MB201
A2D48
FB31
AB92
AB118
AB79
AB110
AB74
AB65
AB77
AB117
AB122
AB76
AB87
AB99
AB89
AB116
AB109
AB91
AB80
AB93
AB66
AB124
AB123
AB106
AB64
AB94
AB104
AB68
AB121
AB115
AB73
AB63
AB108
AB113
AB112
AB97
AB78
AB114
AB111
AB81
AB90
MB187
MB194
MB181
MB195
MB202
MB210
MB224
MB211
MB173
MB196
MB220
MB219
MB174
MB182
MB183
MB203
MB213
MB205
MB198
MB214
MB208
MB209
MB184
MB158
MB161
MB160
MB157
MB163
MB159
MB212
MB204
MB197
MB156
MB155
MB154
AB126
MB226
MB164
A2D15
A2D52
AB98
AB96
AB95
AB75
AB85
AB88
AB86
AB107
AB102
AB84
AB83
GND
AHDR56
GND
AHDR68
AHDR67
AHDR66
AHDR65
AHDR63
AHDR64
AHDR61
AHDR62
AHDR59
AHDR58
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Figure 8-6 200 Pin Connectors — Signal Connections

Chapter 9
Utilities
PCI Debug—General Pontificating
PC-Based—AETEST.EXE
Debugging of PCI-based hardware can be troublesome, so it is best to do
so with a tiered approach. The following sequence of events needs to
occur for a PCI-based peripheral to start working:
1. The hardware must boot itself at power-up — in the case of the
DN3000k10:
a. The µP must boot.
b. Recognize the SmartMedia card.
c. Configure the FPGA. (Hopefully, all this occurs before RST# on the
PCI bus is deasserted.)
2. The PCI BIOS executes the PNP routines and configures the BARs on all
PCI peripherals.
3. The operating system driver initializes the card.
4. The application initiates communication with the driver and the
application executes.
The steps are dependant. Each of the steps must start and execute flawlessly
before the next step occurs. When you get a PCI card for the first
time, it is necessary to debug each step before attempting to go to the
next. We provide utilities to help with each step.
Steps 1 and 2 are best done without an operating system in place.
Windows NT-based systems take minutes to reboot after a crash (the-BLUEscreen-of-death)
and an NT driver won’t work unless the hardware is
debugged. Since crashing is a regular occurrence in a PCI hardware debug
environment, we find it easiest to do our debug and manufacturing test in
the old DOS environment. Virtually all PCI peripherals get configured with
addresses beyond the IM boundary. On a PC, C programs cannot access
memory locations beyond IM unless special programs called DOS extenders
are used. Several freeware DOS extenders are available. We use a free DOSextender
called DJGPP. More information can be found at
http://www.delorie.com/DJGPP.
A utility program called AETEST is provided with the DN3000k10. AETEST
can be run under DOS, Windows 98/ME, Windows NT/2000, or LINUX. When
used under DOS, you must boot your PC with a DOS disk. We ship one with
the DN3000k10 in case you don’t know how to make one on your own. All
features work in the native mode of AETEST, which is DOS.
DN3000k10 User’s Manual 9-1

Utilities
All source code for AETEST is provided, so you are welcome to customize
the program to your own applications.
AETEST is not a stable program. We add and subtract features when we
need to for debug and verification purposes, so don’t be concerned if the
screens that you see aren’t exactly replicated here.
In a nutshell, AETEST lets you do the following:
• Determine if PCI recognizes the DN3000k10
• Read/write/loop any memory location
• Read/write/loop configuration space
• Display all configured PCI devices
• Display memory setting from any locations
• Fill memory with various patterns
• Run various tests on the DN3000k10
– SSRAM Test
– Multiplier Test
– SDRAM Test
– Interconnect Test
– Daughter Card Test
AETEST Utility
Installation
Instructions
Installation Instructions for DOS
1. The files aetestdj.exe and cwsdpmi.exe (the DOS extender) need
to be in the same directory.
2. Run aetestdj.exe.
Installation Instructions for Windows NT
1. Install the device driver: install.exe and qldriver.sys must be
in the same directory.
2. Type “install”
3. After the driver is installed, start the driver by selecting
Control Panel–>Devices–>find “QLDriver” –>click “Start”
4. Run aetestnt.exe.
Installation Instructions for Windows 2000
1. Install the device driver: qldriver2000.inf and the driver file
(qldriver.sys) should be in the same directory.
2. Open Control Panel, click on “Add/Remove Hardware” and then go
to “Next–>.”
3. Choose Add/Troubleshoot a device (the default option) and click on
“Next–>.”
4. Wait until it finishes new hardware device searching; choose “Add a
new device,” and click on “Next–>.”
5. Choose “No, I want to select the hardware from a list,” and press
“Next–>.”
6. Choose “Other Devices” from Hardware Types list and press “Next–>”
7. Click on “Have Disk…”
9-2 The DINI Group

Utilities
8. In “Copy Manufacturer’s Files From:” window, find the directory
where qldriver.sys is located, then press “OK.”
9. You should see “dn2000k10 driver” under Models; click on
“Next–>.”
10. Press “Next–>” and then “Finish.”
11. Run aetestnt.exe.
Installation Instructions for LINUX
This has been tested on Red Hat Linux 7.2 (kernel version 2.4.x).
Note that all the text files, including the scripts, are DOS text format (with
an extra carriage return character after every new line), so you need to
convert them.
1. You must be root to start the driver and the program. “dndev_load”
and “dndev_unload” are scripts that load and unload the driver;
“dndev.o” is the driver file.
2. Load the driver; type “sh dndev_load”
3. Unload the driver; type “sh dndev_unload”
4. After driver is loaded, run the utility aetest_linux.
5. Note: You might need to run chmod on aetest_linux to make it
executable: type “chmod u+x aetest_linux.”
Installation Instructions for Solaris
The utility and driver are tested on Solaris 7.0/Sparc, with the 32-bit
kernel.
Note that all the text files, including the scripts, are DOS text format (with
an extra carriage return character after every new line), so you need to
convert them.
1. To install the driver, go to the driver directory, make sure the driver
file “dndev” is in the sparc sub-directory, and run
“sh dndev_uninstall.sh”
2. To uninstall the driver, run “sh dndev_uninstall.sh”
3. To run the test utility, run “aetest_solaris” as root after the driver
is loaded.
The driver is compiled with the gcc compiler.
aetest_solaris is compiled with “gmake.” You can download it from
the GNU website. The “make” from the Solaris installation does not work
with our makefile format.
You may need to make aetest_solaris executable; run “chmod u+x
aetest_solaris.”
DN3000k10 User’s Manual 9-3

Utilities
Installation Instructions for Windows 98/ME
There are two ways to run AETEST: You can run the DOS version
“aetestdj.exe” directly, or you can run AETEST with a device driver.
To run AETEST with a device driver follow the steps below.
1. Choose a default PCI driver for the device. When Windows first starts
with the device plugged in, it should ask for a device driver. Select
“Specify the location of the driver.”
2. Select “Display a list of the drivers in a specific location…”
3. Select “Other devices.”
4. Under “Manufacturers” tab, select “unknown device.”
5. Under “Models” select “unsupported device.”
6. The driver file (pcifg.vxd) and aetest98.exe must be in the same
directory. Run aetest98.exe.
NOTE: To re-compile the driver file pcicfg.vxd, you need the VtoolsD
compiler from www.numega.com.
AETEST
Options:
Description
and
Definitions
Startup
When AETEST is first started, it tries to find a device that it recognizes. We
have arbitrarily defined the DN3000k10 with a DEVICE_ID of 0x1250 or
0x1251 and a VENDOR_ID of 0x17DF. We have arbitrarily defined the
DN3000k10S with a DEVICE_ID of 0x1240 and a VENDOR_ID of 0xABCD
or 0x17DF. The DN2000k10 series has a DEVICE_ID of 0x1234, 0x1235,
0x1236 or 0x1237 and VENDOR_ID of 0xABCD. You should see the
following screen if AETEST recognizes a DN3000k10 (Figure 9-1):
Figure 9-1 AETEST Startup Screen, DN3000k10 Recognized
9-4 The DINI Group

Utilities
Most of this initial display is debug information. The program is looking
for a Vendor and Device ID that it recognizes, and finds vendor=abcd
and device=1240, which is a DN3000k10 stuffed with a 2V60000. The
lines after Configuration space: show what is in the configuration
space and how the BARs are configured.
If AETEST does not see a PCI peripheral it recognizes, you will see the
following (Figure 9-2):
Figure 9-2 AETEST Startup Screen, No PCI Peripheral Recognized
AETEST will still run, but many DINI product-specific options will not be
available.
DN3000k10 User’s Manual 9-5

Utilities
AETEST Main
Screen
The AETEST Main Screen is shown in Figure 9-3.
Figure 9-3 AETEST Main Screen
Options
Read FPGA Revision. Display the revision ID of the FPGA. We will
update the revision ID of the FPGA every time we change the reference
design.
PCI Menu. Display the PCI utilities menu.
Memory Menu. Display the Memory Menu.
Flash Menu. Display the Flash Utilities Menu (DN2000k10 series only!).
Clock Menu. Display the Clock Utilities Menu.
Dedicated Multiplier Test. Execute the multiplier test.
Q. Quit and return to the DOS prompt
The selections are sometimes case sensitive, so be aware of the status of
the CAPS LOCK on your keyboard. The base addresses for each of the
configured BARs is displayed on all screens. You will need these addresses
if you want to manually read and write to address locations within the PCI
reference design. In this example (Figure 9-3, above), BAR0 is configured
to 0xFD800000 and BAR1 is configured to 0xE0000000. BAR[5:2] are not
configured so they show up as 0x0.
9-6 The DINI Group

Utilities
PCI Menu The AETEST PCI menu is shown in Figure 9-4.
Figure 9-4 AETEST PCI Menu
Set PCI Device Number. Sets a PCI device number of your choice as
the “active” device (hex input). This option lists the available Device
Numbers to help you match up your Device ID and Vendor ID with the
device number.
Set PCI Function Number. Sets a PCI function number of your choice
as the “active” function of a multi-function device (hex input). This option
lists the Device ID and Vendor ID of each function within the “active”
device number to help you to choose the desired function.
Display all Configured PCI Devices. Displays the PCI Device
Numbers and corresponding Device ID and Vendor ID of all devices seen
on the bus. This does not display device numbers with a Device ID and
Vendor ID of all ones (OxFFFF).
Display Vendor and Device ID for PCI device-function.
Displays the Vendor ID and Device ID of the active device and function
number. In the example above, this would display the Vendor ID and
Device ID of the PCI device at device number 0x7F, function number 0x00.
Loop on PCI device-fun: 7f-0 and Display Vendor and Device
ID. Reads and displays the Vendor ID and Device ID of the “active” device
number and function number. Repeats this action until the user hits a key
to stop it.
DN3000k10 User’s Manual 9-7

Utilities
Loop on PCI device-fun: 7f-0 and Don’t Display Vendor and
Device ID. Same as previous menu option, except doesn’t display
results. This menu option is useful when using an oscilloscope to debug
configuration reads.
Loop on all PCI device numbers and Display Device/Vendor
ID’s. Loops on each device number, reading the Vendor ID and Device ID
for each. It moves onto the next device number when you press any key.
That is, it continually reads the Vendor ID and Device ID from device
number 0 until you hit a key, at which point it continually reads the
Vendor ID and Device ID from device number 1. It moves all the way
through device number 0 to device number 0x7F (in case there are any
bridges on your PCI bus).
Display all PCI information for PCI device-function: 7f-0.
Reads and displays all of the configuration space for the “active” device
and function number. Use options “S” and “F” to change between the
“active” device number and function number, and then use this option to
view the entire configuration space.
Write config(uration) DWORD. Allows write to configuration space.
The following text will appear to remind you what is in configuration
space for a PCI device:
PCI_CS_VENDOR_ID
PCI_CS_DEVICE_ID
PCI_CS_COMMAND
PCI_CS_STATUS
PCI_CS_REVISION_ID
PCI_CS_CLASS_CODE
PCI_CS_CACHE_LINE_SIZE
PCI_CS_MASTER_LATENCY
PCI_CS_HEADER_TYPE
PCI_CS_BIST
PCI_CS_BASE_ADDRESS_0
PCI_CS_BASE_ADDRESS_1
PCI_CS_BASE_ADDRESS_2
PCI_CS_BASE_ADDRESS_3
PCI_CS_BASE_ADDRESS_4
PCI_CS_BASE_ADDRESS_5
PCI_CS_EXPANSION_ROM
PCI_CS_INTERRUPT_LINE
PCI_CS_INTERRUPT_PIN
PCI_CS_MIN_GNT
PCI_CS_MAX_LAT
Input config offset (hex 0x00-0xff):
word to write (in hex):
Loop indefinitely (y or n)
0x00
0x02
0x04
0x06
0x08
0x09
0x0c
0x0d
0x0e
0x0f
0x10
0x14
0x18
0x1c
0x20
0x24
0x30
0x3c
0x3d
0x3e
0x3f
If looping was selected, any keypress will stop the loop.
9-8 The DINI Group

Utilities
Read config(uration) DWORD. Allows read from configuration
space. Has options for single read, loop read with display, and loop read
without display.
Configure BARs from File. Reloads the PCI configuration of the
“active” device from a file. It writes 0x001F to the command register, and
writes the 6 bars with the values from the file. This is useful for hot-swapping
devices (power switch still required on extender), or reinitializing a
device when its configuration has been altered.
WARNING: Because the PCI BIOS is not assigning the BARs for this device,
you may induce a memory conflict by using this option. This option is for
advanced users only!
Save Bar Configuration to File. Writes PCI Device ID, Vendor ID and
the BARs into a file (from the “active” device). This option is for advanced
users only!
Memory Menu
The memory menu (Figure 9-5) allows you to perform a variety of tests of
PCI memory along with some DN3000k10 specific tasks.
Figure 9-5 AETEST Memory Menu
DN3000k10 User’s Manual 9-9

Utilities
Write to Memory Test. Write a selected number of long words to a
specific PCI memory location (Figure 9-6).
Figure 9-6 AETEST Write to Memory Test
You will be prompted for the memory location (in hex). The physical
address is needed. All 4 gigabytes of PCI memory can be accessed. A
minimum of 1 to a maximum of 1024 long words can be written, in
sequential order, to the same address. A looping option is available if you
want to use an oscilloscope. If you are in a scope loop, any keypress will
terminate the loop and return you to the main menu.
Read Memory Test. Read a single long word from a specific PCI
memory location (Figure 9-7).
Figure 9-7 AETEST Read Memory Test
You will be prompted for the memory location (in hex). The physical
address is needed. All 4 gigabytes of PCI memory can be read. Three
options are available:
1. Read once and display.
2. Read indefinitely and display.
3. Read indefinitely and don’t display.
9-10 The DINI Group

Utilities
Write/Read Test. Write a long word to a specific PCI memory location
and immediately read what was written. Repeat for a selected number of
long words (Figure 9-8).
Figure 9-8 AETEST Write/Read Test
You will be prompted for the memory location (in hex). The physical
address is needed. All 4 gigabytes of PCI memory can be read. The
program will prompt for the number of long words you with to write
(1 to 1024). Three options are available:
1. Read once and display.
2. Read indefinitely and display.
3. Read indefinitely and don’t display.
Option 3 is a very useful scope loop.
Memory Fill. Fill memory with a selected pattern (Figure 9-9).
Figure 9-9 AETEST Memory Fill
You will be prompted for the memory location (in hex). The physical
address is needed. All 4 gigabytes of PCI memory can be written. The
program will prompt for the number of bytes (in hex) you wish to fill
(4 to 0xfffffffc). The following fill options are available:
1. fill with 0 — fill all the locations with 0x00000000 (clear the
memory)
2. address=data — fill each long word with its address
3. alternating 0x55555555, 0xAAAAAAAA
4. 0xffffffff — set all of memory
5. data=~address — fill each long word with the address (each
bit inverted).
DN3000k10 User’s Manual 9-11

Utilities
Memory Display. Display 160 long words of memory. You are
prompted for the starting address (in hex):
Input starting address (hex and 32 bit aligned):
The following screen is displayed (Figure 9-10):
Figure 9-10 AETEST Memory Display
(f) forward — pages the screen forward in memory.
(b) back — pages the screen backwards in memory.
(j) jump — jump to a specific location (in hex).
(0) goto — jump back to the original address location specified at
the beginning.
(d) delay and display loop — display, wait for a second, and display
again. Loop until a key is struck.
Write Memory Byte. Write a specific number of bytes to a single
memory address (Figure 9-11).
Figure 9-11 AETEST Write Memory Byte
You will be prompted for the memory location (in hex). The physical
address is needed. All 4 gigabytes of PCI memory can be accessed. A
minimum of 1 to a maximum of 1024 bytes will be written, in sequential
order, to the same address. A looping option is available if you want to use
9-12 The DINI Group

Utilities
an oscilloscope. If you are in a scope loop, any keypress will terminate the
loop and return you to the main menu.
Read Memory Byte. Read a single byte from a specific PCI memory
location (Figure 9-12).
Figure 9-12 AETEST Read Memory Byte
You will be prompted for the memory location (in hex). The physical
address is needed. All 4 gigabytes of PCI memory can be read. Three
options are available:
1. Read once and display.
2. Read indefinitely and display.
3. Read indefinitely and don’t display.
Write/Read Memory Byte. Write and read a single DWORD from a
specific PCI memory location. After entering a memory address (hex, 32
bits), you specify how many DWORDS you want written and read back, and
the data. Then, you choose from the 3 options as above. The menu option
does not perform any data checking. (Figure 9-13)
Figure 9-13 AETEST Write/Read Memory Byte
Memory test on SSRAM1. Tests one of the SSRAM chips on the
DN3000k10.
Memory test on SSRAM2. Tests one of the SSRAM chips on the
DN3000k10.
Memory test on SSRAM3. Tests one of the SSRAM chips on the
DN3000k10.
Memory test on SDRAM. Tests the SDRAM chip on the DN3000k10.
Full Memory Test (Including BlockRAM). Tests all of the memories.
This includes the SSRAM chips, the SDRAM, and the BlockRAM internal
to the FPGA.
DN3000k10 User’s Manual 9-13

Utilities
Memory test on FPGA block memory. Tests the BlockRAM inside
the FPGA. On the DN2000k10, the BlockRAM is only in FPGA F.
BAR memory range test. Generic memory test that prompts the user
for BAR number, starting address offset, DWORD count, and number of
iterations. The user is also prompted if the program should stop if error
occurs, or if the program should display any errors that occur. This allows
for maximum flexibility when debugging a design with an oscilloscope, or
debugging any memories or memory locations on your PCI bus. The
memory test is very complete, performing a write then a read to every
location, a read from every location, and then a read/write/read test to
every location. All other memory test options listed in the memory menu
are based on this generic memory test function.
9-14 The DINI Group

Appendix A
Berg Connector Datasheets
Figure A-1 and Figure A-2 contain the schematics for the Berg 91403-003
Connector.
Figure A-3 through Figure A-5 contain the schematics for the Berg
91294-003 connector.
DN3000k10 User’s Manual A-1

Berg Connector Datasheets
Figure A-1 Berg 91403-003 Datasheet Page 1 of 2
A-2 The DINI Group

Berg Connector Datasheets
Figure A-2 Berg 91403-003 Datasheet Page 2 of 2
DN3000k10 User’s Manual A-3

Berg Connector Datasheets
Figure A-3 Berg 91294-003 Datasheet Page 1 of 3
A-4 The DINI Group

Berg Connector Datasheets
Figure A-4 Berg 91294-003 Datasheet Page 2 of 3
DN3000k10 User’s Manual A-5

Berg Connector Datasheets
Figure A-5 Berg 91294-003 Datasheet Page 3 of 3
A-6 The DINI Group

Glossary and Acronyms
Glossary and Acronyms
µP microprocessor
A/D analog to digital
AREF Analog Voltage Reference
ASIC application specific integrated
circuits
AVCC Analog Vcc
BAR Base Address Register
BGA ball grid array
BIOS Basic Input/Output Services
CLB configurable logic block
CMOS complementary metal-oxide
semiconductor
CPLD Complex Programmable Logic
Device
DCI digitally controlled impedance
DCM Digital Clock Manager
DES data encryption standard
DIMM dual in line memory module
EEPROM Electrically Erasable PROM
EIA Electronic Industries
Association
FAQ frequently asked questions
FAT file allocation table
FIFO first in first out
FPGA field programmable gate array
FT flowthrough
GND ground
HDL Hardware Description
Language
I/O input/output
IDC integrated desktop connector
IP intellectual property
LED light emitting diode
LSI large scale integration
LUT
LVCMOS
LVDS
LVTTL
MDR
NIST
PCI
PCI-X
PGP
PL
PLL
PNP
PWB
RAM
RISC
RSA
RTL
SDRAM
SRAM
SSRAM
TDEA
TDM
TTL
lookup table
low voltage complementary
metal-oxide semiconductor
Low-Voltage Differential
Signaling
low voltage
transistor-transistor logic
Mini D Ribbon
National Institute of Standards
and Technology
peripheral component
interconnect
peripheral component
interconnect (extended)
Pretty Good Privacy
pipelined
phase lock loop
plug-and-play
printed wire board
random access memory
reduced instruction set
computer
A public-key cryptosystem
developed by MIT professors
Ronald L. Rivest, Adi Shamir,
and Leonard M. Adleman
resistor transistor logic
synchronous dynamic random
access memory
shadow random access
memory
synchronous static random
access memory
riple data encryption algorithm
time division multiplexing
transistor-transistor logic
DN3000k10 User’s Manual G–1

UCF
VHDL
VREF
ZBT
user configuration file
VHSIC Hardware Description Language
reference voltage
zero-bus-turnaround
2 Xilinx Intellectual Property Solutions

Index
Index
Symbols
[C-F]DS 4-10, 4-12
µP 2-9, 2-11 to 2-13, 2-16, 2-18, 2-28, 8-1, 9-1
See also microprocessor
A
ACLK 4-1
ADSC# 5-9, 5-11
ADSP# 5-9, 5-11
ADV# 5-11
AETEST 9-1 to 9-7, 9-9 to 9-10, 9-13
ALE 2-16
ASIC 2-1 to 2-2, 2-29 to 2-30, 4-1, 4-16, 5-1, 7-1, 7-6 to
7-7
ATMega128L 2-12
ATmega128L 2-1, 2-9 to 2-14, 2-16, 2-18
Atmega128L 2-9
B
Battery 2-9
battery 2-1, 2-7 to 2-9
BCLK 4-1
BCLKOUT 4-17
BCPUCLK 2-18
Berg 8-5
Berg connector 8-5, A-1
BIOS 9-1, 9-9
bitgen options 2-21, 2-23, 2-27
bitstream encryption 2-1, 2-7
BlockRAM 2-26 to 2-27, 7-1, 9-13 to 9-14
Blockram 7-1
board termination voltage 2-6 to 2-7
Bridges2silicon 2-19
BUFINA 4-3 to 4-4, 4-6
BUFINB 4-3 to 4-4, 4-7
bus bars 8-5
BWE# 5-11
BWx# 5-11
C
C_CCLK 2-16, 2-19
C_DIN 2-16, 2-19
C_DONE 2-16, 2-19
C_INIT– 2-16, 2-19
C_PROG– 2-16, 2-19
carry 2-3
carry chains 2-3
CCLK 2-19 to 2-21, 4-10, 4-13 to 4-14, 4-17
CE# 5-11
CE2# 5-11
Certify TDM 2-1
ChipScope ILA Logic Analyzer 2-19
cipher block chaining 2-7
CLB 2-3
CLKIN 4-16
CLKOUT 4-1, 4-3 to 4-4
clock 2-1, 2-5, 2-16, 2-18, 2-20, 2-30 to 3-1, 4-1, 4-3 to
4-6, 4-10 to 4-12, 4-14 to 4-16, 4-18, 5-9 to
5-10, 5-14, 7-6, 8-7, 9-6
clock buffer 4-1
clock buffers 4-1, 4-7, 4-13, 6-2
clock distribution 4-4
clock divider function 4-11
clock division 4-11
clock edge 2-5
clock enable 2-5
clock frequency 4-1
clock frequency multipliers 4-11
clock grid 4-1, 4-3, 4-6, 4-13
clock input 4-6, 4-11, 4-13
clock inputs 4-14, 4-16, 4-18, 8-7
clock menu 9-6
clock multiplication 4-11
clock multiplication mechanism 4-11
clock outputs 4-1, 4-10 to 4-11, 4-16 to 4-17
clock signal 2-18, 4-4
clock signals 4-13 to 4-14, 4-16 to 4-17, 7-6
clock skew 4-1, 4-11 to 4-13
CLOCKA 4-3 to 4-4
CLOCKB 4-3 to 4-4, 4-7
configuration 2-1, 2-3, 2-7, 2-9, 2-16, 2-18 to 2-21,
2-23 to 2-26, 2-28, 3-4 to 3-5, 4-1, 4-4, 4-16,
5-13, 6-3, 8-1, 9-2, 9-5, 9-8 to 9-9
µP 2-9
µP and FPGA 2-9
bitstream 2-7
clock grid 4-4
FPGA 2-1, 2-9, 2-16, 2-18, 3-4, 8-1
JTAG 2-18 to 2-20
serial 2-18 to 2-19
SmartMedia 2-23 to 2-24, 2-28
stand-alone 6-3
via SelectMap 2-18, 2-20 to 2-21, 2-25 to 2-26
DN3000k10 User’s Manual I–1

Index
Index (Continued)
via SmartMedia 2-3
configuration bit files 2-3
configuration space 9-2, 9-5, 9-8 to 9-9
CPLD 2-1, 2-3, 2-14, 2-16, 2-18, 2-28, 4-1, 4-3 to 4-4,
6-2, 8-1, 8-4
CPLD_TCK 2-17
CPLD_TDI 2-17
CPLD_TDO 2-17
CPLD_TMS 2-17
CPUCLK 2-16, 2-18
CSF– 2-16
custom daughter cards 2-2
CY7B993V 4-11 to 4-12, 4-14
D
D 2-16
Data Encryption Standard
See DES
daughter card 2-2, 2-21, 4-17, 6-5, 7-1 to 7-4, 7-7 to
7-8, 8-5, 8-7, 9-2
daughter connections 2-2
DCI 2-6
DCLK 4-13, 4-16 to 4-18
DCM 4-16 to 4-17, 5-14
debug 2-2 to 2-3, 2-12, 8-4, 9-1, 9-8, 9-14
analyzer-based 2-2, 9-1 to 9-2, 9-5, 9-8, 9-14
decryption 2-7 to 2-8
DES 2-1, 2-7 to 2-8
design 1-2 to 1-3, 2-2, 2-7, 2-20, 2-25, 9-6, 9-14
logic 2-7
Design Manager 2-20
Device ID 2-23, 9-5, 9-7 to 9-9
differential LVDS pairs 7-1
Digital Clock Managers
See DCM
Digitally Controlled Impedance
See DCI
DIMM 2-3, 5-1, 5-11, 6-2
DIND0F 2-16
divider function 4-10 to 4-12
DLL 7-1
DN3000k10 1-1, 2-1 to 2-3, 2-6 to 2-7, 2-9 to 2-12,
2-14 to 2-16, 2-20 to 2-21, 2-24 to 2-25, 2-27
to 2-28, 2-30 to 3-1, 3-4, 4-1, 4-3 to 4-4, 4-6 to
4-7, 4-14, 5-1, 5-9, 5-11, 6-1 to 6-5, 7-1, 7-6 to
7-7, 8-1, 8-3, 8-5, 8-7, 9-1 to 9-2, 9-4 to 9-5,
9-9, 9-13
block diagram 2-2
description 2-2
features 2-1 to 2-2
Fequently Asked Questions 1-1
Technical Support 1-1
Dn3000k10 3-1
DN3000k10SD 7-1, 7-6 to 7-8
DN3k10SD 2-2, 7-4
DNPCIEXT-S3 3-1
DONEF 2-16
DOS 9-1 to 9-2, 9-4, 9-6
DOS extenders 9-1 to 9-2
DOUTBSYF 2-16
drive 6-3
drive power connector 6-3
dual 2-5
dual-port 2-5
diagram 2-5
E
ECLK 4-10, 4-13 to 4-14, 4-16 to 4-17, 5-1, 5-11
EEPROM 2-12, 5-13 to 5-14
embedded memory 2-1, 2-5, 2-30
encryption 2-1, 2-7 to 2-8
ESD 1-1
extender card 3-1
external memories 2-2, 5-1
F
FBDIS 4-10 to 4-11
FBDS 4-10 to 4-11
FBF0 4-10, 4-13
FCLKOUT 4-16 to 4-18
feedback disable 4-10
feedback output divider function 4-10
feedback output phase function 4-10
FIFO 2-5
FLASH 2-1, 2-3, 2-9, 2-12, 2-15, 9-6
FlashPath 2-25, 2-28 to 2-29
FPGA 1-2, 2-1, 2-3, 2-8 to 2-9, 2-15 to 2-16, 2-18 to
2-21, 2-23 to 3-1, 3-4 to 3-5, 4-16 to 4-17,
5-11, 6-2 to 6-3, 7-8, 8-1, 8-4, 8-6 to 8-7, 9-1,
9-6, 9-13 to 9-14
configuratin 9-1
configuration 2-1, 2-3, 2-9, 2-15 to 2-16, 2-18 to
I–2 The DINI Group

Index
Index (Continued)
2-21, 2-23 to 2-29, 8-4
fpga 2-20, 2-23
FPGA A 2-3, 2-24, 4-17
FPGA B 2-3, 2-24, 4-17
FPGA C 2-3
FPGA D 2-3, 2-24
FPGA E 2-3, 2-24
FPGA F 2-3, 2-15, 2-24 to 2-25, 3-4, 4-16 to 4-17
FPGA_C 2-3
frequency select 4-10
FS 4-10 to 4-12, 4-14
FTCK 2-16, 2-20
FTDI 2-16, 2-20
FTDO 2-16, 2-20
FTMS 2-16, 2-20
FWRTSM– 2-16
G
GCLK 4-17
GW# 5-11
H
HyperTerminal 2-15, 2-21
I
impedance 2-6
INITF– 2-16
input clock select 4-10
interconnect 2-1, 5-2, 7-8, 8-7, 9-2
INV1 4-14
INV2 4-10, 4-14
IOATTRIBUTE 2-6
J
JTAG 2-2, 2-8 to 2-9, 2-11 to 2-14, 2-16 to 2-20, 2-25,
3-4
clock 2-20
configuration 2-18
interface 2-13
JTAG clock 2-20
jumper definitions 4-9 to 4-10
jumper settings 2-25, 4-15
L
LD# 5-11
LED 2-2 to 2-3, 2-16, 2-19, 2-25, 7-4, 8-3 to 8-4
LOCK_N 2-16, 2-19, 8-4
logic analyzer 2-2, 2-19
LTC1326 8-1
LUT 2-3, 2-5
LVCMOS33 2-6
LVDS 2-7, 7-1, 7-6, 8-7
LVPECL 4-1, 4-13
M
M 2-16
M66EN 3-5, 3-7
main configuration file 2-23
main.txt 2-20, 2-23 to 2-26, 8-1
MBCK 4-17, 8-7
MDR 7-6
memories 2-2, 2-5, 2-30, 5-1, 5-14, 8-6 to 8-7, 9-13 to
9-14
microprocessor 2-1, 2-3, 2-9, 6-2
See also µP
MODE 4-10
mounting holes 8-5
multiplexers 2-3
multiplexing 2-1, 2-11, 5-11
multiplication 2-6, 4-11
multiplier 2-6
multiplier blocks 2-6
O
oscillator 2-1, 2-18, 4-1, 4-3 to 4-4, 4-7, 4-11, 4-14 to
4-15, 6-2
oscillators 2-1, 4-1
oscilloscope 7-1, 8-4 to 8-5, 9-8, 9-10, 9-13 to 9-14
output divider function 4-10, 4-12
output mode 4-10
output phase function 4-10
output-enable 7-7
DN3000k10 User’s Manual I–3

Index
Index (Continued)
P
pattern 2-2, 8-5
pattern generator 2-2, 8-5
PCI 1-1 to 1-2, 2-1 to 2-2, 2-6, 3-1 to 3-2, 3-4 to 3-7,
4-16, 6-1 to 6-3, 6-5, 8-5, 8-7, 9-1 to 9-2, 9-4 to
9-14
BIOS 9-1, 9-9
bracket 8-5
bus 3-1, 9-1, 9-8, 9-14
capabilities header 3-6
clock 2-1
configuration 9-9
connector 3-1, 4-16, 6-1, 6-5
debug 9-1
driver 9-4
JTAG Signals 3-4
memory 9-10 to 9-13
reference design 9-6
Signals 3-2
signals 3-1
slot 3-1, 3-4, 6-1, 6-3, 8-7
specification 3-1, 3-4 to 3-5
specifications 3-1
target design 2-2
PCI Clock 2-1
PCI Menu 9-7
PCI_CLK 4-16
PCI-X 1-2 to 1-3, 2-1 to 2-2, 2-6, 3-1, 3-3 to 3-7
capabilities header 3-6
edge connector 3-3
present header 3-5
PCIXCAP 3-6 to 3-7
PCLK
See PCI_CLK
PECL 4-6, 4-13
PLL 2-1, 2-19, 4-1, 4-7, 4-11, 8-4
pll 8-4
PLL1A 4-3 to 4-4, 4-10
PLL1B_N 4-10
PLL1B_PRE 4-3
PLL1BN_PRE 4-3 to 4-4
PLL2B 4-13 to 4-14
PLL2B_N 4-10
PLL2B_PRE 4-3
PLL2BN 4-13 to 4-14
PLL2BN_PRE 4-3 to 4-4
PLLSEL2 4-10
polarity 4-15
power 2-14, 2-25 to 2-26, 3-1, 3-4, 3-6, 6-1 to 6-3, 6-5,
7-4, 8-5 to 8-7, 9-9
power connector 2-1, 6-3, 8-7
power distribution 3-1, 6-1
Power Down Status Pin 2-20, 2-28
power header 6-3, 6-5
power management 1-2, 3-5
Power Management Enable
See PME–
power rails 6-1 to 6-5, 8-5 to 8-6
power supply 2-28, 5-13, 6-2 to 6-5, 7-4 to 7-5, 8-1,
8-7
power switch 9-9
power-up 8-1, 9-1
PROG– 2-16
prototyping boards 7-1, 7-6 to 7-7
PWB 1-1, 2-1 to 2-3, 2-6, 2-16, 2-18, 2-28, 3-1, 8-5
R
R/W# 5-11
RB[C-F]F 4-10, 4-13
RD– 2-16
RDYBUSY– 2-16
reference design 2-20, 2-25, 9-6
regulator 2-1, 3-1, 6-2
reset 2-26
reset button 2-26
Roboclock 2-1, 2-19, 4-1, 4-3 to 4-4, 4-6 to 4-9, 4-12
to 4-14, 4-16 to 4-18, 5-11, 6-2, 8-4
RoboclockII 4-1, 6-2, 8-4
RST# 3-4, 9-1
S
SDRAM 2-3, 2-26 to 2-27, 4-16, 5-1, 5-11 to 5-14, 6-2,
6-5, 9-2, 9-13
security 2-7 to 2-8
SelectI/O 7-1
SelectRAM 2-5 to 2-6
serial 2-14
serial port 2-14 to 2-15, 2-21 to 2-23, 2-25
Signals
[C-F]DS 4-10, 4-12
ACLK 4-1
ADSC# 5-9, 5-11
ADSP# 5-9, 5-11
I–4 The DINI Group

Index
Index (Continued)
ADV# 5-11
ALE 2-16
ATmega128L
ALE 2-16
BCPUCLK 2-18
CPUCLK 2-16, 2-18
RD– 2-16
SRAMCS– 1-4, 2-16
UPAD 2-16
UPADC 2-11
UPADDR 2-16
WR– 2-16
BCLK 4-1
BCLKOUT 4-17
BCPUCLK 2-18
BUFINA 4-3 to 4-4, 4-6
BUFINB 4-3 to 4-4, 4-7
BWE# 5-11
BWx# 5-11
C_CCLK 2-16, 2-19
C_DIN 2-16, 2-19
C_DONE 2-16, 2-19
C_INIT– 2-16, 2-19
C_PROG– 2-16, 2-19
CCLK 2-19 to 2-21, 4-10, 4-13 to 4-14, 4-17
CE# 5-11
CE2# 5-11
CLKIN 4-16
CLKOUT 4-1, 4-3 to 4-4
Clock
[C-F]DS 4-10, 4-12
ACLK 4-1
BCLK 4-1
BCLKOUT 4-17
BUFINA 4-3 to 4-4, 4-6
BUFINB 4-3 to 4-4, 4-7
CCLK 2-19 to 2-21, 4-10, 4-13 to 4-14, 4-17
CLKIN 4-16
CLKOUT 4-1, 4-3 to 4-4
CLOCKA 4-3 to 4-4
CLOCKB 4-3 to 4-4, 4-7
DCLK 4-13, 4-16 to 4-18
ECLK 4-10, 4-13 to 4-14, 4-16 to 4-17, 5-1,
5-11
FBDIS 4-10 to 4-11
FBDS 4-10 to 4-11
FBF0 4-10, 4-13
FCLKOUT 4-16 to 4-18
FS 4-10 to 4-12, 4-14
GCLK 4-17
INV1 4-14
INV2 4-10, 4-14
MODE 4-10
PCI_CLK 4-16
PLL1A 4-3 to 4-4, 4-10
PLL1B_N 4-10
PLL1B_PRE 4-3
PLL1BN_PRE 4-3 to 4-4
PLL2B 4-13 to 4-14
PLL2B_N 4-10
PLL2B_PRE 4-3
PLL2BN 4-13 to 4-14
PLL2BN_PRE 4-3 to 4-4
PLLSEL2 4-10
RB[C-F]F 4-10, 4-13
CLOCKA 4-3 to 4-4
CLOCKB 4-3 to 4-4, 4-7
CPLD
LED 2-16
CPLD_TCK 2-17
CPLD_TDI 2-17
CPLD_TDO 2-17
CPLD_TMS 2-17
CPUCLK 2-16, 2-18
CSF– 2-16
D 2-16
DCLK 4-13, 4-16 to 4-18
DIND0F 2-16
DONEF 2-16
DOUTBSYF 2-16
ECLK 4-10, 4-13 to 4-14, 4-16 to 4-17, 5-1, 5-11
FBDIS 4-10 to 4-11
FBDS 4-10 to 4-11
FBF0 4-10, 4-13
FCLKOUT 4-16 to 4-18
FGPA JTAG
FTDO 2-16
FPGA
C_CCLK 2-16, 2-19
C_DIN 2-16, 2-19
C_DONE 2-16, 2-19
C_INIT– 2-16, 2-19
C_PROG– 2-16, 2-19
CSF– 2-16
D 2-16
DIND0F 2-16
DONEF 2-16
DOUTBSYF 2-16
FWRTSM– 2-16
INITF– 2-16
M 2-16
PROG– 2-16
DN3000k10 User’s Manual I–5

Index
Index (Continued)
FPGA JTAG
FTCK 2-16, 2-20
FTDI 2-16, 2-20
FTDO 2-20
FTMS 2-16, 2-20
FS 4-10 to 4-12, 4-14
FTCK 2-16, 2-20
FTDI 2-16, 2-20
FTDO 2-16, 2-20
FTMS 2-16, 2-20
FWRTSM– 2-16
GCLK 4-17
GW# 5-11
INITF– 2-16
INV1 4-14
INV2 4-10, 4-14
LD# 5-11
LED 2-16
LOCK_N 2-16, 2-19, 8-4
M 2-16
MODE 4-10
PCI
ADSC# 5-9, 5-11
ADSP# 5-9, 5-11
ADV# 5-11
BWE# 5-11
BWx# 5-11
CE# 5-11
CE2# 5-11
GW# 5-11
LD# 5-11
LOCK_N 2-16, 2-19, 8-4
R/W# 5-11
RST# 3-4, 9-1
PCI JTAG
CPLD_TCK 2-17
CPLD_TDI 2-17
CPLD_TDO 2-17
CPLD_TMS 2-17
TCK 2-12, 2-17, 2-20, 3-4
TDI 2-12, 2-17, 2-20, 3-4
TDO 2-12, 2-17, 2-20, 3-4
TMS 2-12, 2-17, 2-20, 3-4
TRST# 3-4
PCI_CLK 4-16
PLL1A 4-3 to 4-4, 4-10
PLL1B_N 4-10
PLL1B_PRE 4-3
PLL1BN_PRE 4-3 to 4-4
PLL2B 4-13 to 4-14
PLL2B_N 4-10
PLL2B_PRE 4-3
PLL2BN 4-13 to 4-14
PLL2BN_PRE 4-3 to 4-4
PLLSEL2 4-10
PROG– 2-16
R/W# 5-11
RB[C-F]F 4-10, 4-13
RD– 2-16
RDYBUSY– 2-16
RST# 3-4, 9-1
SMALE 2-16
SmartMedia card
RDYBUSY– 2-16
SMALE 2-16
SMCE– 2-16
SMCLE 2-16
SMRE– 2-16
SMRTMED 2-16
SMWE– 2-16
SMWP– 2-16
SMCE– 2-16
SMCLE 2-16
SMRE– 2-16
SMRTMED 2-16
SMWE– 2-16
SMWP– 2-16
SRAMCS– 1-4, 2-16
TCK 2-12, 2-17, 2-20, 3-4
TDI 2-12, 2-17, 2-20, 3-4
TDO 2-12, 2-17, 2-20, 3-4
TMS 2-12, 2-17, 2-20, 3-4
TRST# 3-4
UPAD 2-16
UPADC 2-11
UPADDR 2-16
WR– 2-16
slice 2-3 to 2-4, 2-6
SMALE 2-16
SmartMedia 2-9, 8-1, 8-3, 9-1
SmartMedia card 2-9, 2-15 to 2-16, 2-18 to 2-19,
2-25 to 2-26, 2-28 to 2-29, 8-1, 9-1
SMCE– 2-16
SMCLE 2-16
SMRE– 2-16
SMRTMED 2-16
SMWE– 2-16
SMWP– 2-16
speed 2-3, 3-1
speed grade 2-3, 2-30 to 3-1
I–6 The DINI Group

Index
Index (Continued)
SRAM 2-9, 2-16, 5-1, 6-2
SRAMCS– 1-4, 2-16
SSRAM 2-26 to 2-27, 4-16, 5-1, 5-3 to 5-11, 8-7, 9-2,
9-13
Startup 2-20
Startup Clock 2-20 to 2-21
static 1-1
static electricity 1-1
Synopsys 2-29
Synplicity 2-1, 2-29
synthesis 1-2, 2-5, 2-29 to 2-30
synthesis tools 2-5 to 2-6, 2-29 to 2-30
T
target design 2-2
TCK 2-12, 2-17, 2-20, 3-4
TDI 2-12, 2-17, 2-20, 3-4
TDO 2-12, 2-17, 2-20, 3-4
technical support 1-1
The DINI Group 1-1
TMS 2-12, 2-17, 2-20, 3-4
TRST# 3-4
U
UCF 2-6, 3-1
UPAD 2-16
UPADC 2-11
UPADDR 2-16
V
Vendor 9-7
Vendor ID 9-7 to 9-9
verbose level 2-23 to 2-26
Verilog 1-2, 2-2, 2-6, 2-16
VHDL 1-2, 2-6
VirtexII 1-2, 2-1, 2-3, 2-5 to 2-7, 2-9, 2-18, 2-20, 2-28,
3-1, 3-4, 4-16 to 4-17, 6-2 to 6-3
architecture 2-3 to 2-5
DCM 4-16 to 4-17
DES 2-7
overview 2-3
voltage 2-6 to 2-7, 2-11 to 2-12, 2-21, 3-4, 4-11, 4-13,
6-2, 7-5 to 7-6
W
WR– 2-16
X
XC2V3000 2-28
XC2V4000 2-1, 2-5, 2-28
XC2V6000 2-1 to 2-3, 2-5, 2-28
XC2V8000 2-1, 2-28
XC95288XL 2-16
DN3000k10 User’s Manual I–7

Index
Index (Continued)
I–8 The DINI Group