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Tutorial on Mixed mode simulation and simulation of spice netlists in ...

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Figure 1: W<strong>in</strong>dow Comparator<br />

2 The digital secti<strong>on</strong><br />

In the library mixedtutorial, create a new cell-view ”<strong>and</strong>gate” with ”functi<strong>on</strong>al”<br />

as the View name <strong>and</strong> ”Verilog-editor” as the tool (see Fig. 2). When you click<br />

<strong>on</strong> OK, a text editor should open up. Write code for the AND gate as shown <strong>in</strong><br />

Fig. 3. Hit ESC <strong>and</strong> :wq to save <strong>and</strong> quit the editor. You may ignore warn<strong>in</strong>gs<br />

for now. When asked if you want to create a symbol view, hit yes. And voila !<br />

You’re d<strong>on</strong>e with the digital secti<strong>on</strong>.<br />

Figure 2: Creat<strong>in</strong>g a verilog cell-view<br />

2

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