MAX 9000 Programmable Logic Device Family Data Sheet

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MAX 9000 Programmable Logic Device Family Data Sheet The instruction register length for MAX 9000 devices is 10 bits. EPM9320A and EPM9560A devices support a 16-bit UESCODE register. Tables 11 and 12 show the boundary-scan register length and device IDCODE information for MAX 9000 devices. Table 11. MAX 9000 Boundary-Scan Register Length Device Boundary-Scan Register Length EPM9320, EPM9320A 504 EPM9400 552 EPM9480 600 EPM9560, EPM9560A 648 Table 12. 32-Bit MAX 9000 Device IDCODE Note (1) Device IDCODE (32 Bits) Version (4 Bits) Part Number (16 Bits) (2) Manufacturer’s Identity (11 Bits) Notes: (1) The IDCODE’s least significant bit (LSB) is always 1. (2) The most significant bit (MSB) is on the left. (3) Although the EPM9320A and EPM9560A devices support the IDCODE instruction, the EPM9320 and EPM9560 devices do not. Figure 11 shows the timing requirements for the JTAG signals. 1 (1 Bit) EPM9320A (3) 0000 1001 0011 0010 0000 00001101110 1 EPM9400 0000 1001 0100 0000 0000 00001101110 1 EPM9480 0000 1001 0100 1000 0000 00001101110 1 EPM9560A (3) 0000 1001 0101 0110 0000 00001101110 1 24 Altera Corporation
f Figure 11. MAX 9000 JTAG Waveforms TMS TDI TCK TDO Signal to Be Captured Signal to Be Driven t JCH MAX 9000 Programmable Logic Device Family Data Sheet t JPZX t JSZX t JCP t JSSU Table 13 shows the JTAG timing parameters and values for MAX 9000 devices. Table 13. JTAG Timing Parameters & Values for MAX 9000 Devices Symbol Parameter Min Max Unit tJCP TCK clock period 100 ns tJCH TCK clock high time 50 ns tJCL TCK clock low time 50 ns tJPSU JTAG port setup time 20 ns tJPH JTAG port hold time 45 ns tJPCO JTAG port clock to output 25 ns tJPZX JTAG port high impedance to valid output 25 ns tJPXZ JTAG port valid output to high impedance 25 ns tJSSU Capture register setup time 20 ns tJSH Capture register hold time 45 ns tJSCO Update register clock to output 25 ns tJSZX Update register high impedance to valid output 25 ns tJSXZ Update register valid output to high impedance 25 ns For detailed information on JTAG operation in MAX 9000 devices, refer to Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Altera Corporation 25 t JCL t JSH t JPCO t JSCO t JPSU t JPH tJSXZ t JPXZ
Page 1 and 2: ® MAX 9000 Programmable Logic Devi
Page 3 and 4: General Description Table 4. MAX 90
Page 5 and 6: Functional Description f MAX 9000 P
Page 7 and 8: Figure 2. MAX 9000 Logic Array Bloc
Page 9 and 10: MAX 9000 Programmable Logic Device
Page 11 and 12: Parallel Expanders Figure 5. MAX 90
Page 17 and 18: Figure 10. MAX 9000 IOC To Row or C
Page 19 and 20: In-System Programmability (ISP) MAX
Page 23: Programming with External Hardware
Page 27 and 28: Operating Conditions MAX 9000 Progr
Page 29 and 30: Table 20. MAX 9000A Device Typical
Page 31 and 32: Figure 14. MAX 9000 Timing Model t
Page 33 and 34: Table 22. MAX 9000 Internal Timing
Page 35 and 36: Table 24. Interconnect Delays MAX 9
Page 37 and 38: Figure 15. I CC vs. Frequency for M
Page 39 and 40: GND 6, 18, 24, 25, 48, 61, 67, 70 1
Page 43 and 44: No Connect (N.C.) MAX 9000 Programm

MAX 9000 Programmable Logic Device Family Data Sheet

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