MAX 9000 Programmable Logic Device Family Data Sheet

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MAX 9000 Programmable Logic Device Family Data Sheet Figure 1. MAX 9000 Device Block Diagram IOC IOC Logic Array Block (LAB) IOC IOC Macrocell I/O Cell (IOC) LAB Local Array IOC IOC Logic Array Blocks The MAX 9000 architecture is based on linking high-performance, flexible logic array modules called logic array blocks (LABs). LABs consist of 16-macrocell arrays that are fed by the LAB local array, as shown in Figure 2 on page 7. Multiple LABs are linked together via the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. The I/O pins are supported by I/O cells (IOCs) located at the end of each row (horizontal) and column (vertical) path of the FastTrack Interconnect. Each LAB is fed by 33 inputs from the row interconnect and 16 feedback signals from the macrocells within the LAB. All of these signals are available within the LAB in their true and inverted form. In addition, 16 shared expander product terms (“expanders”) are available in their inverted form, for a total of 114 signals that feed each product term in the LAB. Each LAB is also fed by two low-skew global clocks and one global clear that can be used for register control signals in all 16 macrocells. 6 Altera Corporation IOC IOC IOC IOC IOC IOC FastTrack Interconnect IOC IOC IOC IOC
Figure 2. MAX 9000 Logic Array Block Row FastTrack Interconnect DIN1 DIN2 DIN3 DIN4 LAB Local Array (114 Channels) Shared Expander Signals MAX 9000 Programmable Logic Device Family Data Sheet LABs drive the row and column interconnect directly. Each macrocell can drive out of the LAB onto one or both routing resources. Once on the row or column interconnect, signals can traverse to other LABs or to the IOCs. 33 Global Control Select Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 16 16 Column FastTrack Interconnect Altera Corporation 7 GCLK1 GCLK2 GCLR GOE 16 16 16 16 48 48 Local Feedback To Peripheral Bus and Other LABs in the Device To Peripheral Bus See Figure 7 for details.
Page 1 and 2: ® MAX 9000 Programmable Logic Devi
Page 3 and 4: General Description Table 4. MAX 90
Page 5: Functional Description f MAX 9000 P
Page 9 and 10: MAX 9000 Programmable Logic Device
Page 11 and 12: Parallel Expanders Figure 5. MAX 90
Page 17 and 18: Figure 10. MAX 9000 IOC To Row or C
Page 19 and 20: In-System Programmability (ISP) MAX
Page 23 and 24: Programming with External Hardware
Page 25 and 26: f Figure 11. MAX 9000 JTAG Waveform
Page 27 and 28: Operating Conditions MAX 9000 Progr
Page 29 and 30: Table 20. MAX 9000A Device Typical
Page 31 and 32: Figure 14. MAX 9000 Timing Model t
Page 33 and 34: Table 22. MAX 9000 Internal Timing
Page 35 and 36: Table 24. Interconnect Delays MAX 9
Page 37 and 38: Figure 15. I CC vs. Frequency for M
Page 39 and 40: GND 6, 18, 24, 25, 48, 61, 67, 70 1
Page 43 and 44: No Connect (N.C.) MAX 9000 Programm

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