2.5D interposers look increasingly like the near term ... - I-Micronews

M A Y 2 0 1 2 I S S U E N ° 2 3
2.5 D silicon interposer,
cross section
(Courtesy of ASE Group)
6
INDUSTRY REVIEW
13x13 mm silicon interposer,
top view (Courtesy of ASE Group)
2.5D interposers look increasingly
like the near term, high performance
solution
Lower costs and faster time to market are helping drive some early adoption of 2.5D
interposers at advanced nodes, where splitting up big die into several smaller ones
improves yields, and the ecosystem is ready to handle the technology with only
evolutionary change.
It’s by no means a defi nitive consensus, but there
seems to be a developing view that interposers
will provide both system cost and performance
advantages near term for some applications, that
both foundry and OSAT models for backside fi nish
and assembly of interposers seem workable, and
that the interposers will remain a useful solution
for some applications even after the maturity of
full 3D. But plenty of issues remain to be worked
out - from user needs and pathfi nding tools to
manufacturing technology and the ecosystem of
partnerships and vendor relationships-to enable
this major change in the traditional semiconductor
manufacturing business.
Compelling benefi ts drive adoption
at the leading edge, create ongoing
market for interposers
One initial reason companies aggressively pursuing
the bleeding edge of high-end 28nm and 20nm
platforms see the most immediate benefi t in
interposers, is that they can break up one large
die with very low yields into several smaller die
with signifi cantly higher yields connected on an
interposer, suggests Ron Huemoeller, Amkor SVP
Advanced 3D Interconnect Platform Development.
That approach can reportedly improve yields from
levels in the teens for large die at the most advanced
CMOS process nodes, to up to 30%-40% for the
multiple smaller die, for signifi cant savings in both
cost and time to market, as well as providing some
power management options. But even as yields at
these advanced nodes improve, interposers also
provide the additional benefi t of allowing designers
to strip out technologies with wider geometries like
cache memory or analog logic that take up space
and add mask count. “This is what really turned
our heads”, says Huemoeller, noting the potential
to eliminate two to four mask levels for signifi cant
savings in cost and improvement in yields. He sees
main demand coming from large package body,
side-by-side stacking for network, GPU and CPU
applications, on large silicon interposers.
3 D P a c k a g i n g

Altera CoWoS wafer developed with TSMC,
and an image of the Altera 2.5D device using
the process (Courtesy of Altera)
Perhaps it’s signifi cant that the big industry
leading IDMs Intel, IBM and Samsung, who
were talking about this technology openly a
while ago, now have little to say, though they
clearly have a lot of inside activity going on. “It’s
a good sign that everyone is going silent,” says
Tarun Verma, Altera Corp. Senior Director of
Packaging Engineering. “We’re moving beyond
pre-competitive path fi nding, and everyone is
now working on their own solutions.”
“We believe that perhaps the time for silicon
interposers has come,” says Bill Chen, ASE
Fellow and Senior Technical Advisor, noting
that it is becoming the top topic at ongoing
industry events. With growing consensus
that wide I/O memory stack with TSV will
become available, the technical debate
increasingly centers on which applications
are right for 3D and for 2.5D, rather than
whether there is room for both. “The silicon
interposer is now a concept that people think
can be implemented – it won’t be easy, but it
is doable,” he notes. “It’s suffi ciently similar
to the old idea of multichip modules that
it’s not such foreign a concept.” Historically,
multichip modules were manufactured by one
company, so the idea of combining different
die from different makers was hard to accept,
and to implement. However, this is no longer
such a diffi cult concept today for the fablessfoundry-OSAT
community. Back then, test
and rework posed major challenges, and both
remain key challenges for the 3D and 2.5D
manufacturing community today. Cost also is
a top consideration, and inevitably there are
major challenges associated with that too. For
high volume manufacturing, an accelerated
learning curve and yield success will be key
to driving down systems cost.
3 D P a c k a g i n g
The most important advantage of interposers
is the ability to mix and match capabilities
on the interposer, to build the different
functions (processor, memory, analog,
RF, etc) each in their own optimum silicon
technology and then combine them, instead
of integrating them all in a SoC, argues Matt
Nowak, Qualcomm Senior Director, Advanced
Technology. “However, quantifi cation and
optimization of the benefi ts require detailed
‘pathfi nding’ analysis of specifi c product
architecture/technology combinations,” he
notes. The highest tiers of performance will
adopt the technology fi rst, where cost is not
a factor if advantages in form factor, signal
integrity and power savings are realized,
he concurs, pointing to computer servers,
network processors, FPGAs, and high
performance graphics. And interposers will
remain the best ongoing solution for some
high-end functions in computer and network
processing, where the signal and power
benefi ts cannot be achieved with other
existing technology.
Huemoeller expects interposer technology
to move down to the core mainstream chip
markets for desktops, tablets and TVs,
because the main high volume chip makers
will fi nd the direct integration of logic and
memory on wide I/O interposers will be
the lowest cost solution at the system
I S S U E N ° 2 3 M A Y 2 0 1 2
level for the logic/memory interface to
reduce latency and reduce the power usage
of driving memory. The next generation
above 8000 pin HBM JEDEC memory standard
is targeted at the center of the market.
Though the interposer will add cost, it will
ultimately allow the opportunity to reduce
both the size and the number of layers in the
motherboard, as well as the number of mask
layers at the wafer level, for potentially
signifi cant saving at the systems level. Even
as full 3D TSV technology develops, high
end logic makers are likely to keep using
interposers, as they are reluctant to put the
big vias into their leading edge logic chips,
leery of the potential issues associated
with low-k delamination and reliability, he
argues.
“Interposer technology will move down
to the desktop, tablet & TV markets as integration
of logic and Wide I/O memory is shown to be cost
effective at the system level while reducing
the latency and power usage driving memory,”
expects Ron Huemoeller, Amkor Technology
FINE-PITCH INTERPOSERS
« System partitioning » interposers
Two types of interposers
3D integrated passive devices
The main driver is heterogenous integration,
concurs Verma, who notes that multiple chips
on interposers provides lots of capability
in bandwidth expansion for Altera’s long
term roadmap, and those of its partner
TSMC, with which it developed its recently
announced 3D test vehicle. “With our focus
on communications infrastructure and high
speed networks, in my view the interposer
will continue to have a role even after full 3D
development, especially for high performance
applications. Our next generation product
portfolio will use interposers in both catalog
and customer driven products.”
COARSE INTERPOSERS
3D LED silicon submounts
Interposers for CMOS
image sensors
7
MEMS & sensor 3D
capping inteposers
Miscellaneous interposers
(3D Silicon & Glass Interposers report, July 2012, Yole Développement)

Cost and re-thinking interconnect
ecosystem remain key
challenges
Interposer cost of course still remains a
key challenge in most people’s minds,
but perhaps even more challenging is
re-thinking the working of much of the
traditional package interconnect sector.
“My 10,000 foot view is four big areas of
need,” says Verma. “We have to fi rst fi gure
out what customers want. Then there is
the design environment –how to partition
the design very early on in product design,
which is very different from what we’re
used to. Then there’s the manufacturing
environment. And fi nally there’s enabling
the ecosystem, where people will have to
work closely together with partners in new
ways. We need early path fi nding for this
infrastructure, for the technology and for the
viable business models at the same time…
It will be an exciting two to three years of
change for the foundries and the OSATs.”
Biggest challenge of all, says Nowak,
remains software partitioning. Cost remains
a major challenge for many applications, as
well as the related issues of yield, testing,
and identifying known good interposers.
Progress on meeting
some challenges
M A Y 2 0 1 2 I S S U E N ° 2 3
Interposer packaging costs themselves have
come down sharply from fi rst introduction
some 18 months ago when there was only
one manufacturer, and the technology
is still only in development. “We looked
at interposer manufacturing costs quite
hard, and determined customers’ target
pricing could be achieved, both at entry
level volumes and at future high volume
manufacturing, and at everything from
mid-end graphics applications to highend
routers,” says Huemoeller. Of course,
increasing volumes will help, as will
improvements in the less mature process
steps, like throughput for wafer thinning
and thin wafer handling, and the temporary
adhesive cost. He says general reliability for
multiple die on a 100μm thick interposer
with 10μm wide TSVs at 210μm pitch,
logic at 40μm pitch microbumps with 25μm
diameter passed level 4MRT, TC-B 1000
8
cycles, HTS 1000 hours and HAST 110°C,
85% RH 500 hours.
Front end fabs will most likely make
interposers for now, since they have the
depreciated 65nm tool sets, and decades
of experience doing 1-2μm features at
very high yields. However, that doesn’t
mean the interposers will necessarily need
65nm technology. Those assets are simply
available at present with excess capacity in
some cases. First generation of interposer
products will require 10μm wide vias and
40-50μm μbumps. To be competitive and
hit the pricing targets with decent margin,
suppliers will need to leverage depreciated
assets rather than new investment,
Huemoeller fi gures, and says Amkor has no
plans to do this internally from scratch.
“Our next generation product portfolio will use
interposers in both catalog and customer driven
products”, says Tarun Verma, Altera Corp.
TSV production intercepts - Amkor Technology view
Si InterpT + DDR3T + Logic
GPU, CPU (28nm)
Apps ProcessorT + SDR
Smart Phone / Table (28nm)
Memory (DDRT )
Server, Custom Mem.
45 & 32nm
Si InterposerT + Logic
ASIC, FPGA (28nm)
Logic - Backside Metal
Power Amp.
Die with TSV indicated by = T
Interp. Req'd
Production
Since 2010
But there will likely be room for a variety
of interposers. “With heterogeneous
integration, there will be a potential market
for interposers where the requirements
for pitch and L/S are less demanding,
such as within the analog and RF mixed
signal arena,” says Chen, noting ASE has
developed its own interposer technology for
such markets.
Still up in the air is who will do the rest of the
process, and how. One option being pioneered
Interposer Required for some platforms
Interposer Required
2011 2012 2013 2014 2015
(Courtesy of Amkor Technology)
by TSMC with Altera in its 3D test vehicle
is for the foundry to do the whole process,
attaching the chip to the interposer wafer and
then attaching the chip-interposer unit to the
package substrate. This allows for bonding
the die to a perfectly fl at interposer surface
before processing, avoids shipping thinned
wafers, and eliminates all the vendor interface
issues. But it also necessitates putting
known-good die on untested interposers,
until someone can fi gure out how to test the
passive interposers, although the mature
process technology used for interposers does
have very high yields.
An alternative approach is to ship the IC
wafers to the OSAT before thinning, and let
the OSAT do the thinning and passivation,
then attach the die to interposers already
bonded to package substrates. This also
avoids having to ship thinned wafers, uses
the existing infrastructure of assembly
equipment, and allows the assembler to
manage with any warpage or other issues
caused by backside processes, such as
passivation, that can impact assembly.
Huemoeller says Amkor customers so far
are all endorsing this approach of having
the OSAT do the backside fi nish, so all back
process quality and assembly are clearly the
responsibility of the assembler, after wafer
mapping clearly identifi es any front side
defects.
Chen notes that there is currently no one
single answer for how best to divide the
work fl ow of backside fi nish and assembly
with the interposers. “Our market is an
effi cient market, which means the most
effi cient solution will prevail,” he says.
3 D P a c k a g i n g

“Certainly, every case will be different, even
with the same players involved. In every
case, players all need to look at what each
can bring to the table and decide on the
most effi cient way to divide up the task.”
“There are advantages to each different
process fl ow, and proponents of both
approaches will likely fi nd a way to make
them happen. Technically both will work,
with collaboration of the right parties,”
says Verma. “The data on which is better
changes monthly—it’s a moving target.” He
argues that methods for testing interposers
are under development, and possibly some
methods developed to test substrates back
in the era of multichip modules that were
never much used could be resurrected.
Putting components on in sequence,
starting with the cheapest fi rst and doing
intermediate test before putting on the
more expensive components can also help
avoid wasting known-good die. He fi gures
both foundries and OSATs will ultimately
be involved in parts of the interposer
business, leading to economies of scale
and lower cost. And OSATs may fi gure out
how to make relative coarser interposers
using the existing packaging infrastructure
of depreciated back end equipment, which
could have a major impact on costs.
Most of the components of the technology
are in place, argues Verma, noting that
though the EDA infrastructure is still far
behind what’s needed for true 3D design,
current technology is good enough to
enable fi rst generation product. Plenty of
manufacturing technology issues remain
to reduce costs, but at least the issues are
fairly clear, with headroom for improvement
in thin wafer handling throughput and
adhesives, testing technology, assembly
of bumps at 40μm pitch and below, and
underfi ll materials. The trend is towards
compression bonding, for its big advantage
of less thermal cycling of the materials, which
can particularly impact the low-k dielectric
layers, says Huemoeller. But even thermal
compression bonding is not good enough
for the increasing number of bumps, argues
Vermaa. There’s a lot of concentrated effort
in developing alternatives, including direct
copper to copper bonding. Copper-copper
bonding has been proven by Ziptronix and
Intel, and will be needed at