Virtex-5 FPGA XtremeDSP Design Considerations User Guide - Xilinx

Chapter 1: DSP48E Description and Specifics
C
CEC
RSTC
D
EN
RST
Figure 1-8: C Port Logic
OPMODE, ALUMODE, and CARRYINSEL Port Logic
C Input to
Y and Z
Multiplexers and
Pattern Detector
The OPMODE, ALUMODE, and CARRYINSEL port logic supports flow through or
registered input control signals. Multiplexers controlled by configuration bits select flow
through or optional registers. The control port registers allow users to trade off increased
clock frequency (i.e., higher performance) vs. data latency. The registers have independent
clock enables and resets. The OPMODE and CARRYINSEL registers are reset by
RSTCTRL. The ALUMODE is reset by RSTALUMODE. The clock enables and the
OPMODE, ALUMODE, and CARRYINSEL port logic are shown in Figure 1-9.
OPMODE
CECTRL
RSTCTRL
ALUMODE
CEALUMODE
RSTALUMODE
CARRYINSEL
7
1
1
4
1
1
3
D
EN
D
EN
D
EN
30 www.xilinx.com Virtex-5 FPGA XtremeDSP Design Considerations
UG193 (v3.5) January 26, 2012
RST
RST
RST
48
48
48
UG193_c1_08_032806
To the X, Y, Z
Multiplexers and
3-Input Adder/Subtracter
Figure 1-9: OPMODE, ALUMODE, and CARRYINSEL Port Logic
7
4
3
To Adder/Subtracter
To Carry Input
Select Logic
UG193_c1_09_092106
R