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Tolerance & Immunity to Negative VS Transients<br />
IR’s New HVICs set an Industry benchmark<br />
outperforming the Competition by far<br />
10<br />
time [nsec]<br />
0 100 200 300 400 500 600 700<br />
0<br />
-10<br />
-20<br />
-30<br />
-40<br />
-21<br />
-26<br />
Competitor’s<br />
destructive<br />
Failures!!!<br />
amplitude [V]<br />
-50<br />
-60<br />
-70<br />
-80<br />
-90<br />
Datasheet SOA<br />
-50<br />
IR latch-up limit<br />
Point of Failure for Negative Vs Transient @ V BS =15V<br />
New –V S Immunity Circuitry for IR HVIC:<br />
IR’s new ICs NEVER flip or glitch HO!!<br />
(Latch-up can occur above SOA curve)<br />
Competitor S<br />
Competitor F<br />
IRS2607D
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