Trends from Ten Years of Soft Error Experimentation

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6T SRAM cell SER: NMOS depletion region plays important role March 24, 2009 Sun Microsystems 24
Traditional SRAM layout L-shaped OD Ref: Intel's 0.18um SRAM cell 25
Page 1 and 2: Trends from Ten Years of Soft Error
Page 3 and 4: Introduction ● Reliability and Av
Page 5 and 6: Early high altitude tests ● Broom
Page 7 and 8: Test Strategy ● Memory - Load pat
Page 9 and 10: Systems in the beam ● Good ● Ba
Page 11 and 12: Small low cost tester March 24, 200
Page 13 and 14: Tradeoff Summary ● System ● Tes
Page 15 and 16: Apparent beam attenuation Technolog
Page 17 and 18: Test Results March 24, 2009 Sun Mic
Page 19 and 20: SER trend for SRAM & Flops SRAM 19
Page 21 and 22: Effect of Vdd and Area Vdd ↓ Crit
Page 23: 6T SRAM cell Ref: Borrowed from EE2
Page 27 and 28: Raw SEU Rate Per Processor Relative
Page 33 and 34: Multi-cell upsets March 24, 2009 Su
Page 35 and 36: Design Scenarios : Parity ~16 μm
Page 37 and 38: Design Scenarios : ECC (2) ● Plot
Page 39: Questions ? March 24, 2009 Sun Micr

Trends from Ten Years of Soft Error Experimentation

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