Trends from Ten Years of Soft Error Experimentation

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Litho friendly layout Traditional layout New industry standard Ref: Ishida et. al., IEDM 98-201. 26
Raw SEU Rate Per Processor Relative Tech. (nm) Relative SEU in FITs/kbit uncorrected Mbits/Processor SEU/Processor 250 3.2 1.52 5.0 180 3.0 1.52 4.3 130 2.4 3.28 7.9 90 1.0 33.6 33.6 65 0.7 44.3 30.5 Optical shrink March 24, 2009 Sun Microsystems 27
Page 1 and 2: Trends from Ten Years of Soft Error
Page 3 and 4: Introduction ● Reliability and Av
Page 5 and 6: Early high altitude tests ● Broom
Page 7 and 8: Test Strategy ● Memory - Load pat
Page 9 and 10: Systems in the beam ● Good ● Ba
Page 11 and 12: Small low cost tester March 24, 200
Page 13 and 14: Tradeoff Summary ● System ● Tes
Page 15 and 16: Apparent beam attenuation Technolog
Page 17 and 18: Test Results March 24, 2009 Sun Mic
Page 19 and 20: SER trend for SRAM & Flops SRAM 19
Page 21 and 22: Effect of Vdd and Area Vdd ↓ Crit
Page 23 and 24: 6T SRAM cell Ref: Borrowed from EE2
Page 25: Traditional SRAM layout L-shaped OD
Page 29 and 30: Raw SEU Rate Per Processor Relative
Page 31 and 32: Raw SEU Rate Per Processor Relative
Page 33 and 34: Multi-cell upsets March 24, 2009 Su
Page 35 and 36: Design Scenarios : Parity ~16 μm
Page 37 and 38: Design Scenarios : ECC (2) ● Plot
Page 39: Questions ? March 24, 2009 Sun Micr

Trends from Ten Years of Soft Error Experimentation

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