EMI-EMC Analysis and Noise Reduction on PCB

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Supported Third-Party Layout Tools � Cadence Allegro v16.0 � Cadence APD v16.0 � Cadence SiP Digital/RF v15.7 � Cadence Virtuoso v6.1 � Mentor BoardStation 8.x � Mentor Expedition v2005 � Mentor PADS v2005.2 � Support coming for v2007 (v2005.x ASCII files can be exported from v2007) � Zuken CR5000 v9.0.2
5 Steps for <strong>EMC</strong> <strong>Analysis</strong> 1) Impedance <strong>Analysis</strong> <strong>and</strong> <strong>Noise</strong> <strong>Reduction</strong> 2) <strong>EMC</strong> Decoupling is an iterative Capacitor process <strong>Analysis</strong> 3) Signal Extraction It’s much easier to design for <strong>EMI</strong> prevention rather than try to correct problems later on 4) Emissions <strong>Analysis</strong> 5) Enclosure Simulation
Page 1 and 2: EMI-EMC</s
Page 3 and 4: Coupling process Conduction Conduct
Page 5 and 6: � Loops in which currents flow ac
Page 7 and 8: Low |Z| at 50 MHz Near-Fields from
Page 9 and 10: Pwr Noise Signal P
Page 11 and 12: MIXED SIGNAL PCB Virtual Prototypin
Page 13 and 14: SIWAVE Physical Model Extraction FP
Page 15: Layout Import and
Page 19 and 20: Plane Impedance Simulation PWR Impe
Page 21 and 22: Step 2 Decoupling Capacitor <strong
Page 23 and 24: Resonance Simulation � Scans enti
Page 25 and 26: PCB Resonances and
Page 27 and 28: Choosing Correct Capacitor � Buil
Page 29 and 30: Impedance and Volt
Page 31 and 32: Add 2 decoupling capacitor on hot s
Page 33 and 34: What-IF Analysis:
Page 35 and 36: SIwave - EM Model Extraction � SI
Page 37 and 38: V(U28_DQ10_D3) [V] V(U28_DQ10_D3) [
Page 39 and 40: 1.90 1.85 1.80 1.75 1.70 1.65 What-
Page 41 and 42: Real EMI Source in
Page 43 and 44: WRITE DDR READ DDR Emission <strong
Page 45 and 46: Step 5 Enclosure Simulation 1) Impe
Page 47: MICROPROCESSOR CKP CKN DDR SDRAM U2

EMI-EMC Analysis and Noise Reduction on PCB

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