EMI-EMC Analysis and Noise Reduction on PCB

<strong>EMI</strong>-<strong>EMC</strong> <strong>Analysis</strong> <strong>and</strong>
<strong>Noise</strong> <strong>Reduction</strong> on
Printed Circuit Board
Cristian Gozzi, Application Engineer
ANSOFT CORPORATION, Italy
E-mail: cgozzi@ansoft.com
Phone: +39 06 5916845

Agenda
� Brief overview of <strong>EMI</strong>-<strong>EMC</strong> noise
contribution on PCB
� <strong>EMI</strong>/<strong>EMC</strong> analysis
� Ansoft Solutions & Simulation capabilities
� 5 Steps for <strong>EMC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Noise</strong> <strong>Reduction</strong>
� Simulation review
� Question <strong>and</strong> Answers

Coupling process
Conduction
Conductive
<strong>EMI</strong> <strong>EMI</strong> Filters Filters
Elements of <strong>EMC</strong>
<strong>EMI</strong> <strong>EMI</strong> Filters Filters
<strong>EMI</strong> <strong>EMI</strong> source source
Space & Field
Capacitive Inductive Radiative
Immunity Immunity
EMS
Emission
Shields Shields
Middle High
Frequency
Application
Shields Shields Shields Shields Shields Shields

PCB <strong>EMI</strong> Sources
� Intentional Sources
� Expected or easily predicted sources for radiation
� Emissions from intentional signals include loop-mode sources.
� Unintentional Sources ( more than 90% of <strong>EMI</strong> *)
� Unexpected or “surprise” sources
� Emissions from unintentional signals include common-mode,
crosstalk coupling to I/O traces (PCB, PKG, <strong>and</strong> IC levels),
power planes, <strong>and</strong> other board structures.
*Reference from “ PCB Design for Real-
World <strong>EMI</strong> Control ” Bruce Archambeault

� Loops in which
currents flow act as
antennas
� Area of loop
determines
radiation efficiency
Radiated <strong>EMI</strong> Basics
� Injecting a realistic
current excitation
can predict radiation
i
i
i

� Current is the primary
cause of loop radiation
� High impedance power
distribution systems
generate noise in
proportion to current
Radiated <strong>EMI</strong> Basics
� Inductive paths generate
noise in proportion to
current switching speed
V =
IZ
PCB pwr/gnd layers
V =
L
di
dt

Low |Z| at 50 MHz
Near-Fields from PCB
High |Z| at 137 MHz

MIXED SIGNAL PCB Example
USB
GPS
Digital
Processing
Bluetooth
GPS

Pwr <strong>Noise</strong>
Signal
Power Integrity
- Switching <strong>Noise</strong>
- Impedance Profile
- Power/Gnd Plane Resonance
- Return Path discontinuities
PCB - Design Overview
Power Integrity
Electromagnetic
Interference
Signal Integrity
<strong>EMI</strong>/<strong>EMC</strong>
- Common mode radiation
- Differential mode radiation
Aggressors
Victims
Signal Integrity
- Impedance
- Crosstalk
- Reflection
- Termination
- Dielectric Losses

� Probe placement <strong>and</strong> Impedance
measurements
� Need connectors; difficult to place
in crytical points of PCB
� Timing of Digital lines
� Laborator measurements;
different instruments needed
(oscilloscope; logic analyzer etc.)
<strong>and</strong> difficult to place many probes
� Near Field Calculation probying all
over the PCB
� Manual Probe or Near Field Array
Scanner measurements needed
� Emission Tests
� Anechoic chamber measurements
PCB Prototyping
MEASUREMENTS
PERFORMED
<strong>EMC</strong> Issue?
DESIGN
SYSTEM
MANUFACTURE
PROTOTYPE
TIME & COSTS INCREASE !

MIXED SIGNAL PCB Virtual Prototyping
� Virtual Probe placement
<strong>and</strong> Impedance measurements
� Timing <strong>and</strong> Eye Diagram of Digital lines
� Near-Field Calculation all over the PCB
� Far-Field <strong>and</strong> Emission Tests
Ansoft Corporation 50.00 100.00 150.00 200.00 Nexxim1 250.00 300.00 350.00 400.00 450.00 500.00
Time [ns]
1.40
V(V_DDR_D0-R_U11-G8) [V]
V(V_DDR_D0-R_U11-G8) [V]
1.20
1.00
0.80
0.60
0.40
0.00 0.25 0.50 0.75 1.00 1.25
Time [ns]
1.50 1.75 2.00 2.25 2.50
1.40
0.90
Curve Info
V(DDR_U28_1V8)
Transient1
V(U28_DQ0_A8)
Transient1
V(U28_DQ10_D3)
Transient1
V(U28_DQ11_C2)
Transient1
V(U28_DQ12_C3)
Transient1
V(U28_DQ13_B2)
Transient1
V(U28_DQ14_B3)
Transient1
V(U28_DQ15_A2)
Transient1
XY Plot 3
0.40 Virtual Probing for Impedance <strong>Analysis</strong>
Time [us]
(PWR – GND pin groups highlighted)
10.00 15.00
12.38
Ansoft Corporation DDR Data BUS TOP DQ[0...15] View Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
Curve Info
V(V_DDR_D0-R_U11-G8)
Transient
BOTTOM View
1.80
1.75
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25

� HFSS – 3D Full-wave
Electromagnetic Field
Simulation
� SIwave - Full-wave EM
solver of PCBs for Signal
<strong>and</strong> Power Integrity
<strong>Analysis</strong>
� Designer/Nexxim –Time
<strong>and</strong> Frequency Domain
Simulator for Signal <strong>and</strong>
Power Integrity System
<strong>Analysis</strong>
Ansoft Tools for <strong>EMC</strong> Study

SIWAVE Physical Model Extraction
FPGA
SDRAM
PHYSICAL Real System SIWAVE Physical Model Extracted
� SIWAVE use Finite-Element-Method (FEM) plus Ansoft’s
proprietary auto-adaptive mesh to characterize <strong>and</strong> extract
the physical behavior of system

� Planes
� Isl<strong>and</strong>s
� Splits
� Voids
� Swiss Cheese
(holes effect)
� Board Edges
� Open Boundary
� Etching
� Traces
� Pads
SIWAVE PCB H<strong>and</strong>ling
� 3D features
� Vias
� Bodwire
� Components
� Capacitors
� Resistors
� Inductors
� Ferrites

Layout Import <strong>and</strong> Translation
� Direct access to Ansoft tools from Cadence environment
� Allegro layout is directly translated <strong>and</strong> imported in SIWAVE
� Component file is also imported
Cadence Allegro/APD
Access Ansoft Tools
directly from Allegro!

Supported Third-Party Layout Tools
� Cadence Allegro v16.0
� Cadence APD v16.0
� Cadence SiP Digital/RF v15.7
� Cadence Virtuoso v6.1
� Mentor BoardStation 8.x
� Mentor Expedition v2005
� Mentor PADS v2005.2
� Support coming for v2007 (v2005.x ASCII files
can be exported from v2007)
� Zuken CR5000 v9.0.2

5 Steps for <strong>EMC</strong> <strong>Analysis</strong>
1) Impedance <strong>Analysis</strong>
<strong>and</strong> <strong>Noise</strong> <strong>Reduction</strong>
2) <strong>EMC</strong> Decoupling is an iterative Capacitor process <strong>Analysis</strong>
3) Signal Extraction
It’s much easier to design for
<strong>EMI</strong> prevention rather than try
to correct problems later on
4) Emissions <strong>Analysis</strong>
5) Enclosure Simulation

Step
1
Impedance <strong>Analysis</strong>
1) Impedance <strong>Analysis</strong>
2) Decaps <strong>Analysis</strong>
3) Signal Extraction
4) Emissions <strong>Analysis</strong>
5) Enclosure Simulation
Mechanism: High plane impedance
causes currents to spread out more to
Find return path = larger antenna
Goal: Ensure a low impedance as seen by
active parts = drop less voltage!
Fix: Change stackup, plane cutouts <strong>and</strong>
decoupling as necessary
Bare PCB impedance profile

Plane Impedance Simulation
PWR Impedance
PWR net without decaps
Ztarget
MASK Spec.
PWR net with decaps
Fmax

Pwr
GND
Customer Case Example
Old NEW model
Old model NEW model
Impedance : Original layout
Pwr
Impedance: Improved layout
GND

Step
2
Decoupling Capacitor <strong>Analysis</strong>
1) Impedance <strong>Analysis</strong>
2) Decaps <strong>Analysis</strong>
3) Signal Extraction
4) Emissions <strong>Analysis</strong>
5) Enclosure Simulation
Goal: Ensure power planes has stable
voltage across frequency range
Fix: Change stackup, plane cutouts <strong>and</strong>
decoupling as necessary

PCB Resonances
� Resonance frequencies (Rectangle):
f
r
=
2π
c
ε
r
mπ
⎞
⎟
a ⎠
� Arbitrary shapes are difficult to predict.
⎛
⎜
⎝
2
⎛
+ ⎜
⎝
nπ
⎞
⎟
b ⎠
2

Resonance Simulation
� Scans entire PCB/PKG on all layers
� Eigenmode analysis identifies location
<strong>and</strong> frequency of natural cavity
resonances that exist between planes
� If a resonance is excited, Signal
Integrity <strong>and</strong> <strong>EMI</strong> can be compromised:
High Z, null in S21, excite parallel plate
waveguides propagation modes.

Resonance Modes Results
Red <strong>and</strong> Blue zone indicate the
High Impedance Peaks in the
planes at particular frequency
Net VDD_CORE Resonance @ 864MHz
Net 3V3_CODEC_A/D Resonance @ 1320MHz

PCB Resonances <strong>and</strong> <strong>EMI</strong>
� Return path current is disrupted at the via.
� Signal vias couple to the planes.
� Creates a feed for the parallel plate
waveguide.

Decoupling Capacitor on Package
On-chip Pwr/Gnd
Decoupling Capacitor
Ball Bonding
Power/Ground
Chip
Via
Wire Bonding Ball Bonding
Package P/G
Network
Chip Decoupling Decoupling Capacitor
Capacitor on Chip on Package
PCB P/G
Network
Decoupling Capacitor
on PCB
VRM
Bulk Capacitor
Near VRM
VRM

Choosing Correct Capacitor
� Built in Capacitor library (Vendor
measurement S-Parameter)
� Select by Vendor <strong>and</strong> Part number
� ESR, ESL included
� Examine component plot <strong>and</strong> properties
� Component attachment accurately modeled
from pad dimensions

Decoupling Capacitor effect on
PDS Impedance
1uF
0.1uF
Bare PCB
0.01uF
10uF
Total PDN

Impedance <strong>and</strong> Voltage distribution on
Planes accross Frequency
F1 F2
VDD_ABCDE0 F1_res @ 1.17GHz
VDD_ABCDE0 F2_res @ 1.29GHz

Step #1: Plane Impedance Simulation
Simulation Correlation
1.17 GHz
Step #4: Near Field <strong>Analysis</strong> around PCB
Step #2: Resonant Mode @1.17GHz Step #3: Far Field Emission Test @ 3meters
1.17 GHz

Add 2 decoupling capacitor on hot spots
to filter resonance mode @ 1.17GHz
What-IF <strong>Analysis</strong>
Filter Impedance Spike

What-IF <strong>Analysis</strong>
Before De-coupling capacitor After add De-coupling capacitor
1.8V Power Plane Impedance of uP has been reduced

What-IF <strong>Analysis</strong>:
Emission <strong>Reduction</strong> from PCB
Emission from PCB Edge
due to resonances @ 1.17GHz
Before De-coupling capacitor
<strong>Reduction</strong> of Emission
After add De-coupling capacitor

Step
3
Signal Extraction
1) Impedance <strong>Analysis</strong>
2) Decaps <strong>Analysis</strong>
3) Signal Extraction
4) Emissions <strong>Analysis</strong>
5) Enclosure Simulation
Ensure signals meet required
b<strong>and</strong>width
Change routing as necessary

SIwave – EM Model Extraction
� SIWAVE extract electromagnetic N-ports model (S-Parameters block) of
Driver-Receiver Communication channel (Data BUS, Clock, Data Strobe,
Power net etc.)
� This physical model include all possible coupling that exist between nets
have been extracted:
� Signal-to-Signal
� Signal-to-PWR/GND
� PWRi-to-PWRj
� This simulation capability allow to strictly couple Signal Integrity <strong>and</strong>
Power Integrity issues
uP
DRAM DRAM

DRIVER
logic_in
enable
V791
0 0
ANSOFT DESIGNER Setup
pullup
pulldown
uP_VDD_1V8_IO
io
out_of_in
IBIS model uP ST
RECEIVER
U29_DQ13_B2
Signal net
R882
VTT
Rtt
Power net
Power net
uP_SDRDQ10_W13
DDR_U29_1V8
logic_in
enable
Enable_DDR2
IBIS model DDR Micron
Signal net
pullup
pulldown
0
io
out_of_in
MICROPROCESSOR
CK P
CK N
DDR SDRAM U28
CLK
CLK#
DDR SDRAM U29
CLK
CLK#
CLOCK DATA STROBE
DQ SU
DQ SL
CLOCK DATA STROBE
U_DQS
L_DQS
CLOCK DATA STROBE
U_DQS
L_DQS
DATA DQ[0...15]
DATA DQ[0...15]
DATA DQ[0...15]
DDR WRITE Operation
TERMINATIONS
Quite Traces Power Planes
SIwave PCB Dynamic Link
uP
DDR DDR
Voltage Regulator
26MHz OSCILLATORS

V(U28_DQ10_D3) [V]
V(U28_DQ10_D3) [V]
1.45
1.25
1.05
0.85
0.65
0.45
NEXXIM – Transient Simulation
Ansoft Corporation EYE Diagramm U28 DQ10 Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
0.25
0.00 1.00 2.00 3.00 4.00
Time [ns]
5.00 6.00 7.00 8.00
1.25
0.75
0.25
0.03 0.23 0.43 0.63 0.83 1.03 1.23 1.43 1.63 1.83
Time [us]
Curve Inf o
V(U28_DQ10_D3)
Transient1
Ansoft Corporation Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
1.60
Curve Inf o
Y1 [V]
1.40
1.20
1.00
0.80
0.60
0.40
0.20
DDR CLK
V(U28_CKN)
Transient1
V(U28_CKP)
Transient1
0.00
20.00 40.00 60.00 80.00 100.00 120.00
Time [ns]
140.00 160.00 180.00 200.00
Curve Info
V(DDR_U28_1V8)
Transient1
V(U28_DQ0_A8)
Transient1
V(U28_DQ10_D3)
Transient1
V(U28_DQ11_C2)
Transient1
V(U28_DQ12_C3)
Transient1
V(U28_DQ13_B2)
Transient1
V(U28_DQ14_B3)
Transient1
V(U28_DQ15_A2)
Transient1
Curve Inf o
V(DDR_U28_1V8)
Transient1
V(DDR_U29_1V8)
Transient1
V(uP_VDD_1V8_IO)
Transient1
Ansoft Corporation DDR Data BUS DQ[0...15] Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
0.25
50.00 100.00 150.00 200.00 250.00 300.00
Time [ns]
350.00 400.00 450.00 500.00
DDR 1.8V Power Planes
Ansoft Corporation Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00
Time [ns]
1.80
1.75
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
1.80
1.79
1.77
1.76
1.75
1.80
1.79
1.77
1.76
1.75
1.85
1.80
1.75
1.70
1.65

Ansoft NameCorporation X Y
Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
1.87
m1
m2
35.1762
36.0287
1.8154
1.7996
Curve Inf o
F1 F2
V(uP_VDD_1V8_IO)
m3
1.85
36.8657 1.7797
Transient1
m4 37.6401 1.7758
V(uP_VDD_1V8_IO) [V]
1.82
1.80
1.77
1.75
1.72
1.70
F1
AC Voltage <strong>Noise</strong> on Power Net
m1
m2
F2
m3
m4
1.67 Name Delta(X) Delta(Y) Slope(Y) InvSlope(Y)
d(m1,m2) 0.8525 -0.0158 -0.0185 -53.9866
Power Integrity <strong>Analysis</strong>
uP 1.8V Power
F1=1/Delta_T1=1/0.8525ns=1.173GHz
F2=1/Delta_T2=1/0.7745ns=1.29GHz
d(m2,m3)
1.65
d(m3,m4)
30.00
0.8370
0.7745
-0.0199
-0.0040
40.00
-0.0238
-0.0051
-42.0473
-194.7995
50.00 60.00 70.00 80.00 90.00 100.00
Tim e [ns]
uP 1.8V Power Impedance [Ohm]

1.90
1.85
1.80
1.75
1.70
1.65
What-IF <strong>Analysis</strong>: Improvement on
Power <strong>and</strong> Signal Integrity
Ansoft Corporation Nexxim_PCB_MARELLI_SIwave_link_DDR_Read_mod
1.95
Curve Info
Y1 [V]
XY Plot 1
V(uP_VDD_1V8_IO)1
Imported
V(uP_VDD_1V8_IO)
Transient1
1.60
0.00 5.00 10.00 15.00 20.00 25.00
Time [ns]
30.00 35.00 40.00 45.00 50.00
New design
Original design
Ansoft Corporation Nexxim_PCB_MARELLI_SIwave_link_DDR_Read_mod
1.60
Curve Info
Y1 [V]
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
XY Plot 2
V(U28_CKN)1
Imported
V(U28_CKP)1
Imported
V(U28_CKN)1
Imported
V(U28_CKP)1
Imported
0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00
Time [ns]
New design
Original design
� Voltage noise (AC ripple) has been reduced by adding decoupling
capacitors on Power Plane to filter resonances; this modification has
also improved quality signal of clock traces (removed excessive
undershoot spikes)

Step
4
Emissions <strong>Analysis</strong>
1) Impedance <strong>Analysis</strong>
2) Decaps <strong>Analysis</strong>
3) Signal Extraction
4) Emissions <strong>Analysis</strong>
5) Enclosure Simulation
Verify <strong>EMI</strong> is at acceptable level
Optimize previous three simulations
Underst<strong>and</strong> trends that cause radiation
Isolate mechanisms to make informed tradeoffs

Real <strong>EMI</strong> Source into PCB
� Translates time domain response into spectrum <strong>and</strong> pars these frequency
domain data as voltage noise <strong>EMI</strong> sources into SIWAVE.
� Emission analysis will use these voltage noise info.
Ansoft Corporation
0.00
DDR CLK Spectrum
Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
Curve Info
dB(V(U28_CKP))
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
CLOCK
dB(V(U28_CKP))
Transient1
-100.00
0.00 0.10 0.20 0.30 0.40 0.50
Spectrum [GHz]
0.60 0.70 0.80 0.90 1.00
Ansoft Corporation DDR DQS Spectrum
Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
dB(V(U28_DQSU_E2))
-5.00
-25.00
-45.00
-65.00
-85.00
-105.00
STROBE
Curve Info
dB(V(U28_DQSU_E2))
Transient1
-125.00
0.00 0.10 0.20 0.30 0.40 0.50
Spectrum [GHz]
0.60 0.70 0.80 0.90 1.00
Ansoft Corporation
20.00
DDR Power 1.8V Spectrum Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
Curve Inf o
dB(V(DDR_U28_1V8))
0.00
-20.00
-40.00
-60.00
-80.00
-100.00
-120.00
POWER 1.8V
dB(V(DDR_U28_1V8))
Transient1
-140.00
0.00 0.10 0.20 0.30 0.40 0.50
Spectrum [GHz]
0.60 0.70 0.80 0.90 1.00

ANSOFT DESIGNER - SIWAVE
Dynamic Sourcing
Ansoft Corporation DDR CLK
Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
V(U28_CKP) [V]
1.40
1.20
1.00
0.80
0.60
0.40
0.20
Curve Info
V(U28_CKP)
Transient1
0.00
20.00 40.00 60.00 80.00 100.00 120.00
Time [ns]
140.00 160.00 180.00 200.00
Ansoft Corporation
0.00
DDR CLK Spectrum
Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
Curve Info
dB(V(U28_CKP))
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
dB(V(U28_CKP))
Transient1
-100.00
0.00 0.10 0.20 0.30 0.40 0.50
Spectrum [GHz]
0.60 0.70 0.80 0.90 1.00
CLOCK
Time Domain
FFT
CLOCK
Spectrum

WRITE DDR
READ DDR
Emission <strong>Analysis</strong> with SIWAVE
Voltage <strong>Noise</strong> Spectrum pushed from DESIGNER
Parallel
Normal

<strong>EMC</strong> Test: Measurement vs. Simulation
VERY CLOSE RESULTS !
Differences
Differences
on
on
amplitude
amplitude
between
between
misurated
misurated
<strong>and</strong>
<strong>and</strong>
simulated
simulated
emission
emission
are
are
due
due
to
to
following
following
factors:
factors:
-
-
SIwave
SIwave
compute
compute
total
total
radiated
radiated
field
field
on
on
a
a
sphere
sphere
with
with
a
a
radius
radius
of
of
1
1
meter,
meter,
so
so
on
on
simulation
simulation
it
it
is
is
not
not
take
take
account
account
for
for
Antenna/Cable
Antenna/Cable
losses,
losses,
Polarization
Polarization
<strong>and</strong>
<strong>and</strong>
Multi-path
Multi-path

Step
5
Enclosure Simulation
1) Impedance <strong>Analysis</strong>
2) Decaps <strong>Analysis</strong>
3) Signal Extraction
4) Emissions <strong>Analysis</strong>
5) Enclosure Simulation
Test performance of different
enclosures – does it work?
Iterate design as necessary

<strong>EMC</strong> from PCB into Enclosure
<strong>EMC</strong> Emission Test
Maximum |E| at 3 meters
Near Field <strong>EMI</strong> source from PCB

MICROPROCESSOR
CKP
CKN
DDR SDRAM U28
CLK
CLK#
DDR SDRAM U29
CLK
CLK#
CLOCK DATA STROBE
DQ SU
DQ SL
CLOCK DATA STROBE
U_DQS
L_DQS
CLOCK DATA STROBE
U_DQS
L_DQS
DATA DQ[0...15]
DATA DQ[0...15]
DATA DQ[0...15]
<strong>EMI</strong>-<strong>EMC</strong> <strong>Analysis</strong>
Virtual Prototyping with Ansoft Tools
DDR WRITE Operation
TERMINATIONS
Quite Traces Power Planes
SIwave PCB Dynamic Link
Voltage Regulator
26MHz OSCILLATORS
Curve Inf o
V(DDR_U28_1V8)
Transient1
V(U28_DQ0_A8)
Transient1
V(U28_DQ10_D3)
Transient1
V(U28_DQ11_C2)
Transient1
V(U28_DQ12_C3)
Transient1
V(U28_DQ13_B2)
Transient1
V(U28_DQ14_B3)
Transient1
V(U28_DQ15_A2)
Transient1
1.90
1.85
1.80
1.75
1.70
1.65
Ansoft Corporation DDR Data BUS DQ[0...15] Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
0.25
50.00 100.00 150.00 200.00 250.00 300.00
Time [ns]
350.00 400.00 450.00 500.00
Ansoft Corporation
1.95
XY Plot 1
Nexxim_PCB_MARELLI_SIwave_link_DDR_Read_mod
Curve Info
Y1 [V]
1.60
0.00 5.00 10.00 15.00 20.00 25.00
Time [ns]
30.00 35.00 40.00 45.00 50.00
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
1.80
1.75
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
0.25
1.25
V(uP_VDD_1V8_IO)1
Imported
V(uP_VDD_1V8_IO)
Transient1
Ansoft Corporation
0.00
DDR CLK Spectrum
Nexxim_PCB_MARELLI_SIwave_link_DDR_Write
Curve Inf o
dB(V(U28_CKP))
dB(V(U28_CKP))
Transient1
-100.00
0.00 0.10 0.20 0.30 0.40 0.50
Spectrum [GHz]
0.60 0.70 0.80 0.90 1.00