Systolic arrays for matrix multiplications

Conclusions Systolic arrays can be successfully used asaccelerators in application domains which needmatrix multiplication When dimension of problem is too large thanusage of fixed-size SA become significant mathematical model for realization of matrix-vectormultiplication on fixed-size linear SA is derived The memory interface that provides correspondingdata transfers from/to SA is designed in detail FPGA implementations of fixed-size systolic arraysand corresponding address generators are performed