Design and Applications of Delay Locked Loop

University of Niš
Faculty of Electronic Engineering
Department of Electronic
Goran Jovanović
Design and Applications of
Delay Locked Loop
DAAD Workshop "Embedded System Design"
Niš, , Serbia, 5-95
9 July 2010.

Delay elements and delay lines
Architecture and properties of DLL
circuits, comparison with PLL
Linearization of analog delay
element, three solutions
Application with delay elements and
DLL circuits

wide regulation range
linear delay regulation
characteristic
low power consumption
discrete characteristic
coarse regulation
high jitter level
Continual &
fine delay regulation
simple realization
resistant to interference
narrow regulation range
nonlinear delay
regulation
larger power
consumption
wide regulation
range,
fine regulation
complex
realization
complicated
control
larger power
consumption

Digital delay lines are realized as chain of
elements with fixed delay value.
The number of elements in a chain
determines the amount of the delay.

Digital delay lines
are controlled with:
multiplexer,
shift register and
CMOS switch

V P bias
V dd
M 4
M 2
V 0
M 1
i d3
W 4 /L 4
i d4
V ctrl
in
out
C L
V N bias
M 3
W 3 /L 3
CLK ref
1 2 3 4 5
CLK ref
EK 1 EK 2 EK 3 EK 4 EK 5
CLK out
(a)
Simple circuits with
structure of inverter or
buffer.
Control voltage
change:
DC operate point,
impedance value in
critical circuit’s node
1
2
3
4
5
CLK out
(b)

It consists of:
two inverters stage
bias circuit
2200
Transistors M 3
& M 4
limited
charging/ discharging current
of parasite output capacitance.
1800
1400
t
d
=
C
⋅V
L dd
2 ⋅ i d 3
1000
600
2.6 2.8 3 3.2 3.4 3.6 3.8 4
Voltage V c [V]

It consists of:
inverter stage
variable capacitive load
840
800
Inverter with variable capacitive output
impedance (transistor M 4 & M 8 )
Bias circuit is not necessary.
Control voltage V ctrl polarize gates
transistors M 3 & M 7 which work in linear
mode (like resistors) and determine
output impedance.
kašnjenje td [ps]
760
720
680
640
600
560
3 3.5 4 4.5 5
napon V ctrl [V]

V dd
M
V
5
ctrl
V dd
out A
in A
M 3 M 4
M 1 M 2
V dd
M 6
out B
in B
Delay elements with
differential input/output
latch structure
good resistance on interference
and compliance of rising and
falling edge delay
Differential delay elements use limited
charge/discharge current and parasite
output capacitance to obtain delay
very fine delay
regulation and good
resistance to noise
complex realization,
large power
consumption, small
output voltage level

Current starved delay
element has the best
features :
the wider range of
delay regulation,
simple realization,
low-power
consumption

DLL circuits is used for control delay elements and lines.
Ensures that the output clock signal to synchronize with a
reference clock.
DLL architectures is classified into
three types:
analog
digital
hybrid (with double loop)
If exist, phase error
between referent and
output signalsa,
negative feedback
loop corrected delay
value.

digital DLL
analog DLL

Delay td
digital DLL
TIME RASPONSE
analog DLL

the wider range of
delay regulation
fine regulation
complex realization
complex control
larger power
consumption

DL
CP
PD
DL
CP
PD
DL
CP
PD
I
k
k
k
C
s
k
sC
k
k
k
sC
k
k
s
D
s
D
⋅
⋅
⋅
+
=
⋅
⋅
+
⋅
⋅
=
1
1
1
)
(
)
0 (
C
k
I
f
C
k
k
k
DL
CP
ref
DL
CP
PD
N
⋅
⋅
=
⋅
⋅
=
ω
N
DL
CP
ref
I
DLL
s
k
I
f
C
s
s
D
s
D
s
H
ω
+
=
⋅
⋅
⋅
+
=
=
1
1
1
1
)
(
)
(
)
(
0
first order system,
absolute stable

θ ( s)
= θ
⋅ F(
s)
second order system,
0
PD CP VCO
H PLL( s)
=
potential unstable ( s)
s + K ⋅ K ⋅ K ⋅ F(
s)
i
K
⋅ K
PD
⋅ K
CP
VCO
Nisko-
Frekventni
Fltar
f ref
Naponski Kontrolisani Oscilator
VCO
Strujna
Pumpa
UP
Fazni
Detektor
NFF
SP
FD
V ctrl
DOWN
f out
ξ
H ( s)
=
1
ω n τ z
2
θ0(
s)
θ ( s)
i
=
s
2
2
n
2⋅ξ
⋅ωn
⋅ s + ω
+ 2⋅ξ
⋅ω
⋅ s + ω
= ωn
= K PD ⋅ KCP
⋅ KVCO
⋅ K F
n
2
n

Characteristic DLL PLL
Frequency
multiplying
No
yes
Architecture simple complex
transfer function firs order second order
stabile absolute conditional
locking time short long
delay range of
regulation
limited
unlimited
tracking jitter small large
PLL
2
, DLL
2
∆t ∆t
∆t
α ≅
ω
2ω
ref
2
2
2
PLL = α ⋅ ∆t VCO
PLL
∆t
2
= N ⋅ ∆
DLL t d
2

The proposed three solutions to the
analog voltage controlled lines with
linear regulation of the delay as a
function of control voltage :
with control threshold voltage
current starved delay element
with symmetrical load
current starved element with
nonlinear bias circuit
Proposed solutions is
differ in:
method of
implementation
is useful for different
range of delay
regulation

Delay is determined by:
charge/discharge current
output impedance (capacitance)
threshold voltage (hysteresis)
C
C
td LH = ( VH
+ −V−
) td
HL = ( V+ −VH
−)
I
I
1
2
CLKin
τ=t dLH
= t dHL
τ =
C ∆ V
I
V L
∆V=V H+
-V -
= V +
-V H-
I 1
=I 2
=I
CLKout

Delay is proportional:
output capacity and
threshold voltage (hysteresis)
and reciprocal:
charge/discharge output
current
CLK in I 2,i i=1,..,5
+V H
histerezis
I 1,i i=1,..,5
t
CLK out
t dLH T/2 t dHL T/2 t
-V H
V L
CLKout
voltage controlled
capacitance can not
be implemented in
linear and suitable
manner

It consist of :
integrator (IN)
threshold voltage generator
(GH)
comparator (K)
threshold voltage V H
has
opposite value for raisin
and falling clock edge, to
avoid changes in pulse
width.

V +
V+
V +
V B
M 7
M 5
M 6
V bp
V bn
M 4
M 3
M 2
M 1
I 1
SW 1
I 2
IN
V L
C=1pF
V H
CLK out
hysteresis
voltage
generator with
characteristic
V +
M 2
M 3
V ctrl
SW 2
M 12
V H+
M 9
M 10
CLK in
M 8
V H
V ctrl
V H+
V H-
M 1
M 11
V H-
scheme of delay line with hysteresis
voltage regulation

6.0V
4.0V
2.0V
0V
5.0V
4.0V
2.0V
0V
30ns
CLK in
V H+
V H-
V H+ V H-
3.6V 1.4V
3.4V 1.6V
3.2V 1.8V
3.0V 2.0V
0s 0.2us 0.4us 0.6us 0.8us 1.0us
t
5.0V
4.0V
2.0V
0V
60ns 530ns
t
t
560ns
delay in
function of
control
voltage
delay
linearity
error in
function of
control
voltage
[ns]
dτ
τ
52
50
48
46
44
42
40
38
2.6 2.8 3 3.2 3.4 3.6 3.8 4
1.5
1
0.5
0
-0.5
10 ns
x 10 -3
1 V
V ctrl [V]
-1
2.6 2.8 3 3.2 3.4 3.6 3.8 4
V ctrl [V]

The modification is made by
adding a transistors M 5
& M 6
They present symmetrical
load.
Symmetrical load increase the current
charging/discharging the output capacitance
and change shape of regulation characteristic.
Current is a variable and it value depends
from output voltage.
Symmetrical load provide negative feedback
which gives linear regulation characteristic.

current starved
delay element
with symmetrical load
⎛W
⎜
⎝ L
⎛W
⎜
⎝ L
3
3
5
5
⎞
⎟
⎠
⎞
⎟
⎠
delay linearity error in function of
control voltage
Delay in function of control
voltage
⎛W
⎜
⎝ L
⎛W
⎜
⎝ L
3
3
5
5
⎞
⎟
⎠
⎞
⎟
⎠

Delay tp [ps]
−
dV
0
C L = id
3 +
dt
i
d 5
t
p1
=
k
k
1
2
τ
( V − V )
g
t
⋅ arctan
k
k
1
2
( V − V )
2 ⎛Vdd
⎞
( V − V ) + ⎜ − V ⎟ ⋅ ( V −V
)
g
V
2
t
dd
⋅
⎝
k
k
1
2
2
g
t
⎠
t
dd
t

Bias circuit control
charging/discharging
current I cp
of output
C load
capacitance.
Interconnection of BIAS circuit and current
starved element
The delay is
determined by the
equation:
t
d
=
C
load
2 ⋅
⋅V
I
cp
dd
Typical, current I cp
in
a linear way depends
on the control
voltageV ctrl
.

V ctrl
R
Nonlinear bias circuits use
square characteristics of MOS
transistor in saturation.
Bias circuit is designed to
provide reciprocal relation
between current and voltage.

28
26
22
L A =10 m
L A =12 m
L A =14 m
18
14
-0.8 -0.4 0 0.4 0.8 1
V ctrl [V]
0.08
0.07
0.06
0.05
0.04
0.035
-0.8 -0.4 0 0.4 0.8 1
V ctrl [V]
2
1
0
-1
-2
-3
L A =10 m
L A =12 m
L A =14 m
L A =10 m
L A =12 m
L A =14 m
a)
b)
-4
-0.8 -0.4 0 0.4 0.8 1
V ctrl [V]
c)
Simulation
of:
bias circuit
and
current
starved
delay
element
BIAS circuit
simulation
60
50
40
30
25
-0.8 -0.4 0 0.4 0.8 1
V ctrl [V]
a)
3000
2500
2000
1500
1000
500
0
-500
-1000
-0.8 - 0.4 0 0.4 0.8 1
V ctrl [V]
b)

Bias circuit
I
LPF1
LPF2
four-stages delay line with nonlinear
bias circuit
UP
DOWN
DOWN
UP
CP1
CP2
I
DLL with two current pump.
It provides differential
control voltage.

Simulation
of DLL with
two charge
pump
and
nonlinear
bias circuit

DLL and delay lines include wide area
of applications :
fast RAM memory,
serial USB2 i IEEE 1394 interfaces
FPGA chips,
telecommunication,
circuits for PN coda tracking
spread spectrum systems
measuring and processing
equipment...
Some suggested
applications:
multi-frequencies and
multi-phases clock
synthesis with DLL
high-resolution time-todigital
converter
adaptive duty cycle
corrector

The most important DLL‘s
application is achieving the
correct transfer data
between two synchronous
digital blocks
synthesis and distribution of
clock signal, clock-skew and
jitter problems elimination

CLK ref
2.Ph_1
2.Ph_4
4.Ph_1
4.Ph_2
Phase Detector
Current pump
Loop Filter
V ctrl
Delay Line
EK 1 EK 2 EK 3 EK n
Edge Combiner Circuit
s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 1
CLK out
1.Ph_1
1.Ph_8
V ctrl+
V +
V +
M 2
CLK i-1
CLK i
t d
V ctrl-
AND 1
M 1
M 3
M 6
M 4
M 5
In 1
s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 1
s i
CLK ref
1.Ph_2
1.Ph_3
1.Ph_4
1.Ph_5
a)
1.Ph_6
1.Ph_7
1.Ph_8
2.Ph_1
2.Ph_2
2.Ph_3
b)
2.Ph_4
4.Ph_1
4.Ph_2
c)
CLK ref
s 1
s 2
s 3
d)
2.Ph_1 2.Ph_2 2.Ph_3 2.Ph_4
(a)
(b)
4. Ph_1 4. Ph_2

DLL based frequency multiplier uses voltage-controlled delay
elements which represents a significant advantage related to the
standard solution with a PLL frequency multiplier circuit which
uses voltage controlled ring oscillator.
Illustration form of
jitter accumulation in
PLL and DLL circuits for
frequency multiplying

The timing resolution of the delay
Vernier technique is determined by
the difference between two
propagation delay values.
Start signal spreads through the
upper (slower) delay line (t d1 ).
Stop signal is spread through the
lower (faster) line delay (t d2 ).
Measurements resolution of several
tens of pico-seconds can be achieved
if difference in delays between upper
and lower elements small enough.
Measurement range is equal to the
duration of one period of reference
clock.

stop start
Modifying
Vernier delay
technique
DLL is used
for
calibration
delay lines in
Vernier
convertora
Fazni
detektor

t x
t 4
t 5
t 6
t 7
t 8
t 9
S 1 C 1
1
t 0
t 1
t 2
t 3
S 2 C 2
1
S 3 C 3
1
S 4 C 4
S 7
S
1 elements.
1
6
1
C 7
C 8
1
9 C 9
1
1
S 10
1 Waveform of S i i C i represent start i stop
pulses on outputs of appropriate delay
S 5 C 5
S 6 C
8
C 10
S 11
C 12
S 11 0
S 12 0
5.0ns 10.0ns 15.0ns 20.0ns 25.0ns 30.0ns
time

V dd
V DCC
in
M 2
*
out
in
*
M 3
out
M 2
V dd
V DCC
V BP
in
V BN
M 1
M 1
(a)
V dd V dd
M 4
* M 6
M 2
M 3
(c)
*
in
out
M 5
V DCC
V DCC
(b)
6 stages
7 stages
(d)
out
Working principle of duty cycle
corrector is based on delay element
which gives a different delay value
for rising and falling edge of signal.
Circuit from Fig. (c) has the
widest range of regulation.
Circuits from Fig. (a), (b) and
(d) have influence or just on
expansion or just on
compression of pulses.

(a) Scheme
(b) Ekvivalent scheme
100
90
80
Pulse / period
ratio in function
of control voltage
Duty Cycle [%]
70
60
50
40
V ctrl
30
1.5 2 2.5 3 3.5
20
V ctrl [V]

Voltage
CLKin
PICSout
Spice
simulation for
different
values of
control
voltage
V ctrl

Symmetrical relation between pulse/pause is unmatched
when:
signal passes through a long series of buffers,
unbalance of N and P MOS transistors,
technology variations,
temperature or supply voltage have change ...
PWCL scheme
Waveform at
PWCL
obtained by
Spice
simulation

It is presented three new solutions for
linear analog delay line :
with threshold voltage control,
with symmetrical load,
with nonlinear bias circuit,
and proposed new and modified
existing application :
multi-frequency and multi-phase
clock synthesis with DLL
time-to-digital converter
adaptive pulse width control loop
The applied models and
design rules are for
technology companies
South Africa
Microelectronics (SAMES)