Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
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It consists <strong>of</strong>:<br />
inverter stage<br />
variable capacitive load<br />
840<br />
800<br />
Inverter with variable capacitive output<br />
impedance (transistor M 4 & M 8 )<br />
Bias circuit is not necessary.<br />
Control voltage V ctrl polarize gates<br />
transistors M 3 & M 7 which work in linear<br />
mode (like resistors) <strong>and</strong> determine<br />
output impedance.<br />
kašnjenje td [ps]<br />
760<br />
720<br />
680<br />
640<br />
600<br />
560<br />
3 3.5 4 4.5 5<br />
napon V ctrl [V]
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