Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
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<strong>Delay</strong> is determined by:<br />
charge/discharge current<br />
output impedance (capacitance)<br />
threshold voltage (hysteresis)<br />
C<br />
C<br />
td LH = ( VH<br />
+ −V−<br />
) td<br />
HL = ( V+ −VH<br />
−)<br />
I<br />
I<br />
1<br />
2<br />
CLKin<br />
τ=t dLH<br />
= t dHL<br />
τ =<br />
C ∆ V<br />
I<br />
V L<br />
∆V=V H+<br />
-V -<br />
= V +<br />
-V H-<br />
I 1<br />
=I 2<br />
=I<br />
CLKout