Design and Applications of Delay Locked Loop

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θ ( s) = θ ⋅ F( s) second order system, 0 PD CP VCO H PLL( s) = potential unstable ( s) s + K ⋅ K ⋅ K ⋅ F( s) i K ⋅ K PD ⋅ K CP VCO Nisko- Frekventni Fltar f ref Naponski Kontrolisani Oscilator VCO Strujna Pumpa UP Fazni Detektor NFF SP FD V ctrl DOWN f out ξ H ( s) = 1 ω n τ z 2 θ0( s) θ ( s) i = s 2 2 n 2⋅ξ ⋅ωn ⋅ s + ω + 2⋅ξ ⋅ω ⋅ s + ω = ωn = K PD ⋅ KCP ⋅ KVCO ⋅ K F n 2 n
Characteristic DLL PLL Frequency multiplying No yes Architecture simple complex transfer function firs order second order stabile absolute conditional locking time short long delay range <strong>of</strong> regulation limited unlimited tracking jitter small large PLL 2 , DLL 2 ∆t ∆t ∆t α ≅ ω 2ω ref 2 2 2 PLL = α ⋅ ∆t VCO PLL ∆t 2 = N ⋅ ∆ DLL t d 2
Page 1 and 2: University of Niš Faculty of Elect
Page 3 and 4: wide regulation range linear delay
Page 5 and 6: Digital delay lines are controlled
Page 7 and 8: It consists of: two inverters stage
Page 9 and 10: V dd M V 5 ctrl V dd out A in A M 3
Page 11 and 12: DLL circuits is used for control de
Page 13 and 14: Delay td digital DLL TIME RASPONSE
Page 15: DL CP PD DL CP PD DL CP PD I k k k
Page 19 and 20: Delay is determined by: charge/disc
Page 21 and 22: It consist of : integrator (IN) thr
Page 23 and 24: 6.0V 4.0V 2.0V 0V 5.0V 4.0V 2.0V 0V
Page 25 and 26: current starved delay element with
Page 27 and 28: Bias circuit control charging/disch
Page 29 and 30: 28 26 22 L A =10 m L A =12 m L A =1
Page 31 and 32: Simulation of DLL with two charge p
Page 33 and 34: The most important DLL‘s applicat
Page 35 and 36: DLL based frequency multiplier uses
Page 37 and 38: stop start Modifying Vernier delay
Page 39 and 40: V dd V DCC in M 2 * out in * M 3 ou
Page 41 and 42: Voltage CLKin PICSout Spice simulat
Page 43: It is presented three new solutions

Design and Applications of Delay Locked Loop

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