Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
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<strong>Delay</strong> is proportional:<br />
output capacity <strong>and</strong><br />
threshold voltage (hysteresis)<br />
<strong>and</strong> reciprocal:<br />
charge/discharge output<br />
current<br />
CLK in I 2,i i=1,..,5<br />
+V H<br />
histerezis<br />
I 1,i i=1,..,5<br />
t<br />
CLK out<br />
t dLH T/2 t dHL T/2 t<br />
-V H<br />
V L<br />
CLKout<br />
voltage controlled<br />
capacitance can not<br />
be implemented in<br />
linear <strong>and</strong> suitable<br />
manner
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