Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
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CLK ref<br />
2.Ph_1<br />
2.Ph_4<br />
4.Ph_1<br />
4.Ph_2<br />
Phase Detector<br />
Current pump<br />
<strong>Loop</strong> Filter<br />
V ctrl<br />
<strong>Delay</strong> Line<br />
EK 1 EK 2 EK 3 EK n<br />
Edge Combiner Circuit<br />
s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 1<br />
CLK out<br />
1.Ph_1<br />
1.Ph_8<br />
V ctrl+<br />
V +<br />
V +<br />
M 2<br />
CLK i-1<br />
CLK i<br />
t d<br />
V ctrl-<br />
AND 1<br />
M 1<br />
M 3<br />
M 6<br />
M 4<br />
M 5<br />
In 1<br />
s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 1<br />
s i<br />
CLK ref<br />
1.Ph_2<br />
1.Ph_3<br />
1.Ph_4<br />
1.Ph_5<br />
a)<br />
1.Ph_6<br />
1.Ph_7<br />
1.Ph_8<br />
2.Ph_1<br />
2.Ph_2<br />
2.Ph_3<br />
b)<br />
2.Ph_4<br />
4.Ph_1<br />
4.Ph_2<br />
c)<br />
CLK ref<br />
s 1<br />
s 2<br />
s 3<br />
d)<br />
2.Ph_1 2.Ph_2 2.Ph_3 2.Ph_4<br />
(a)<br />
(b)<br />
4. Ph_1 4. Ph_2
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