Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
Design and Applications of Delay Locked Loop
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28<br />
26<br />
22<br />
L A =10 m<br />
L A =12 m<br />
L A =14 m<br />
18<br />
14<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
0.08<br />
0.07<br />
0.06<br />
0.05<br />
0.04<br />
0.035<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
2<br />
1<br />
0<br />
-1<br />
-2<br />
-3<br />
L A =10 m<br />
L A =12 m<br />
L A =14 m<br />
L A =10 m<br />
L A =12 m<br />
L A =14 m<br />
a)<br />
b)<br />
-4<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
c)<br />
Simulation<br />
<strong>of</strong>:<br />
bias circuit<br />
<strong>and</strong><br />
current<br />
starved<br />
delay<br />
element<br />
BIAS circuit<br />
simulation<br />
60<br />
50<br />
40<br />
30<br />
25<br />
-0.8 -0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
a)<br />
3000<br />
2500<br />
2000<br />
1500<br />
1000<br />
500<br />
0<br />
-500<br />
-1000<br />
-0.8 - 0.4 0 0.4 0.8 1<br />
V ctrl [V]<br />
b)