Design and Applications of Delay Locked Loop

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V + V+ V + V B M 7 M 5 M 6 V bp V bn M 4 M 3 M 2 M 1 I 1 SW 1 I 2 IN V L C=1pF V H CLK out hysteresis voltage generator with characteristic V + M 2 M 3 V ctrl SW 2 M 12 V H+ M 9 M 10 CLK in M 8 V H V ctrl V H+ V H- M 1 M 11 V H- scheme of delay line with hysteresis voltage regulation
6.0V 4.0V 2.0V 0V 5.0V 4.0V 2.0V 0V 30ns CLK in V H+ V H- V H+ V H- 3.6V 1.4V 3.4V 1.6V 3.2V 1.8V 3.0V 2.0V 0s 0.2us 0.4us 0.6us 0.8us 1.0us t 5.0V 4.0V 2.0V 0V 60ns 530ns t t 560ns delay in function of control voltage delay linearity error in function of control voltage [ns] dτ τ 52 50 48 46 44 42 40 38 2.6 2.8 3 3.2 3.4 3.6 3.8 4 1.5 1 0.5 0 -0.5 10 ns x 10 -3 1 V V ctrl [V] -1 2.6 2.8 3 3.2 3.4 3.6 3.8 4 V ctrl [V]
Page 1 and 2: University of Niš Faculty of Elect
Page 3 and 4: wide regulation range linear delay
Page 5 and 6: Digital delay lines are controlled
Page 7 and 8: It consists of: two inverters stage
Page 9 and 10: V dd M V 5 ctrl V dd out A in A M 3
Page 11 and 12: DLL circuits is used for control de
Page 13 and 14: Delay td digital DLL TIME RASPONSE
Page 15 and 16: DL CP PD DL CP PD DL CP PD I k k k
Page 17 and 18: Characteristic DLL PLL Frequency mu
Page 19 and 20: Delay is determined by: charge/disc
Page 21: It consist of : integrator (IN) thr
Page 25 and 26: current starved delay element with
Page 27 and 28: Bias circuit control charging/disch
Page 29 and 30: 28 26 22 L A =10 m L A =12 m L A =1
Page 31 and 32: Simulation of DLL with two charge p
Page 33 and 34: The most important DLL‘s applicat
Page 35 and 36: DLL based frequency multiplier uses
Page 37 and 38: stop start Modifying Vernier delay
Page 39 and 40: V dd V DCC in M 2 * out in * M 3 ou
Page 41 and 42: Voltage CLKin PICSout Spice simulat
Page 43: It is presented three new solutions

Design and Applications of Delay Locked Loop

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