EBD_intro_slides.pdf - Microelectronic Systems Laboratory - EPFL

EDA Based DesignIntroductionAlain VachouxMicroelectronic Systems Laboratoryalain.vachoux@epfl.ch

Table of contents♦ Some definitions♦ Full-custom design flow♦ Semi-custom (standard cell based) design flowA. Vachoux, 2005-2006 EDA Based Design Introduction - 2

Electronic Design Automation (EDA)♦ Category of (software) tools for designing and producing electronic systemsincluding printed circuit boards (PCBs), integrated circuits (ICs), or systemson chips (SoCs)♦ Alternative terms:Computer-aided engineering (CAE), computer-aided design (CAD)♦ Largest EDA companies:• Cadence Design Systems (market value: US$ 3.5 billion)• Synopsys (market value: US$ 2.5 billion)• Mentor Graphics (market value: US$ 1.0 billion)• Magma Design Automation (market value: US$ 387 million)♦ To probe further:• http://www.eda.org/• http://www.edacafe.com/• http://www.dac.com/• http://www.date-conference.com/• http://www.deepchip.com/-- standard working groups-- commercial site-- main conference in US-- main conference in Europe-- AYNTKBATA about EDAA. Vachoux, 2005-2006 EDA Based Design Introduction - 3

Design process/flow (1/2)A. Vachoux, 2005-2006 EDA Based Design Introduction - 4

Design process/flow (2/2)♦ Requirements• What the system should do• Characteristics or features of thedesired (required) system♦ Specifications• Result of the requirementanalysis• Items, materials, or services• Procedures for validating therequirements♦ Architecture design• How the system should work• Hardware/software partitioning• Hardware partitioning(RF, analog, digital parts)• IP blocks (design reuse)♦ Architecture design (cont'd)• Performance evaluation(operability, speed, consumption,area, etc.)♦ Component design• Detailed/physical design• Block implementation♦ Manufacture• At foundry location (ASIC) or deviceprogramming (FPGA)♦ Test• Functional/structural testing ofchip samplesA. Vachoux, 2005-2006 EDA Based Design Introduction - 5

Design methodology♦ Series of standards, rules and procedures to optimize the designprocess/flow on the basis of particular criteria such as:• User's needs (performances)•Market relevance (cost)• Available resources (time to market)♦ EDA tools• Specification toolse.g., Matlab/Simulink, VHDL,diagram editors• Design toolse.g., schematic/layout editors, logicsynthesizers, place&route tools• Verification toolse.g., simulators, formal checkers,DRC, LVS• Test toolse.g., ATPG tools, fault simulators,scan insertion tools♦ Technological process• Full/semi-custom designProcess description (designrules, device models)Cell libraries (logic gates,custom blocks)IP libraries (memories, etc.)• Programmable devices (FPGA)Pre-placed configurable blocksProgrammable interconnectsIP blocks (memories,processor cores, etc.)A. Vachoux, 2005-2006 EDA Based Design Introduction - 6

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 7

Full-custom design process/flowDesign SpecificationsSchematic CaptureTechnology: 0.8 um twin-well CMOSPropagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case)Transition times of "sum" and "carry_out" Symbol signals creation

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 9

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 10

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 11

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 12

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 13

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 14

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 15

Full-custom design process/flowDesign SpecificationsSchematic CaptureSymbol creationSimulationLayoutDRC- Design Rule CheckParasitics ExtractionLVS – Layout versus Schematic CheckPost-Layout SimulationA. Vachoux, 2005-2006 EDA Based Design Introduction - 16

Semi-custom design process/flowDesign SpecificationsHDL RTL codingRTL simulationLogic SynthesisGate-Level SimulationStandard Cell Place and RouteTiming Delay ExtractionBackannotated Gate-Level SimulationSystem IntegrationA. Vachoux, 2005-2006 EDA Based Design Introduction - 17

Semi-custom design process/flowDesign SpecificationsHDL RTL codingTechnology: 0.8 um twin-well CMOSPropagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case)Transition times of "sum" and "carry_out" signals RTL simulation

Semi-custom design process/flowDesign Specificationsentity addsub isgeneric (NBITS: natural := 4);port (clk, rst, add: in std_logic;a, b: in unsigned(NBITS-1 downto 0);z : out unsigned(NBITS-1 downto 0));end entity addsub;HDL RTL codingarchitecture dfl of addsub isRTL signal simulation a_reg, b_reg, z_reg: unsigned(NBITS-1 downto 0);beginprocess (rst, clk)Logic begin Synthesisif rst = '1' thena_reg '0');b_reg '0');z '0');elsif clk'event and clk = '1' thena_reg

Semi-custom design process/flowDesign SpecificationsHDL RTL codingRTL simulationLogic SynthesisGate-Level SimulationStandard Cell Place and RouteTiming Delay ExtractionBackannotated Gate-Level SimulationSystem IntegrationA. Vachoux, 2005-2006 EDA Based Design Introduction - 20

Semi-custom design process/flowDesign SpecificationsHDL RTL codingRTL simulationLogic SynthesisGate-Level SimulationStandard Cell Place and RouteTiming Delay ExtractionBackannotated Gate-Level SimulationSystem IntegrationA. Vachoux, 2005-2006 EDA Based Design Introduction - 21

Semi-custom design process/flowDesign SpecificationsHDL RTL codingRTL simulationLogic SynthesisGate-Level SimulationStandard Cell Place and RouteTiming Delay ExtractionBackannotated Gate-Level SimulationSystem IntegrationA. Vachoux, 2005-2006 EDA Based Design Introduction - 22

Semi-custom design process/flowDesign SpecificationsHDL RTL codingRTL simulationLogic SynthesisGate-Level SimulationStandard Cell Place and RouteTiming Delay ExtractionBackannotated Gate-Level SimulationSystem IntegrationA. Vachoux, 2005-2006 EDA Based Design Introduction - 23

Semi-custom design process/flow(TIMESCALE 1ns)(CELL(DELAY(ABSOLUTEDesign SpecificationsHDL RTL coding(INTERCONNECT clk z_regx7x/C (0.0045:0.0045:0.0045) (0.0045:0.0045:0.0045))(INTERCONNECT clk z_regx6x/C (0.0044:0.0044:0.0044) (0.0044:0.0044:0.0044))(INTERCONNECT clk z_regx5x/C (0.0044:0.0044:0.0044) (0.0044:0.0044:0.0044))(INTERCONNECT clk z_regx4x/C (0.0044:0.0044:0.0044) (0.0044:0.0044:0.0044))RTL simulation(INTERCONNECT clk z_regx3x/C (0.0043:0.0043:0.0043) (0.0043:0.0043:0.0043))(INTERCONNECT clk z_regx2x/C (0.0046:0.0046:0.0046) (0.0046:0.0046:0.0046))...(CELL(CELLTYPE "INV3")(INSTANCE U93)(DELAY(ABSOLUTE(IOPATH A Q (0.6556:0.6556:0.6556) (0.411:0.411:0.411)))))...Logic SynthesisGate-Level SimulationStandard Cell Place and RouteTiming Delay ExtractionBackannotated Gate-Level SimulationSystem IntegrationA. Vachoux, 2005-2006 EDA Based Design Introduction - 24

Semi-custom design process/flowDesign SpecificationsHDL RTL codingRTL simulationLogic SynthesisGate-Level SimulationStandard Cell Place and RouteTiming Delay ExtractionBackannotated Gate-Level SimulationSystem IntegrationA. Vachoux, 2005-2006 EDA Based Design Introduction - 25

AcronymsAYNTKBATA: All You Need To Know But Afraid To AskASIC: Application-Specific Integrated CircuitASSP: Application-Specific Standard ProductATPG: Automatic Test Pattern GeneratorCAD: Computer-Aided DesignDRC: Design Rule CheckEDA: Electronic Design AutomationHDL: Hardware Description LanguageIP: Intellectual PropertyLVS: Layout Versus SchematicRTL: Register Transfer LevelSoC: System on ChipVHDL: Very high-speed integrated circuit HDLA. Vachoux, 2005-2006 EDA Based Design Introduction - 26