EBD_intro_slides.pdf - Microelectronic Systems Laboratory - EPFL

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Semi-custom design process/flowDesign SpecificationsHDL RTL codingTechnology: 0.8 um twin-well CMOSPropagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case)Transition times of "sum" and "carry_out" signals RTL simulation
Semi-custom design process/flowDesign Specificationsentity addsub isgeneric (NBITS: natural := 4);port (clk, rst, add: in std_logic;a, b: in unsigned(NBITS-1 downto 0);z : out unsigned(NBITS-1 downto 0));end entity addsub;HDL RTL codingarchitecture dfl of addsub isRTL signal simulation a_reg, b_reg, z_reg: unsigned(NBITS-1 downto 0);beginprocess (rst, clk)Logic begin Synthesisif rst = '1' thena_reg '0');b_reg '0');z '0');elsif clk'event and clk = '1' thena_reg
Page 1 and 2: EDA Based DesignIntroductionAlain V
Page 3 and 4: Electronic Design Automation (EDA)
Page 5 and 6: Design process/flow (2/2)♦ Requir
Page 7 and 8: Full-custom design process/flowDesi
Page 17: Semi-custom design process/flowDesi
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EBD_intro_slides.pdf - Microelectronic Systems Laboratory - EPFL

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