EBD_intro_slides.pdf - Microelectronic Systems Laboratory - EPFL

Semi-custom design process/flowDesign Specificationsentity addsub isgeneric (NBITS: natural := 4);port (clk, rst, add: in std_logic;a, b: in unsigned(NBITS-1 downto 0);z : out unsigned(NBITS-1 downto 0));end entity addsub;HDL RTL codingarchitecture dfl of addsub isRTL signal simulation a_reg, b_reg, z_reg: unsigned(NBITS-1 downto 0);beginprocess (rst, clk)Logic begin Synthesisif rst = '1' thena_reg '0');b_reg '0');z '0');elsif clk'event and clk = '1' thena_reg