Mobile Intel® 945 Express Chipset Family

More documents

Recommendations

Info

6.6.4 DMIPVCCTL - DMI Port VC Control B/D/F/Type: 0/0/0/DMIBAR Address Offset: C-Dh Default Value: 0000h Access: R/W; RO Size: 16 bits Bit Access Default Value 15:4 RO 000h Reserved 6.6.5 DMIVC0RCAP - DMI VC0 Resource Capability B/D/F/Type: 0/0/0/DMIBAR Address Offset: 10-13h Default Value: 00000001h Access: RO Size: 32 bits Device 0 Memory Mapped I/O Register Description 3:1 R/W 000b VC Arbitration Select (VCAS): This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. The value 000b when written to this field will indicate the VC arbitration scheme is hardware fixed (in the root complex). This field cannot be modified when more than one VC in the LPVC group is enabled. 000: Hardware fixed arbitration scheme - e.g., Round Robin Others: Reserved See the current PCI Local Bus Specification for more details. 0 RO 0b Reserved Bit Access Default Value 31:24 RO 00h Reserved 23 RO 0b Reserved 22:16 RO 00h Reserved Description 15 RO 0b Reject Snoop Transactions (REJSNPT): 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 1: Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. 14:8 RO 00h Reserved 7:0 RO 01h Port Arbitration Capability (PAC): Having only bit 0 set indicates that the only supported arbitration scheme for this VC is non-configurable hardwarefixed. 202 Datasheet
Device 0 Memory Mapped I/O Register 6.6.6 DMIVC0RCTL0 - DMI VC0 Resource Control B/D/F/Type: 0/0/0/DMIBAR Address Offset: 14-17h Default Value: 800000FFh Access: R/W; RO Size: 32 bits This register controls the resources associated with PCI <strong>Express</strong> Virtual Channel 0. Bit Access Default Value Description 31:31 RO 1b Virtual Channel 0 Enable (VC0E): For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. 30:27 RO 0h Reserved 26:24 RO 000b Virtual Channel 0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only. 23:20 RO 0h Reserved 19:17 R/W 000b Port Arbitration Select (PAS): Configures the VC resource to provide a particular Port Arbitration service. Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource. Because only bit 0 of that field is asserted. This field will always be programmed to 1. 16:8 RO 000h Reserved 7:1 R/W 7Fh 0 RO 1b Traffic Class / Virtual Channel 0 Map (TCVC0M): Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations within this field correspond to TC values. For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When more than one bit in this field is set, it indicates that multiple TCs are mapped to the VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled VC, software must ensure that no new or outstanding transactions with the TC labels are targeted at the given link. Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0. Datasheet 203
Page 1 and 2:
Mobile Intel® 945 Express Chipset
Page 3 and 4:
Contents 1 Introduction............
Page 5 and 6:
5.1.1 VID - Vendor Identification .
Page 7 and 8:
6.2.73 G5SC - Group 5 Strength Cont
Page 9 and 10:
7.1.1 VID1 - Vendor Identification
Page 11 and 12:
8.2.10 MMADR - Memory Mapped Range
Page 13 and 14:
11 Electrical Characteristics .....
Page 15 and 16:
23 System Memory Organization Suppo
Page 17 and 18:
Revision History Revision Number De
Page 19 and 20:
Introduction 1 Introduction This do
Page 21 and 22:
Introduction Figure 2. Intel Centri
Page 23 and 24:
Introduction 1.1 Mobile Intel® 945
Page 25 and 26:
Introduction 1.1.4.1 Analog CRT •
Page 27 and 28:
Introduction 1.1.10 Mobile Intel®
Page 29 and 30:
Introduction 1.5 Mobile Intel® 945
Page 31 and 32:
Introduction 1.8.7 ICH Support 1.8.
Page 33 and 34:
Introduction (Sheet 2 of 2) Term De
Page 35 and 36:
Signal Description 2 Signal Descrip
Page 37 and 38:
Signal Description Signal Name Type
Page 39 and 40:
Page 41 and 42:
Signal Description 2.2.2 DDR2 SDRAM
Page 43 and 44:
Page 45 and 46:
Signal Description 2.3.1 Serial DVO
Page 47 and 48:
Page 49 and 50:
Signal Description 2.5.4 Serial DVO
Page 51 and 52:
Signal Description LDDC_DATA SDVOCT
Page 53 and 54:
Signal Description 2.8 Platform Pow
Page 55 and 56:
Signal Description 2.10 Reset State
Page 57 and 58:
Signal Description 2.10.3 DDR2 SDRA
Page 59 and 60:
Signal Description 2.10.6 DDR SDRAM
Page 61 and 62:
Signal Description 2.10.9 DMI Signa
Page 63 and 64:
Signal Description 2.10.12 LVDS Sig
Page 65 and 66:
Signal Description 2.10.15 Reset an
Page 67 and 68:
(G)MCH Register Description 3 (G)MC
Page 69 and 70:
(G)MCH Configuration Process and Re
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Host Bridge Device 0 - Configuratio
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
Device 0 Memory Mapped I/O Register
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152: Device 0 Memory Mapped I/O Register
Page 201: Device 0 Memory Mapped I/O Register
Page 225 and 226: PCI Express Graphics Device 1 Confi
Page 253 and 254:
PCI Express Graphics Device 1 Confi
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Page 265 and 266:
Page 267 and 268:
Page 269 and 270:
Page 271 and 272:
Page 273 and 274:
Internal Graphics Device 2 Configur
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
Page 315 and 316:
Page 317 and 318:
Page 319 and 320:
System Address Map 9 System Address
Page 321 and 322:
System Address Map Figure 10. Syste
Page 323 and 324:
System Address Map 9.1.2.1 Compatib
Page 325 and 326:
System Address Map 9.2 Main Memory
Page 327 and 328:
System Address Map In an internal g
Page 329 and 330:
System Address Map 9.4 PCI Express
Page 331 and 332:
System Address Map Figure 14. Graph
Page 333 and 334:
System Address Map 9.7 SMM Space Re
Page 335 and 336:
System Address Map address signal i
Page 337 and 338:
Functional Description 10 Functiona
Page 339 and 340:
Functional Description 10.2 System
Page 341 and 342:
Functional Description 10.2.3.2 Dua
Page 343 and 344:
Functional Description 10.2.4.2 Pin
Page 345 and 346:
Functional Description Table 28. DR
Page 347 and 348:
Page 349 and 350:
Page 351 and 352:
Page 353 and 354:
Page 355 and 356:
Functional Description 10.2.8.1 Sel
Page 357 and 358:
Functional Description 10.3.1.2 Tra
Page 359 and 360:
Functional Description Figure 17. S
Page 361 and 362:
Functional Description Figure 19. S
Page 363 and 364:
Functional Description 10.4 Integra
Page 365 and 366:
Functional Description 10.4.1.3.2 P
Page 367 and 368:
Functional Description 10.4.1.6.3 T
Page 369 and 370:
Functional Description objects). Th
Page 371 and 372:
Functional Description The (G)MCH h
Page 373 and 374:
Functional Description 10.5.2 Plane
Page 375 and 376:
Functional Description 10.5.4 Displ
Page 377 and 378:
Functional Description clock freque
Page 379 and 380:
Functional Description Figure 23. L
Page 381 and 382:
Functional Description 10.5.4.4.2 S
Page 383 and 384:
Functional Description 10.6.2.2 CPU
Page 385 and 386:
Functional Description 10.6.4.2.3 C
Page 387 and 388:
Functional Description 10.6.5.1 CPU
Page 389 and 390:
Functional Description Figure 27. E
Page 391 and 392:
Functional Description 10.7.1.1 Int
Page 393 and 394:
Functional Description 10.7.1.2.5 T
Page 395 and 396:
Functional Description When process
Page 397 and 398:
Electrical Characteristics 11 Elect
Page 399 and 400:
Electrical Characteristics 11.2 Pow
Page 401 and 402:
Electrical Characteristics Table 49
Page 403 and 404:
Page 405 and 406:
Page 407 and 408:
Page 409 and 410:
Page 411 and 412:
Page 413 and 414:
Electrical Characteristics 11.4.3 T
Page 415 and 416:
Strapping Configuration 12 Strappin
Page 417 and 418:
Ballout and Package Information 13
Page 419 and 420:
Ballout and Package Information 13.
Page 421 and 422:
Ballout and Package Information Tab
Page 423 and 424:
Page 425 and 426:
Page 427 and 428:
Page 429 and 430:
Page 431 and 432:
Page 433 and 434:
Page 435 and 436:
Page 437 and 438:
Page 439 and 440:
Page 441 and 442:
Page 443 and 444:
Page 445 and 446:
Page 447 and 448:
Page 449 and 450:
Page 451 and 452:
Page 453 and 454:
Page 455 and 456:
Page 457 and 458:
Ballout and Package Information Fig
Page 459 and 460:
Page 461 and 462:
Page 463 and 464:
Page 465 and 466:
Page 467 and 468:
Page 469 and 470:
Page 471 and 472:
Page 473 and 474:
Page 475 and 476:
Page 477 and 478:
Page 479 and 480:
Page 481 and 482:
show all

Mobile Intel® 945 Express Chipset Family

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?