Mobile Intel® 945 Express Chipset Family

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Figure 3. Ultra Mobile Intel® 945GU Express Chipset Example System Diagram UXGA LFP TV PCI Express* SDVO TPV LVDS TV Out SDVO USB 2.0 (Supports 8 USB ports) IDE Intel ® High Definition Audio GPIO Other ASICs (Optional) TPM (Optional) Processor FSB 400 MHz Ultra Mobile Intel ® 82945GU GMCH Intel ® ICH7-U PCI Bus Power Management Clock Generators System Management (TCO) SMBus 2.0/I 2 C 3 PCI Devices Introduction 22 Datasheet DMI LPC I/F Super I/O DDR2 400 Flash BIOS System Memory 1 GB Maximum (X16 Memory Down 2 ranks, 8 devices)
Introduction 1.1 Mobile Intel® 945GM/GME Express Chipset Feature Support 1.1.1 Processor Support • Intel® Core2 Duo mobile processor, Intel® Core2 Duo mobile processor LV (Low Voltage), Intel® Core2 Duo mobile processor ULV (Ultra Low Voltage) • Intel® Core Duo processor, Intel® Core Duo processor LV (Low Voltage), Intel® Core Duo processor ULV (Ultra Low Voltage) • Intel® Core Solo processor ULV • Intel® Celeron® M processor (Intel Core processor based), Celeron M processor ULV • 533-MHz and 667-MHz front side bus (FSB) support • Source synchronous double-pumped (2x) Address • Source synchronous quad-pumped (4x) Data • Other key features are: — Support for DBI (Data Bus Inversion) — Support for MSI (Message Signaled Interrupt) — 32-bit interface to address up to 4 GB of memory — A 12-deep In-Order Queue to pipeline FSB commands • AGTL+ bus driver with integrated AGTL termination resistors 1.1.2 System Memory Support • Supports single-/dual-channel DDR2 SDRAM • Maximum Memory supported: up to 4 GB at 400, 533 and 667 MHz • 64-bit wide per channel • Three Memory Channel Configurations supported: — Single-Channel — Dual-Channel Symmetric — Dual-Channel Asymmetric • One SO-DIMM connector per channel • 256-Mb, 512-Mb and 1-Gb memory technologies supported • Support for x8 and x16 devices • Support for DDR2 On-Die Termination (ODT) • Enhanced Addressing support (XOR and Swap) • Intel® Rapid Memory Power Management (Intel® RMPM) • Dynamic row power-down • No support for Fast Chip Select mode • Support for 2N timings only • Supports Partial Writes to memory using Data Mask signals (DM) Datasheet 23
Page 1 and 2: Mobile Intel® 945 Express Chipset
Page 3 and 4: Contents 1 Introduction............
Page 5 and 6: 5.1.1 VID - Vendor Identification .
Page 7 and 8: 6.2.73 G5SC - Group 5 Strength Cont
Page 9 and 10: 7.1.1 VID1 - Vendor Identification
Page 11 and 12: 8.2.10 MMADR - Memory Mapped Range
Page 13 and 14: 11 Electrical Characteristics .....
Page 15 and 16: 23 System Memory Organization Suppo
Page 17 and 18: Revision History Revision Number De
Page 19 and 20: Introduction 1 Introduction This do
Page 21: Introduction Figure 2. Intel Centri
Page 25 and 26: Introduction 1.1.4.1 Analog CRT •
Page 27 and 28: Introduction 1.1.10 Mobile Intel®
Page 29 and 30: Introduction 1.5 Mobile Intel® 945
Page 31 and 32: Introduction 1.8.7 ICH Support 1.8.
Page 33 and 34: Introduction (Sheet 2 of 2) Term De
Page 35 and 36: Signal Description 2 Signal Descrip
Page 37 and 38: Signal Description Signal Name Type
Page 41 and 42: Signal Description 2.2.2 DDR2 SDRAM
Page 45 and 46: Signal Description 2.3.1 Serial DVO
Page 49 and 50: Signal Description 2.5.4 Serial DVO
Page 51 and 52: Signal Description LDDC_DATA SDVOCT
Page 53 and 54: Signal Description 2.8 Platform Pow
Page 55 and 56: Signal Description 2.10 Reset State
Page 57 and 58: Signal Description 2.10.3 DDR2 SDRA
Page 59 and 60: Signal Description 2.10.6 DDR SDRAM
Page 61 and 62: Signal Description 2.10.9 DMI Signa
Page 63 and 64: Signal Description 2.10.12 LVDS Sig
Page 65 and 66: Signal Description 2.10.15 Reset an
Page 67 and 68: (G)MCH Register Description 3 (G)MC
Page 69 and 70: (G)MCH Configuration Process and Re
Page 71 and 72: (G)MCH Configuration Process and Re
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(G)MCH Configuration Process and Re
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Host Bridge Device 0 - Configuratio
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Device 0 Memory Mapped I/O Register
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System Address Map 9 System Address
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System Address Map Figure 10. Syste
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System Address Map 9.1.2.1 Compatib
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System Address Map 9.2 Main Memory
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System Address Map In an internal g
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System Address Map 9.4 PCI Express
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System Address Map Figure 14. Graph
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System Address Map 9.7 SMM Space Re
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System Address Map address signal i
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Functional Description 10 Functiona
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Functional Description 10.2 System
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Functional Description 10.2.3.2 Dua
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Functional Description 10.2.4.2 Pin
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Functional Description Table 28. DR
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Functional Description 10.2.8.1 Sel
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Functional Description 10.3.1.2 Tra
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Functional Description Figure 17. S
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Functional Description Figure 19. S
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Functional Description 10.4 Integra
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Functional Description 10.4.1.3.2 P
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Functional Description The (G)MCH h
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Functional Description 10.5.2 Plane
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Functional Description 10.5.4 Displ
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Functional Description clock freque
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Functional Description Figure 23. L
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Functional Description 10.5.4.4.2 S
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Functional Description 10.6.2.2 CPU
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Functional Description 10.6.4.2.3 C
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Functional Description 10.6.5.1 CPU
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Functional Description Figure 27. E
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Functional Description 10.7.1.1 Int
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Functional Description When process
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Electrical Characteristics 11 Elect
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Electrical Characteristics 11.2 Pow
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Electrical Characteristics Table 49
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Electrical Characteristics 11.4.3 T
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Strapping Configuration 12 Strappin
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Mobile Intel® 945 Express Chipset Family

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