Mobile Intel® 945 Express Chipset Family
Mobile Intel® 945 Express Chipset Family
Mobile Intel® 945 Express Chipset Family
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6.4.24 EXTTSCS - External Thermal Sensor Control and Status............................. 191<br />
6.4.25 DFT_STRAP1 – DFT Register .................................................................. 192<br />
6.5 Device 0 MCHBAR ACPI Power Management Controls............................................ 193<br />
6.5.1 Power Management Mode Support Options............................................... 193<br />
6.5.2 C2C3TT - C2 to C3 Transition Timer ........................................................ 194<br />
6.5.3 C3C4TT - C3 to C4 Transition Timer ........................................................ 194<br />
6.5.4 MIPMC4 - Memory Interface Power Management Control 4 ......................... 195<br />
6.5.5 MIPMC5 - Memory Interface Power Management Control 5 ......................... 195<br />
6.5.6 MIPMC6 - Memory Interface Power Management Control 6 ......................... 195<br />
6.5.7 MIPMC7 - Memory Interface Power Management Control 7 ......................... 195<br />
6.5.8 PMCFG - Power Management Configuration .............................................. 196<br />
6.5.9 SLFRCS - Self-Refresh Channel Status ..................................................... 197<br />
6.5.10 GIPMC1 - Graphics Interface Power Management Control 1 ........................ 197<br />
6.5.11 FSBPMC1 - Front Side Bus Power Management Control 1............................ 197<br />
6.5.12 UPMC3 Unit Power Management Control 3................................................ 198<br />
6.5.13 ECO - ECO Bits..................................................................................... 198<br />
6.6 DMI RCRB....................................................................................................... 199<br />
6.6.1 DMIVCECH - DMI Virtual Channel Enhanced Capability............................... 200<br />
6.6.2 DMIPVCCAP1 - DMI Port VC Capability Register 1...................................... 201<br />
6.6.3 DMIPVCCAP2 - DMI Port VC Capability Register 2...................................... 201<br />
6.6.4 DMIPVCCTL - DMI Port VC Control........................................................... 202<br />
6.6.5 DMIVC0RCAP - DMI VC0 Resource Capability............................................ 202<br />
6.6.6 DMIVC0RCTL0 - DMI VC0 Resource Control .............................................. 203<br />
6.6.7 DMIVC0RSTS - DMI VC0 Resource Status................................................. 204<br />
6.6.8 DMIVC1RCAP - DMI VC1 Resource Capability............................................ 205<br />
6.6.9 DMIVC1RCTL1 - DMI VC1 Resource Control .............................................. 206<br />
6.6.10 DMIVC1RSTS - DMI VC1 Resource Status................................................. 207<br />
6.6.11 DMILE2A - DMI Link Entry 2 Address ....................................................... 208<br />
6.6.12 DMILCAP - DMI Link Capabilities ............................................................. 208<br />
6.6.13 DMILCTL - DMI Link Control ................................................................... 209<br />
6.6.14 DMILSTS - DMI Link Status .................................................................... 210<br />
6.6.15 DMICTL1 – DMI Control 1 ...................................................................... 210<br />
6.6.16 DMICTL2– DMI Control 2 ....................................................................... 211<br />
6.6.17 DMIDRCCFG - DMI DRC Configuration ..................................................... 211<br />
6.7 Egress Port (EP) RCRB...................................................................................... 211<br />
6.7.1 EP Register Summary............................................................................ 211<br />
6.7.2 EPPVCCAP1 - EP Port VC Capability Register 1 .......................................... 214<br />
6.7.3 EPPVCCAP2 - EP Port VC Capability Register 2 .......................................... 214<br />
6.7.4 EPVC0RCAP - EP VC 0 Resource Capability ............................................... 215<br />
6.7.5 EPVC0RCTL - EP VC 0 Resource Control ................................................... 216<br />
6.7.6 EPVC0RSTS - EP VC 0 Resource Status .................................................... 216<br />
6.7.7 EPVC1RCAP - EP VC 1 Resource Capability ............................................... 217<br />
6.7.8 EPVC1RCTL - EP VC 1 Resource Control ................................................... 218<br />
6.7.9 EPVC1RSTS - EP VC 1 Resource Status .................................................... 219<br />
6.7.10 EPVC1MTS - EP VC 1 Maximum Number of Time Slots ............................... 219<br />
6.7.11 EPVC1IST - EP VC 1 Isoch Slot Time........................................................ 219<br />
6.7.12 EPESD - EP Element Self Description ....................................................... 220<br />
6.7.13 EPLE1D - EP Link Entry 1 Description....................................................... 221<br />
6.7.14 EPLE1A - EP Link Entry 1 Address ........................................................... 222<br />
6.7.15 EPLE2D - EP Link Entry 2 Description....................................................... 223<br />
6.7.16 EPLE2A - EP Link Entry 2 Address ........................................................... 224<br />
6.7.17 PORTARB - Port Arbitration Table ............................................................ 224<br />
7 PCI <strong>Express</strong> Graphics Device 1 Configuration Registers (D1:F0) ............................ 225<br />
7.1 PEG Device 1 Function 0 Configuration Register Summary..................................... 225<br />
8 Datasheet
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