Test-Generation-Based Fault Detection in Analog ... - ETRI Journal

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circuit.Permanent faults are further classified into catastrophic faults(open and short) and parametric faults (due to disturbance inthe process parameters). When a catastrophic fault occurs, thetopology of the circuit is changed. Due to parametric faults, theperformance parameters of each manufactured circuit deviatefrom the nominal one and therefore correspond to a differentpoint in each parameter space. If each parameter of the circuitis within a fault free space, then the circuit is treated as faultfree; otherwise, it is considered a faulty circuit.In this paper, catastrophic and parametric faults are taken asfault models for analog circuits, which are designed withresistors, capacitors, MOSFETs, and bipolar junctiontransistors. The testing issues related to these faults areaddressed in this study.III. Test Pattern GenerationSince the cost of testing a VLSI chip is a significant fractionof the manufacturing cost, the time required to test a chipshould be minimized, and there should be significant faultcoverage. The objective of the automatic test pattern generatoris to find an optimal set of test stimuli which detects allmodeled faults, that is, a set of test stimuli which when appliedto the circuit can distinguish between the correct circuit and anycircuit with a modeled fault.The goal of the proposed approach is to compute a set of teststimuli that maximizes the fault coverage while minimizingtest access. Therefore, the problem of test signal generation isan optimization problem in principle. Test vector generationusing deterministic techniques is highly complex and timeconsuming because of the extremely large search spacesinvolved. Therefore, artificial intelligence methods have gainedmuch attention [1], [2].Genetic algorithms are search optimization algorithms basedon the mechanics of natural genetics that attempt to use similarmethods for selection and reproduction to solve variousoptimization problems. Genetic algorithms have proven to beeffective in VLSI applications, including circuit layout andpartitioning, cell placement, routing, and automatic testgeneration. The proposed method uses a genetic algorithm forthe generation of the test stimulus which detects bothcatastrophic and parametric faults present in the circuit undertest (CUT).In the literature, a genetic algorithm is used as a test patterngenerator [1], [2] to generate a piece-wise linear (PWL)stimulus. In [1] and [2], multiple node points in the circuits areconsidered for detecting faults in the CUT. However, incomplex systems all nodes in the circuit may not be accessible.Therefore, in this work only the output node is considered formeasurements and the output response is analyzed usingwavelets.1. PWL Signal GenerationBy exciting the CUT with pulses and ramps whosefrequency spectrum stretches over a wide range of frequencies,all faults can be made visible in the measurement space. Thus,a transient PWL signal is generated for detection of bothcatastrophic and parametric faults present in the circuits. Togenerate the PWL test signal, a genetic algorithm is used. Each testvector is a transient stimulus.Figure 1 shows an example test vector. The amplitude limitfor each test vector is fixed based on the allowable range ofinput signal for the circuit, and the frequency of the stimulus isfixed based on the allowable operating frequency of the circuits.For example, if a circuit has a supply voltage of 2.5 V, a gain of2, and a 1 MHz bandwidth, then the amplitude range for thePWL stimulus is fixed from -1 to +1 and the frequency is fixedfrom 1 Hz to 1 MHz. The length of the PWL signal is fixedbased on the amplitude level and frequency of operation of theCUT. Initial random vectors (PWL test signals) are selectedsuch that all amplitude levels are covered.Amplitude1.51.00.50.0-0.5-1.0-1.52. Bounds for Parameters1 2 3 4 5 6 7 8TimeFig. 1. PWL test vector.For the given CUT, the bounds of the parameters are foundas follows.In general, a circuit is bounded by n specifications, S =[s 1 , s 2 ,∙∙∙, s n ]. For designing the circuit, m parameters, P =[p 1 , p 2 ,∙∙∙, p m ] are used. Each specification is dependent on oneor more parameters. Under single parametric (p i ) faultassumption, upper and lower bounds of the parameters arefixed for each specification. Given an acceptable range of s j(upper bound s j u , lower bound s j l ), the accepted tolerance rangeof p i (upper bound p iu, lower bound p i l ) can be found as shownin Fig. 2.The final upper and lower bounds of the accepted range forp i are found as follows:p u i = min (p u i1 , p u i2 ,∙∙∙, p u in ), (1)p l i = max (p l i1 , p l i2 ,∙∙∙, p l in ). (2)210 Palanisamy Kalpana et al. ETRI Journal, Volume 31, Number 2, April 2009
Faills jlp ijFailp jlPassp iklPasss juNominal valuep ijup ikuFailFailFig. 2. Bounds for parameters.After setting the bounds for parameters, the circuit issimulated under fault-free and faulty conditions.3. Feature Extraction Using WaveletsWavelet transform (WT) is capable of providing the time andfrequency resolution simultaneously and hence giving timefrequencyrepresentation of the signal. Deviation of anyparameter alters the specifications of the circuit. Thesespecifications may be represented as time domain or frequencydomain units. If both time and frequency domain informationare available, then all possible faults present in the circuit canbe detected.Generally, the presence of catastrophic faults changes thefunctioning of the circuit. Some of them do not change thecircuit functioning fully and affect only the specifications of thecircuit. In such cases, it is necessary to obtain both time andfrequency domain information about the signal; therefore,wavelet decomposition is performed on the output signal.The output voltage response of the signal is captured and issampled with the sampling frequency of 5f, where f is the basicfrequency of the signal. When this signal passes through thefilter bank, the multiresolution decomposition of the signaltakes place. Two filters are present at each stage of resolution.The first filter is the mother wavelet, which is high pass innature. The second filter is low pass in nature. Thedownsampled output of the high pass filter provides the detailcoefficients, and the low pass filter provides the approximationcoefficients. The detail and approximation coefficients reflectthe high and low frequency contents of the signal.The frequency components at different levels in thedecomposed signal for the signal of frequency 5f are shownin Table 1. Since the approximation coefficients give the basicstructure of the signal, approximation coefficients are used foranalysis. For the selection of a suitable wavelet, analysis isperformed using different wavelets and one which showsmaximum classification efficiency is chosen for classificationof faulty circuits. Since the sampling frequency is 5f, the signalis decomposed into five levels. The wavelet coefficients fromlevel one to level three contain most of the information aboutthe signal.p jus js kp iTable 1. Frequency components at different levels in the decomposedsignal.Detail coefficientApproximation coefficientLevel 1 2.5f –5f 0f –2.5fLevel 2 1.25f –2.5f 0f –1.25fLevel 3 0.625f –1.25f 0f –0.625fLevel 4 0.3125f –0.625f 0f –0.3125fLevel 5 0.15625f –0.3125f 0f –0.15625fPWL signalgenerationTest optimization usinggenetic algorithmFault simulation(CUT)EvaluatefitnessFeatureextraction usingwaveletsFig. 3. Test pattern generation using genetic algorithm andwavelets.4. Proposed Specification Driven Test Pattern GenerationMethodAn overview of the proposed test generation methodology isshown in Fig. 3. The input to the proposed test generatorconsists of the circuit description and the specifications of thecircuit. The output of the test generator consists of test stimuli.The nominal specifications (gain and BW) for the CUT arefound. The acceptable deviation for each parameter (internaland external) is decided based on the given lower and upperbound of the circuit specifications as discussed in section III.2.After the bounds for the parameters are set, the circuit issimulated under fault-free and faulty conditions.A genetic algorithm is used to find the optimal test stimulus.The initial population is generated randomly. All theparameters in the circuit are varied within their acceptablerange of values and Monte Carlo analysis is performed for eachtest pattern. The same test patterns are applied to the fault-freecircuit and the nominal results are observed. The output signalis sampled and wavelet decomposition is performed for everyMonte Carlo result as well as the nominal result. The root meansquare error (RMSE) is calculated between the waveletcoefficients of the nominal result and the wavelet coefficientsof each Monte Carlo result. From this array of MSE values, theminimum and maximum values are chosen. These valuesdetermine the acceptable (threshold) range for the fault freecircuit.Then faults are introduced in the circuit one by one from thefault list, and faults are simulated for each test vector. TheRMSE is calculated as before using wavelets. If this RMSEETRI Journal, Volume 31, Number 2, April 2009 Palanisamy Kalpana et al. 211
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