Test-Generation-Based Fault Detection in Analog ... - ETRI Journal

Table 7. Classification results of SVF using PNN with parametricfaults.Minimum fractionvariance (PCA)1%2%5%SpreadPNNCoif3%C %P %Q0.1 100 100 1000.2 100 100 1000.3 100 100 1000.1 100 100 1000.2 100 100 1000.3 100 100 1000.1 100 100 1000.2 100 100 1000.3 100 100 100Table 8. Comparison of results obtained using the pseudorandom andPWL methods.IEEE benchmark circuitsOperationalamplifierState variablefilterVI. ConclusionCatastrophic faultPseudorandommethodPWLmethodParametric faultPseudorandommethodPWLmethod100% 100% 94.5% 100%100% 100% 95% 100%In the proposed PWL-based testing method, specificationdriven PWL stimulus is generated using a genetic algorithm.The conventional PWL generation method uses measurementsfrom multiple nodes in the circuit, whereas the proposed PWLgeneration method takes only the output node measurements.This is a very important feature of the proposed method. Whenthe circuits were tested with generated PWL signal, it wasfound that the proposed method achieves 100% fault coveragefor catastrophic faults and parametric faults present in AnalogVLSI circuits.References[1] V.N. Pramodchandran and A. Chatterjee, “Test Generation forComprehensive Testing of Linear Analog Circuits UsingTransient Response Sampling,” Int’l Conf. on Computer AidedDesign, 1997, pp. 382-385.[2] V.N. Pramodchandran and A. Chatterjee, “Specification-DrivenTest Design for Analog Circuits,” IEEE Int’l Symp. on Defect andFault Tolerance in VLSI Systems, 1998, pp. 335-340.[3] P. Kalpana and K. Gunavathi, “Specification Based Test PatternGeneration Using Genetic Algorithm and Wavelets,” Int’l Conf.on VLSI Design, 2005, pp. 504-507.[4] S.S. Somayajula, E. Sanchez-Sinencio, and Gyvez, “Analog FaultDiagnosis Based on Ramping Power Supply Current SignatureClusters,” IEEE Trans. on Circuits and Systems–II, vol. 43, 1996,pp. 703-712.[5] Z.R. Yang et al., “Applying a Robust Heteroscedastic ProbabilisticNeural Network to Analog Fault Detection and Classification,”IEEE Trans. on CAD, vol. 19, no. 1, 2001, pp. 142-151.[6] F. Aminian and M. Aminian, “Fault Diagnosis of Analog CircuitsUsing Bayesian Neural Networks with Wavelet Transform asPreprocessor,” J. of Electronic Testing, vol. 17, 2001, pp. 29-36.[7] F. Aminian, M. Aminian, and H.W. Collins, “Analog FaultDiagnosis of Actual Circuits Using Neural Networks,” IEEETrans. on Instrumentation and Measurement, vol. 51, no. 3, 2002,pp. 544-550.[8] P. Kalpana and K. Gunavathi, “Wavelet Based Fault Detection inAnalog VLSI Circuits Using Neural Networks,” Applied SoftComputing Journal, 2008, pp. 1592-1598.Palanisamy Kalpana received her BE degreein electronics and communication engineering,and her ME degree in applied electronics, in1992 and 2002, respectively, from PSG Collegeof Technology, Coimbatore, India. She iscurrently working as an assistant professor inthe ECE Department of the PSG College ofTechnology. Her research interests include ASIC design, CAD ofVLSI design, reconfigurable computing and testing of digital, analog,and mixed signal VLSI circuits.Kandasamy Gunavathi received the BEdegree in electronics and communicationengineering, the ME degree in computer scienceand engineering, and the PhD in 1985, 1989,and 1998, respectively, from PSG College ofTechnology, Coimbatore, Tamil Nadu, India.Her research interests include low-power VLSIdesign, as well as design and testing of digital, analog, and mixedsignal VLSI circuits. She is currently working as a professor with theECE department of PSG College of Technology. She has around 20years of teaching and research experience and is a life member of ISTE.She has published papers in 20 national and international journals and60 national and international conference publications.214 Palanisamy Kalpana et al. ETRI Journal, Volume 31, Number 2, April 2009