Quality Assurance - Index of

The CompanySilicon Systems specializes in the design and manufacture of application-specific,mixed-signal integrated circuits (MSICs®). It offers a sophisticated line of custom andstandard ICs aimed primarily at the storage, communications and industrial marketplace.The company, which is headquartered in California, 30 miles south of Los Angeles, wasfounded in 1972 as a design center. It soon entered into manufacturing and today hasfabrication sites in California and approximately 2,000 employees worldwide. Additionaloperations include assembly and test facilities in California and Singapore, and designengineering centers in California, Colorado, Tokyo and Singapore.Reliability and quality are built into Silicon Systems' products through the use of statisticalproblem solving techniques, analytical controls, and other quantitative methods. SiliconSystems has successfully met quality standards established by the International Organizationof Standardization that governs ISO 9000 certification regulations. Silicon Systems' domesticfacilities have received ISO 9001 certification for Quality Management Systems applicable todesign and manufacture, and, Silicon Systems' Singapore facility has achieved ISO 9002certification which is pertinent to production and installation.The company is committed to the goal of customer satisfaction through the on-time delivery ofdefect-free products that meet or exceed the customer's expectations and requirements. Listedin the back of this publication is a worldwide network of sales representatives and distributorsready to serve you.CERTIFIEDISO 9001~ISI=I ....~ ~ ~1--'~----Silicon Systems, Inc.Quality Management Systems

-------1995 Data Book

NOTICEAll products listed herein and subsequently sold by Silicon Systems, Inc. are subject to theterms and conditions contained in the Silicon Systems Order Acknowledgment Formapplicable to the sale, including those pertaining to warranty, patent infringement andlimitation of liability. Purchasers of these products acquire no rights in the technologyincorporated therein, absent the express written consent of Silicon Systems, Inc. SiliconSystems, Inc. makes no warranty, express or implied, with regard to the information set forthin this publication, nor does it warrant that the products described herein are merchantableor suitable for a particular purpose. Silicon Systems, Inc. reserves the right to discontinueproduction of any product, change a product specification and/or revise product pricing at anytime with, or without, notice.Applications requiring mechanical and electrical parameters outside of the publishedspecifications are not recommended without additional review and acceptance by SiliconSystems, Inc. Silicon Systems, Inc. further assumes no responsibility for the use of anyintegrated circuit technology other than integrated circuit technology embodied in a SiliconSystems, Inc. product. These products are not authorized for use as components in lifesupport devices or other medical systems.© Copyright 1995 Silicon Systems, Inc. All rights reserved. Product and company names listed are trademarks of theirrespective companies.K-Series integrated circuits are protected by the following patents:4,691,172/4,777,453/4,847,868/4,866,739/4,870,370 /4,789,995

ContentsTarget, Advanced andPreliminary InformationIn this data book the following conventionsare used in designating a data sheet''Target,'' "Advanced" or "Preliminary":Target Specification-The target specification is intended as aninitial disclosure of specification goals forthe product. Product is in first stages ofdesign cycle.Advance Information-Indicates a product still in the design cycle,undergoing testing processes, and anyspecifications are based on deSign goalsonly. Do not use for final design.Preliminary Data-Indicates a product not completely releasedto production. The specificationsare based on preliminary evaluations andare not guaranteed. Small quantities areavailable, and Silicon Systems should beconsulted for current information.III

IndexPage #Contents ................................................................................................................................................... IIIIndex ........................................................................................................................................................ IVNumerical Product Index ........................................................................................................................ VIIDiscontinued Parts List ........................................................................................................................... VIIProduct Selector Guide ......................................................................................................................... VIIISection 1. CUSTOM SOLUTIONS ................................................................................................................ 1-0Section 2. QUALITY ASSURANCE AND RELIABILITy ............................................................................. 2-0Section 3.Section 4.NEWSection 5.Section 6.K-SERIES SINGLE-CHIP MODEM FAMILYK-Series Modem Family Introduction ...................................................................................................................... 3-073K212L Bell 212A/103 Single-Chip Modem ........................................................................................... 3-173K221 L CCITT V.22, V.21 Single-Chip Modem ................................................................................... 3-2573K222L V.22, V.21, Bell 212A Single-Chip Modem ............................................................................. 3-5173K222U Single-Chip Modem with UART .............................................................................................. 3-7773K224L V.22bislV.221V.21, Bell 212A1103 Single-Chip Modem ........................................................ 3-11773K302L Bell 212A, 103, 202 Single-Chip Modem .............................................................................. 3-14973K321 L CCITT V.23, V.21 Single-Chip Modem ................................................................................. 3-17773K322L CCID V.23, V.22, V.21 Single-Chip Modem ........................................................................ 3-20173K324L CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem ........................................ 3-229CONTROLLERS & SPECIAL MODEM PRODUCTS73D2248/234873M550/15501255073M291 0/291 OA73M2918/2918A73M223MNP5, V.42 bis Datacom Modem Device Set ......................................................................... .4-1Universal Asynchronous ReceiverlTransmitter with FIFOs .......................................................... *Microcontroller ........................................................................................................................ 4-11Plug and Play Microcontroller and UART (abridged data sheet) ............................................ 4-491200 Baud FSK Modem .......................................................................................................... 4-51ANALOG SIGNALLING & SWITCHING PRODUCTS75T2017ST202/20375T20475T2089/90/917ST98078A207PCM PRODUCTS78P23678P236178P236278P30078P304A78P7200Integrated DTMF Receiver ....................................................................................................... S-1SV Low-Power DTMF Receiver ................................................................................................ 5-9SV Low-Power Subscriber DTMF Receiver ............................................................................ 5-17DTMF Transceivers ................................................................................................................ 5-2SCall Progress Tone Detector ................................................................................................... 5-33MFR1 Receiver ....................................................................................................................... 5-39DS-3 Line Interface ............................................................................................................... : ....... *STS-1 Line Interface ..................................................................................................................... *34.368 Mbitls Line Interface ......................................................................................................... *T1/E1 Integrated Short-Haul Transceiver with Receive Jitter Attenuation ................................ 6-1Low-Power T1/E1 Integrated Short Haul Transceiver with Receive Jitter Attenuation ........... 6-17E3/DS-3 Line Interface with Receive Equalizer ...................................................................... 6-35* Data Sheet available upon request IV

Page #Section 7.NEWNEWNEWNEWNEWSection 8.LAN PRODUCTS780902780837378083927808392L780837778083787802250Ethernet Twisted-Pair Media Attachment Unit .......................................................................... 7-13V/5V PCMCIA Ethernet Combo ............................................................................................ 7 -15Ethernet Coaxial Transceiver .................................................................................................. 7 -59Low Power Ethernet Coaxial Transceiver ............................................................................... 7-711 OBase-T Ethernet Combo for Plug and Play ......................................................................... 7 -73Enhanced PCMCIA Ethernet Device ...................................................................................... 7-75155 Mbitls ATM Line Transceiver ........................................................................................... 7-77PROGRAMMABLE ELECTRONIC FILTERS(See Product Selector Guide, pg. IX, for a complete listing of filter products offered)32F8001/800232F800332F810132F812032F8130/813132F8144Low-Power Programmable Electronic Filter .............................................................................. 8-1Low-Power Programmable Electronic Filter ............................................................................ 8-13Low-Power Programmble Electronic Filter .............................................................................. 8-23Low-Power Programmable Electronic Filter ............................................................................ 8-33Low-Power Programmable Electronic Filter ............................................................................ 8-41Programmable Electronic Filter ............................................................................................... 8-49Section 9.APPLICATION NOTES AND GLOSSARYK-Series Application NotesK-Series General Application Notes ........................................................................................................................ 9-1- Setting DTMF Levels for 1200 Bitls K-Series Modems ........................................................................................ 9-5- SSI 73K212A High Speed Connect Sequence .................................................................................................... 9-6- V.22 & V.22bis Connect Sequences .................................................................................................................... 9-7- Remote Loop Handshake Sequence ................................................................................................................... 9-8- SSI 73K224L Retrain at 2400 bitls ....................................................................................................................... 9-9- 551 73K212, 73K222 Originate & Answer Handshake Sequences ................................ ; .................................. 9-10- SSI 73K224L Originate & Answer Handshake Sequences ................................................................................ 9-12- Troubleshooting the Modem Design ............................................................................. , ..... , .............................. 9-1478P236/2361 1236217200 Demo Board Application Note ....................................................................................... 9-17NEW 7808373 Technical Reference Guide ................................................................................................................... 9-27DTMF Receiver Application Guide ........................................................................................................................ 9-71GLOSSARY .......................................................................................................................................................... 9-85Voiceband Modem Standards Reference Chart .................................................................................................... 9-97Section 10.PACKAGING/ORDERING INFORMATIONPackaging Index ................................................................................................................................................ 10-0Small Form Factor Package Selector Guide ......................................................................................................... 10-1Plastic DIP 8, 14,16 and 18 Pins .......................................................................................................................... 10-4Plastic DIP 20, 22, 24 and 245 Pins ..................................................................................................................... 10-5Plastic DIP 28, 32 and 40 Pins .............................................................................................................................. 10-6Cerdip 8, 14, 16 and 18 Pins ................................................................................................................................. 10-7Cerdip 22, 24 and 28 Pins ..................................................................................................................................... 10-8Ouad (PLCC) 20 and 28 Leads ............................................................................................................................. 10-9Ouad (PLCC) 32 and 44 Leads ........................................................................................................................... 1 0-1 0Ouad (PLCC) 52 and 68 Leads ........................................................................................................................... 1 0-11Ouad Flatpack (OFP) 52, 100 Leads .................................................................................................................. 10-12Ouad Flatpack (QFP) 128 Leads ........................................................................................................................ 10-13Thin Quad Flatpack (TOFP) 32, 48 Leads .......................................................................................................... 10-14Thin Ouad Flatpack (TOFP) 64, 80 and 100 Leads ............................................................................................ 10-15Thin Ouad Flatpack (TQFP) 120 and 128 Leads ................................................................................................ 1 0-16Thin Ouad Flatpack (TOFP) 144 Leads .............................................................................................................. 10-17Very Thin Ouad Flatpack (VTOFP) 32, 48 and 64 Leads ................................................................................... 1 0-18Very Thin Ouad Flatpack (VTOFP) 100 Leads ................................................................................................... 1 0-19Very Thin Quad Flatpack (VTQFP) 120 Leads ................................................................................................... 10-20Ultra Thin Quad Flatpack (UVQFP) 64 and 100 Leads ....................................................................................... 10-21v

Page #Section 10.PACKAGING/ORDERING INFORMATION (continued)SON 8, 14 and 16 Leads ..................................................................................................................................... 1 0-22SOL 16, 18, 20, 24 and 28 Leads ....................................................................................................................... 1 0-23SOL 34 Leads ...................................... ' ........................................................................................................ 1 0-24SOW 32 Leads .............................................................................................................................................. 1 0-24SaM 36 Leads .............................................................................................................................................. 1 0-24SaM 44 Leads .............................................................................................................................................. 1 0-25VSOP 20, 24 Leads ............................................................................................................................................. 10-25VTSOP 16, 20 Leads .......................................................................................................................................... 1 0-26UTSOP 20, 36 Leads .......................................................................................................................................... 10-27Ordering Information ........................................................................................................................................... 1 0-28Section 11. SALES OFFICES/DISTRIBUTORS ............................................................................................ 11-1VI

Numerical IndexSSI Device Numbers Page # SSI Device Numbers Page #32FS001/8002 ....................................................................... 8-1 75T201 .................................................................................. 5-132FS003 .............................................................................. 8-13 75T202/203 ........................................................................... 5-932FS1 01 .............................................................................. 8-23 75T204 ................................................................................ 5-1732FS120 .............................................................................. 8-35 75T2089/90/91 .................................................................... 5-2532FS130/8131 ..................................................................... 8-43 75T980 ................................................................................ 5-3332FS144 .............................................................................. 8-51 78A207 ................................................................................ 5-3973K212L ................................................................................ 3-1 78P236 ......................................................................................*73K221 L .............................................................................. 3-25 78P2361 .................................................................................... *73K222L .............................................................................. 3-51 78P2362 .................................................................................... *73K222U ............................................................................. 3-77 78P300 .................................................................................. 6-173K224L ............................................................................ 3-117 78P304A .............................................................................. 6-17730224S/2348 ....................................................................... 4-1 78P7200 .............................................................................. 6-3573K302L ............................................................................ 3-149 7802250 .............................................................................. 7 -7773K321 L ............................................................................ 3-177 7808373 .............................................................................. 7-1573K322L ............................................................................ 3-201 7808377 .............................................................................. 7 -7373K324L ............................................................................ 3-229 7808378 .............................................................................. 7 -7573M223 ............................................................................... 4-51 7808392 .............................................................................. 7-5973M291 0/291 OA .................................................................. 4-11 780S392L ............................................................................ 7-7173M2918/2918A .................................................................. 4-49 780902 .................................................................................. 7-173M55011550/2550 ...................................................................**Oata Sheet available upon request.Discontinued Parts ListThe following parts are no longer supplied or supported by Silicon Systems.Part # Part #7302180 75T9577302240 75T9817302247F75T9827302404 78A093A/B7302420/2421 78P233A730246 78P2347302950 78P805073K212 (12V Version)78P806073K221 (12V Version) 780833073K222 (12V Version) 780836073K312L 780837073M21473M37673M450U1450/245073M650/1650VII

Communications Products Selector GuideDevice Number 8212 CCIlT CCITT CCIlT CCIlT Description Power Available8103 8202 V.21 V.23 V.22 V.22bis Supply PackagesK-SERIES SINGLE CHIP MODEM FAMILY551 73K212L X low power, integrated single-chip modem +5V 28 DIP, 28 PLCC551 73K2125L X 73K212L with serial interface only +5V 22 DIP551 73K221L X X low power, integrated single-chip modem +5V 22, 28 DIP, 28 PLCC551 73K2215L X X 73K221 L with serial interface only +5V 22 DIP551 73K222L X X X low power, integrated single-chip modem +5V 22, 28 DIP, 28 PLCC551 73K2225L X X X 73K222L with serial interface only +5V 22 DIP551 73K222U X X X 73K222L with 16C450 UART +5V 40 DIP, 44 PLCC551 73K224L X X X X Bell 212A1103, CCITT V.22bisN.221V.21 +5V 28 DIP, 28, 32 PLCC,551 73K2245L X X X X 73K224L with serial interface +5V 22 DIP52 QFP, 64 TQFP551 73K302L X X Bell 212A120211 03 +5V 28 DIP, 28 PLCC551 73K3025L X X Bell 212A1202/1 03; serial interface only +5V 22 DIP551 73K321L X X CCITT V.23N.21 +5V 28 DIP, 28 PLCC~ 551 73K321 5L X X 73K321 L with serial interface only +5V 22 DIP551 73K322L X X X CCITT V.23N.22N.21 +5V 28 DIP, 28 PLCCI551 73K3225L X X X 73K322L with serial interface only +5V 22 DIP551 73K324L B212 X X X X CCITT V.22bisN.22N.23N.21 +5V 28 DIP, 28, 32 PLCC,52 QFP, 64 TQFPIICONTROLLERS AND SPECIAL MODEM PRODUCTSII551 73D2248/2348 X X X modem device set wI AT, MNP +5V Various QFP & TQFPI551 73M223 1200 bitls modem IC, +5V 16 DIP, 16 50Lcompact HDX V.23 modem551 73M550 16C550 pin compatible UART +5V 40 DIP, 44 PLCC, 48 GTReceive and Transmit FIFOs551 73M1550 28-pin version of 73M550, +5V 28 DIP, PLCCfull UART in 28-pin package551 73M2550 28-pin version of 73M550 +5V 28 DIP, PLCCadds J.lPR5T function551 73M291 0/291 OA Microcontroller device +3V1+5V Various QFP & TQFP551 73M291812918A Plug & Play Microcontroller & UART +3.3V1+5V 100 QFPI

Communications Products Selector GuideDevice Number Circuit Function Features Power Available PackagesANALOG SIGNALLING AND SWITCHING PRODUCTSSSI751201 Integrated DTMF Receiver binary coded 2-of-8 output +12V 22 DIPSSI 75T202 Integrated DTMF Receiver low power, binary output +5V 18 DIPSSI 75T203 Integrated DTMF Receiver early detect, binary output +5V 18 DIPSSI75T204 Integrated DTMF Receiver low power, binary output +5V 14 DIP, 16 SOSSI7512089 Integrated DTMF Transceiver generator & receiver, IlP interface +5V 22 DIPSSI 75T2090 Integrated DTMF Transceiver like 75T2089 wI call progress detect +5V 22 DIPSSI 75T2091 Integrated DTMF Transceiver like 75T2090 wI early detect +5V 28 DIP, PLCCSSI 75T980 Imprecise Call Progress Detector energy detect in 305-640 Hz band, Teltone +5V 8 DIPSSI78A207 Integrated MF Receiver detects central office toll signals +5V 20 DIPPCM PRODUCTSSSI78P236 DS-3 Line Interface T3 clock & data recovery, transmit equalization +5V 28 DIP, PLCCSS1781'2361 STS-1 Line Interface Transceiver STS-1 clock & data recovery, transmit equalization +5V 28 DIP, PLCCSSI 78P2362 CEPT E-3 Line Interface Transceiver E3 clock & data recovery, transmit equalization +5V 28 DIP, PLCCx SSI 78P300 T1/E1 Short Haul Transceiver receive jitter attenuation +5V 28 DIP, PLCCSSI78P304A Low-Power 38P300 receive jitter attenuation +5V 28 DIP, PLCC5S178P7200 DS-3/E3 Line Interface Transceiver DS-3/E3 transceiver wlreceive equalization +5V 28 DIP, PLCC& higher transmitter driveLAN PRODUCTSSSI78Q902 10BaseT MAU Transceiver direct interface to twisted pair and AUI +5V 28 DIP, PLCC5S178Q2250 ISS Mbitls ATM Transceiver for NRZ on-chip clock/data recovery +5V 48 TQFPISSI78Q8373 Single-chip Ethernet IC for PCMClA on-chip PCMCIA bus logic, 1 OBaseT Transceiver 3V or 5V 100 TQFP5S178Q8377 Single-chip Ethernet for ISAlPnP on-chip Plug & Play logic, 1 OBaseT transceiver +5V 128 QFP5S178Q8378 Single-chip Ethernet for PCMCIA on-chip PCMCIA multi-function logic 3V or 5V 100 TQFPSSI78Q8392 802.3 Coax Transceiver pin-compatible w/NSC 8392 -9V 16 DIP, 28 PLCCSSI 78Q8392L Low-power Coax Transceiver pin-compatible w/NSC 8392 -9V 16 DIP, 28 PLCC

Communications Products Selector GuideDevice Number Circuit Function FeaturesPROGRAMMABLE FILTERS551 32FB001/B002 Low Power Prog. Elect. Filter 7-Pole Equiripple Active Filter, Prog. Ic IPulse Slimming, 9 - 27 MHz (B001), 6-1B MHz (B002)551 32FB003 Prog. Electronic Filter 7-Pole Equiripple Active Filter, Prog. Ic IPulse Slimming,S - 13 MHz551 32FB011/B012 Prog. Electronic Filter 7-Pole Bessel Active Filter, Prog. Ic IPulse Slimming, (5 - 13 MHz, B011) (6-15 MHz, B012)S51 32FB020lB022 Low Power Prog. Elect. Filter 7-Pole Equiripple Active Filter, Prog. Ic IPulse Slimming, 1.5 - B MHzS51 32FB030 Prog. Electronic Filter 7-Pole.Equiripple Active Filter, Prog. Ic /Pulse Slimming, 250 kHz - 2.5 MHzSSI32F8101/02/03/04 Low Power Dgtl. Prog. Filter (8101/02/03) - 8001/02103 w/Serial Port & DACs, 95 mW, (8004) - Similar to 8103, Ic range 3-9 MHz551 32FB120 Low Power Dgtl. Prog. Filter 32FB020 with serial port and DACs5S132FB130/31 Low Power Dgtl. Prog. Filter 32FB030 with serial port and DACs / 32FB131 = 150 kHz < Ic < 1.5 MHz551 32FB144 Low Power Dgtl. Prog. Filter 2 zerol7-pole linear phase filter, 7-bit serial shift register, 7-27 MHz---- - - - - - - ->

Section 1CUSTOMSOLUTIONSI

1-0

CUSTOM SOLUTIONSSILICON SYSTEMS LEADS THE WAYDEVELOPING MIXED-SIGNAL CUSTOMPRODUCTS.This is a story about leadership. Silicon Systems is dedicatedto taking the point in the creation of high-performance,application-specific custom, mixed-signal integrated circuits(MSICs®).Such dedication means we bring a lot to the party. Includingtruly innovative analog, digital, and mixed analog/digitalICs. A full complement of mixed-signal CMOS, BiCMOS andBipolar waferfabrication processes, state-of-the-art automateddesign tools, production, assembly, test, and QA capability.No one's more experiencedMorethan 20 years of successfullC design work makes usthe most experienced engineering team in the MSICs field. Addit all up and you get a company that saves you time and moneywhile delivering you the most sophisticated mixed-signal customICs you can get.Faster to market for mixed-signal applicationsWhatever your mixed-signal design application, SiliconSystems gives you a competitive advantage. In communica- 1tions, disk drives, other storage products, automotive controlsystems, or other analog/digital sig nal processing applications,you can depend on our technical know-how to do the job rightand turn your design around faster.CMOS. Bipolar. BiCMOS. Analog. Digital.We've done itOur designers are an experienced bunch. They're uniquelyable to take a look at your specific application problem andmove quickly to the right IC solution.Our team is particularly adept at identifying key issuessuch as power, cost and performance trade-offs. So we cangear our efforts toward delivering you an optimized solution,manufactured with the appropriate fab process.... , .'".>.I.·>,~,,·.., ..,....,.., ....I.IA.,Application.... SiliconSystems·Desiglled·.Exal1lplesCMOS Analog Processing For analog continuous time, sampled data • Complete single-chip 2400 bit/s modem(switched-capacitor implementation), and 14.4 kbps modem chip sethigh-current power transistor applications. • Direct-broadcast satellite descramblerlow power, high density capability also • Servo and spindle motor controllers with 1.0supports inclusion of ROMs, RAMs, and Amp motor interfacesother analog/digital subsystems.• High-resolution analog data acquisition• Cellular baseband processorBiCMOS Signal Processing For high-performance, low noise, • Sub 1 nV/'

CUSTOM SOLUTIONSThe right mix of analog and digitalProviding total analog/digital systems on a chip allows youto meet your cost and performance objectives whether you'redesigning the next generation of communication, computerperipheral, or industrial control systems.We've turned to CMOS to effectively implement lowpower,highly integrated systems solutions for everything frommodems and cellular phones to hard disk drive controllers anddigital signal processors.We've gone the BiCMOS route to meet the high-performanceneeds of products like wideband transceivers, wirelessIF modems, RIW amplifiers, low-noise amplifiers, pulse detectors,high-speed data separators and high-performance, lowpowercombo devices.SOPHIST/CA TED TOOLS FORSTRUCTURED CUSTOM DESIGNAt each of six design centers capable of worldwide service- Tustin, San Jose and Nevada City, California; Longmont,Colorado; Tokyo and Singapore - Silicon Systems employsPEGASYS, any internal design automation system developedfrom carefully s~lected vendor tools and our own proprietarysoftware. Using Mentor Graphics workstations of both electricaland physical design, PEGASYS helps create complex designswhile significantly reducing schedules, costs and errors.By integrating third-party tools and custom software, we'rebetter able to design and analyze mixed-signal integratedcircuits in all CMOS, Bipolar and BiCMOS technologies. It's anapproach that has given us the edge in mixed-signal design andhelped put Silicon Systems' customers in a favorable positionin the marketplace.Dracula'I• Product and companynames are trademarks oftheir respective companiesExtraction'"I~-'DRC D~'I~IICrules'Dracula'Hspice'PEGASYS Design System1-2

CUSTOM SOLUTIONSSpecffically, PEGASYS brings the following to each design:• Fully integrated design environment• Methodology for precision circuit design• Integrated electrical and physical design• Unique blend of full-custom and automated layouttechniques• Complete layout verification• Full mixed-signal parasitic extractionOur design automation staff integrates the third-party toolsand optimizes their use on the Mentor platform. This frameworkcan easily accommodate new tools when needed, and itenables us to support a combination of analog and digitaldesign techniques in all CMOS, Bipolar and BiCMOS chipdesigns. By mixing design methodologies, we can achieveoptimum systems performance, even when schedules aretight.Electrical designA single CAE (computer aided engineering) environmentprovides for schematic capture, synthesis, simulation, and fauttgrading. We support this software with extensive libraries ofpre-designed cells and components. Highly specialized cells orcomponents can be designed and enhanced where required.We simulate each circuit to meet precise performance specificationsusing:• Analog circuit simUlation• Digital logic simulation• VHDL simulation• Mixed-mode simulation• Switched-capacitor filter simulation• Analog and mixed-mode behavioral simulationAdmittedly, simulation alone is not the key to perfectingperformance. That's why we work aggressively to refine ourunderstanding of models to make them work with simulation.Inside our progressive device modeling and characterization(DMC) laboratory, we develop accurate circuit simulation modelsand parameters. The DMC lab provides complete devicemodel data for our processes using capabilities such as ACmeasurement, statistical analysis and worst-case modeling.Accurate models are a cornerstone of our design-for-qualityapproach.To ensure high quality test vectors, production test vectorsare derived from simulation vectors using the TSSI tools earlyin the design process. The industry-standard Zycad fault simulatoris then used to determine fault coverage.Physical designOur PEGASYS layout system aids the mask designerthrough all physical design phases, ensuring consistencythroughout the design cycle. This flexible, fully integratedenvironment supports a broad range of layout techniques, fromfull-custom to full-automation.Capabilities include:• Chip floor planning• Analog device generators• Schematic driven layo .... t• On-line point-to-point routing• Compaction• Automatic place and route• Support of custom cells, standard cells, and compiledblocks in any combination• Design rule checking (drc)• Layout-versus-schematic verification (Ivs)• Parasitic extraction/back annotation• Output in industry standard GDS formatIn the first generation Pegasys system, Silicon Systemspioneered a device-generator based approach to precisionanalog layout. In partnership with Mentor Graphics, we haveenhanced this technique for our current system, based onMentor Graphics va ICstation® tools. ICstation® provides tremendousflexibility, combined with ease of customization, tofully support analog and mixed-signal designs. A variety oflayout styles and techniques are combined to meet each chip'sspecific requirements. Rigorous verification checks ensure thequality and accuracy of the layout, for both physical and electricalproperties. Post-layout simulation uses true parasitic modelingto handle remaining problems before first silicon fabrication.STATE OF THE ART CMOS DIGITAL ANDANALOG PROCESSESSilicon Systems offers four proven CMOS process technologiesfor creating cost effective, highly integrated systems solutions.These processes combine small geometry digital circuitcapability with high performance analog capability. Table 1 summarizesSilicon Systems' CMOS process capabilities.Our newest CK process is designed to support highbreakdown, high current power FETs, 15V NPNs for specializedanalog needs, poly capacitors and resistors, low noisedifferential amplifiers and high performance A/D and D/A converters.It also includes highly optimized and silicon areaefficient digital cells including DSPs, microcontrollers,sequencers, memory managers and data paths.The CJ process provides high performance analog anddigital cells and includes the same analog and digital complexdevices in our CK process.Our CG process supports high-performance analog circuitrywith precision poly-poly capacitors. Complex analogcircuitry includes 1.25 Amp power FETs, 12-bit switched capacitoranalog to digital converters and low distortion operationalamplifiers and filters. Complex digital circuitry includesDSPs, microcontrollers, sequencers, memory mangers anddata paths.I1-3

CUSTOM SOLUTIONSBIPOLAR & BICMOS PROCESSTECHNOLOGIESOur bipolar MSICs take advantage of a high-performanceBipolar process, BN (for 5V applications).BN - Low-powerl 8 GHz Bipolar at 5 voltsBecause we employ full oxide isolation in our BN process,we can fabricate very fast, very small transistors and reducesidewall capacitances. This supports not only high speed, butlow power.The BN process features high-performance NPN transistorsto support mixing high-performance emitter coupled logic(ECL) with analog circuitry. To provide for strict TTL I/Ocompatibility,we use superior PtSi Schottky diodes.The resulting speed and packing density allows you toeffectively implement dense high-performance, low-powerBipolar analog/digital capability into your system designs.For a feature-by-feature comparison of Silicon Systems'BN Bipolar process, see Table 3.BiCMOS process technologiesOur BiCMOS process portfolio is expanding to support theevolving demands of the mixed-signal IC market. Now inproduction is our BCA process which combines 13 GHz NPNswith 1.01l CMOS features to support the design of efficient, highperformance, mixed-signal circuits. High bandwidth analogcircuits can be combined with dense digital logic to support thedevelopment of 5V data channels with transfer rates into the120+ MbiVs range, while maintaining low power consumption.The BCA technology has also allowed our designers to develop3V only circuits to address very low power applications.Our second generation BiCMOS process, BCB, will providethe next step in performance with a parallel improvementin circuit density. BCB advances our BiCMOS with o.all CMOSfeature sizes and improved interconnect capability resulting ina significant performance step for CMOS logic. This will allowimplementation of mixed-signal circuits that support data transferrates well beyond 200 MbiVs, while maintaining very lowpower dissipation. The dense digital advantages of BCB willalso expand the possibilities for cost effective customizationand programmability in both 5V and 3V environments.For a summary of our BiCMOS processes see Table 2.1-4

CUSTOM SOLUTIONS............. I ......! .....'''''''''.;I;;,.. ... .Application Gate·· ... Interconnect PitchesI H'-> ............ ........ Voltage BVDSS Length Poly 1 Metal 1 Metal· 2 FeaturesCG Si-Gate, dual metal, 5V 7V 1.511 3.011 4.511 6.011 • DDD SID structuredual poly, PWell• Poly-poly capacitors• Shrinkable to 1.211CJ Si-Gate, dual metal, 5V 7V 1.011 2.011 3.011 3.311 • Ldd SID structuredual poly, NWell• Poly-poly capacitors• Shrinkable to O.SI1ICK Si-Gate, dual metal, 5V 7V O.SI1 1.611 2.011 2.411 • Ldd SID structuredual poly, NWell• Poly-poly capacitors• Shrinkable to 0.511• High voltage FETs• 15V NPNs.? ...... ....... ..> ..DrawnTABLE 1: CMOS Process Chart··>< A i...........Gate Interconnect Pitches.-~':"~~ .,.< .....••.. lf~. ·tS~U~~ Length Poly IMO M1 M2 BV CEO NPNFt Emitter FeaturesBCA: 5V 10V 1.011 2.611 3.211 3.SI1 5.011 SV 13 GHz 1.011 Bipolar:• High Periormance NPNs• Polysilicon emitters• PtSi Schottky Diodes• Poly resistersBCB: 5V SV O.SI1 1.611 2.411 2.011 2.411 SV 15 GHz O.SI1 • Gate Oxide Capacitors• Poly Capacitors• Sidewall Oxide Isolation• FusesCMOS:• Lightly Doped Drains> ...............TABLE 2: BiCMOS Process ChartEmitter M1 M2t'TOC855. aVD.,>

CUSTOM SOLUTIONSA SUPERIOR FINISH FOR CMOS, BIPOLARANDBICMOSYou might say this is the payoff window. The benefits of ourprocess technologies, design tools and our unique customapproach all come together during wafer fabrication, test andassembly.Our two manufacturing centers, located in Tustin andSanta Cruz, California, can offer specialized capabilities tomatch your particular fabrication requirements. Both facilitiesprovide you with high resolution stepper photolithography technology,positive resist, dry plasma etch systems, high currention implantation and automatic sputtering.Fabrication sites in both Tustin and Santa Cruz accommodate4- and 6-inch waferfabrication and Bipolar, CMOS and BiCMOSprocesses.The right packageSilicon Systems offers a wide range of packages to meetthe small footprint requirements of advanced storage andcommunication products. We continue to be innovative insurface mount technology by providing PLCC, SO, VSOP,VTSOP, OFP, TOFP, VTOFP and UTOFP packages. At ourISO 9002-certified Singapore assembly & test facility we havethe full capability to support high quality automated packagingwhile also maintaining rapid cycle times.Promls. Quality through CAMProcess and Management Information System (PROM IS)underscores our commitment to computer-aided manufacturing(CAM). And to delivering you a superior quality product ontime.We use PROM IS to facilitate the data required in ourmanufacturing, monitoring and statistical process control (SPC)systems.With PROMIS we more effectively manage our inventory,accurately track wafers in process, and closely monitor theclean room environment.PROMIS also assists our SPC efforts, as does ourcommitmentto fully train all of our manufacturing personnel in SPCbasics.We design for qualityIt's our view that quality is nothing less than absolutecustomer satisfaction. To achieve it, we begin far "upstream" inthe product development process. Our design-for-qualityapproach scrutinizes the design itself with statistically basedmodels, comprehensive simulation tools and vigorous designreviews.The results of such an effort are IC products that boastlower defect rates, higher parametric performance and farfewer redesigns. Moreover, our persistence in improving qualitykeeps us focused on finding better and faster ways to satisfyfuture customer demands.Quality that deliversWith effective systems such as PROMIS and our designfor-qualityapproach in place, Silicon Systems is prepared todeliver you finished products you can really depend on. Ontime. And within budget.For details on how you can take best advantage of SiliconSystems' custom mixed-signal IC solutions, see your nearestSilicon Systems representative, or contact us. Silicon Systems, Inc.14351 Myford Road, Tustin, CA 92680-7022. 714-573-6000.FAX: (714) 573-6914.Rnal Design ReviewEvaluate PrototypeDesign Components• Schematic Capture• Simulation• Netlisting• Automatic Placingand Routing orHand-Packed Layout• Automatic CircunTraceTest Program CreationPhotomaskWaferFabPrototype(Assembly, Test, Ship)Customer Interface for Full-Customand Cell-Based Designs1-6

Section 2RELIABILITY &QUALITY ASSURANCE•2

CONTINUOUS IMPROVEMENTMISSION ~ OBJECTIVE STATEMENTMissionBe the supplier of choice by exceeding customerexpectations through continuous improvements in ourproducts, systems and services.ObjectivesProvide world class quality in our products and servicesthrough focus on:Customer PartneringCycle Time ImprovementProcess and System ImprovementsDevelop a culture that ensures the consistent use ofcontinuous improvement tools and fact based decisionmethodology by:Senior Management LeadershipEmployee EmpowermentAggressive Goal Setting and Performance MeasurementCommunication and Celebration of Successes2-0

Reliability andQuality AssuranceSECTION 11.1 INTRODUCTIONSilicon Systems is committed to the goal of customer satisfactionthrough the on-time delivery of defect free productsthat exceed the customer's expectations and requirements.This section outlines Silicon Systems' ongoing activities forthe control and continual improvement of quality in everyaspect of our organization.Silicon Systems is diligently working to maintain and improveits position as a world-class provider of mixed-signal integratedcircuits (MSICs®).We realize and practice the concept that quality and reliabilitymust be designed and built into our products. In addition,Silicon Systems utilizes rigid inspections and data analysis toevaluate the acceptability and variation existing in incomingmaterials and performs stringent outgoing quality verification.The manufacturing process flow is encompassed by aneffective system of test/inspection checks and in-line monitorswhich focus on the control and reduction of processvariation. These gates and monitors ensure precise adherenceto prescribed standards and procedures.Silicon Systems also incorporates the use of statistical processcontrol techniques into company operations. The controland reduction of the process variation by the use ofstatistical problem solving techniques, analytical controlsand other quantitative methods ensures that Silicon Systems'products maintain the highest levels of quality and reliability.Our Reliability and Quality Assurance organizations arecommitted to working closely with our customers to provideassistance and a continually improving level of product quality.1.2 SILICON SYSTEMS' QUALITY MANDATE:CONTINUOUS IMPROVEMENTContinuous improvement is Silicon System's strategic thrustfor the 1990's. In order to ensure that all aspects of ourbusiness are encompassed by this mandate, CorporateReliability & Quality Assurance has been chartered with theresponsibility for developing, educating and overseeing theworldwide continuous improvement process. The continuousimprovement initiative will lead to developing a neworganizational culture, changing attitudes and stronger ownershipand accountability for total customer satisfaction.1.3 CHARACTERISTICS OF SILICON SYSTEMS'CONTINUOUS IMPROVEMENT PROCESSExecutive Steering Committee leadership and direction- defines the right things to do and providesguidance - the right way to do them.Continuous improvement is measured everywhere andby everyone. Metrics that reflect pride in accomplishmentare celebrated.Benchmarking is employed as a method to shortenlearning curves and ensure successful ventures.Quality management and employee empowerment areencouraged at all levels.I~ -1'--_.Si.".9"".0.re_ .• F.A. Lab ..FIGURE 1: Organizational Chart2-1

Reliability andQuality AssuranceSupplier partnership is a critical element of our qualitystrategy.This is the essence of Silicon Systems - a total qualityinvolved company -forward looking and immersed in the goalof customer satisfaction and best-in-class business pursuits.1.4 CORPORATE RELIABILITY ANDQUALITY ASSURANCEIt is the objective of the Corporate Reliability and QualityAssurance organization to ensure that proactive qualitysystems are in place to ensure that Silicon Systems' productswill meet or exceed customer requirements and expectations.In addition, the Reliability and Quality Assuranceorganization works to facilitate the timely implementation ofsolutions and monitors the effectiveness of corrective actions.These organizational strategies support the continuingenhancement of quality consciousness throughout SiliconSystems.1.5 ISO 9000 CERTIFICATIONSilicon Systems has determined that ISO 9000 certificationis an important strategy for achieving total customer satisfaction.Our Singapore assembly and test operations facility hasbeen ISO 9002 certified through. SISIR and our domesticfacilities' quality systems have been ISO 9001 certifiedthrough Intertek. We believe strongly that ISO 9000certification proves that Silicon Systems is doing the rightthings to do things right.SECTION 2: QUALITY ASSURANCE2.1 QUALITY OBJECTIVESWhile all Silicon Systems employees have direct responsibilityfor quality in theirfunctions, the Quality Assurance Organizationshave the ultimate responsibility for the reliable performanceof our products. This is accomplished through thedevelopment, administration and assessment offormal qualitysystems which assure Silicon Systems' management, aswell as our customers, that products will fulfill the requirementsof customer purchase orders and all other specifications.Corporate Quality Assurance supports, coordinates and activelyparticipates in the formal qualification of suppliers,material, processes, and products, and the administration ofquality systems to assure that our products meet SiliconSystems quality standards. Product Quality Assurance providesthe liaison between Silicon Systems and the customerfor all product quality related concerns. Manufacturing QualityAssurance administers the manufacturing quality systemsand reports quality monitor data to the factory.It is the practice of Silicon Systems to have corporate qualityand reliability objectives encompass all of its activities. Thisstarts with a strong commitmentof support from the corporatelevel and continues with exceptional customer support longafter the product has been shipped.Silicon Systems emphasizes the belief that quality and reliabilitymust be built into all of its products by ensuring that allemployees are educated in the quality philosophy of thecompany. Some of the features built into Silicon Systemsquality culture include:1. Structured training programs directed at wafer fabrication,test, process control personnel and supportingorganizations.- Team-based problem solving methodologies.- Corporate-wide training of quality philosophy andstatistical methods.2. Stringent in-process inspections, gates, and monitors.3. Rigorous evaluation of designs, materials, and processingprocedures.4. Stringent electrical testing (100% and QC AQUSampietesting).5. Ongoing reliability monitors and process verifications.6. Real-time use of statistical process controlmethodology.7. Corporate level audits of manufacturing, subcontractors,and suppliers.8. Timely corrective action system.9. Control of non-conforming material.These focused quality methods result in products whichdeliver superior performance and reliability in the field.2.2.1 INCOMING INSPECTIONSIncoming inspection plays a key role in Silicon Systems'quality efforts. Small variations in incoming material cantraverse the entire production cycle before being detectedmuch later in the process. By paying strict attention to themonitoring of materials at the earliest possible stage, variationcan be reduced, resulting in a stable uniform process.2.2.2 IN-PROCESS INSPECTIONSSilicon Systems has established key inspection monitors inthe following strategic areas: wafer fabrication, wafer probe,assembly, and final test.Quality control monitors have been integrated throughout themanufacturing flow, so that data may be collected and analyzedto verify the results of intermediary manufacturingsteps. This data is used to document quality trends or longterm improvements in the quality of specific operations.2-2

Reliability andQuality AssuranceFIGURE 2Quality Assurance RelationshipsQuality Steering CommitteeAbnormality control is being used to enhance the effectivenessof this process. In process monitors such as oxideintegrity, electromigration immunity and other parametersmonitor long term reliability as well as circuit performance.2.3 QUALITY STEERING COMMITTEEThe Corporate, Product and Manufacturing Quality Assuranceorganizations work closely together to provide leadershipin the development, integration and assessment ofSilicon Systems' worldwide quality systems and procedures.This team approach ensures that policies and procedures arestandardized and facilitates rapid improvement in products,processes and services.2.4 DESIGN FOR QUALITYSince the foundation of a reliable product is rooted in thedesign process, the Reliability and Quality Assurance organizationsactively participate in comprehensive cross-functionalreviews of design stages priorto the product's transitionto production status. These review stages assure a predictableand effective development cycle. Other important de-sign-related functions include ensuring that process specificationrevisions are translated into updated design parametersand the translation of manufacturing process capabilityinto design guidelines. This is accomplished through theidentification and monitoring of critical process and deviceparameters. Wafer level test at the early stages of processdevelopment also plays a critical role. These elements, includedin Silicon Systems design for quality effort, support thedevelopment of robust design rules which are as insensitiveas possible to inherent manufacturing variation. The result isa product that delivers predictable and reliable long termperformance.2.5 PPM REDUCTION PROGRAMThe primary purpose of a PPM reduction program is toprovide a formalized feedback system in which data fromnonconforming products can be used to improve futureproduct consistency and reliability. The action portion of thisprogram is accomplished in three stages:1. Identification of defects by failure mode.2. Identification of defect causes and initiation of correctiveaction.3. Measurement of results and setting of improved goals.The data summarized from the established PPM program iscompiled as a ratio of units rejectedltested. This ratio is thenexpressed in terms of defective parts per million (PPM).Founded on a statistically valid database of PPM data and anestablished five-year strategic plan identifying PPM improvementgoals, Silicon Systems has consistently achieved excellentquality standards and will continue to progressivelyimprove PPM standards.2.6 COMPUTER AIDED MANUFACTURING CONTROLComputer Aided Manufacturing (CAM) is used throughoutSilicon Systems for the identification, control, collection anddissemination of timely information for logistics control. SiliconSystems also uses this type of computerized system forstatistical process control and manufacturing monitoring.PROMIS, (PROcess Management and Information System),displays approved/controlled recipes, processes, and procedures;tracks work-in-process; reports accu\ate inventoryinformation; allows continuous recording of facilities data;contains statistical analysis capabilities; and much more.PROMIS allows for a paperless facility, a major element inminimizing contamination of clean room areas.I2-3

Reliability andQuality AssuranceTEST CONDITIONS PURPOSE OF EVALUATIONBiased temperature/humidity 85°C/85° %RH Resistance to high humidity with biasHighly accelerated stress test (HAST) JDEC A110 Evaluates package integrityHigh temperature operating life (HTOL) Mil 883D, Method 1005 Resistance to electrical and thermal stressEarly Failure Rate Mil 883D, Method 1005 Detect infant mortalitySteam pressure 121°C/15PSI Resistance to hiQh humidityTemperature cycling Mil 883D, Method 1010 Resistance to thermal excursion (air)Thermal shock Mil 883D, Method 1011 Resistance to thermal excursion (liquid)Salt atmosphere Mil 883D, Method 1009 Resistance to corrosive environmentConstant acceleration Mil 883D, Method 2001 Resistance to constant accelerationMechanical shock Mil 883D, Method 2002 Resistance to mechanical shocksSolderability Mil 883D, Method 2003 Evaluates solderability of leadsLead integrity Mil 883D, Method 2004 Evaluates lead int~grity before board assembly_Vibration, variable frequency Mil 883D, Method 2007 Resistance to vibrationThermal resistance Silicon Systems Method Evaluates thermal dissi~ationElectrostatic damage Mil 883D, Method 3015 Evaluates ESD susceptabilityLatch-up Silicon Systems Method Evaluates latch-up susceptibilitySeal fine and gross leak Mil Std 883D, Method 1014 Evaluates hermeticity of sealed packagesTABLE 1: Reliability Stress TestsSECTION 3: RELIABILITY3.1 RELIABILITY PROGRAMA primary objective at Silicon Systems is to improve thereliability of our products through characterization of ourmanufacturing operations. The identification of specific failuremechanisms occuring in the wafer fabrication and assemblyprocesses is a prerequisite to effective corrective actionaimed at reducing defects and improving quality and reliability.Silicon Systems has defined various programs that willcharacterize product reliability levels on a continuous basis.These programs can be categorically described by:1 . Qualifications2. Production monitors3. Evaluations4. Failure analysis5. Wafer level reliability6. Data collection and presentation for improvementprojects3.2 QUALIFICATIONSExtensive qualification testing and data collection ensuresthat all new product designs, processes, and packagingconfigurations meet the absolute maximum ratings of designand the worst case performance criteria for end users. A largedatabase generated by means of accelerated stress testingresults in a high degree of confidence in predicting final useperformance. The qualification criteria used are periodicallyreviewed to be consistent with Silicon Systems' increasingquality and reliability goals in support of our customers.3.3 PRODUCTION MONITORSThis program has been established to randomly select astatistically significant sample of production products forsubjection to maximum stress test levels in order to evaluatethe useful life of the product in a field use environment.Table 1 lists reliability test methods that are in use at SiliconSystems. This analysis of production monitor at SiliconSystems provides valuable information on possible design/process changes which assure continued improved reliability.The monitors are periodically reviewed for effectiveness andimprovements.3.4 EVALUATIONSThe evaluation program at Silicon Systems is an ongoingeffort that defines standards which address the reliabilityassessment of the circuit design, process parameters, andpackage of a new product. This program continuously analyzesupdated performance characteristics of product as theyundergo improvement efforts at Silicon Systems.2-4

Reliability andQuality Assurance3.5 FAILURE ANALYSISThe failure analysis function is an integral part of the Qualityand Reliability department at Silicon Systems. Silicon Systemshas assembled a highly technical and sophisticatedfailure analysis laboratory and staff. This laboratory providesvisual analysis, electrical reject mode analysis, and bothdestructive and non-destructive data to aid the engineers indeveloping corrective action for improvement. These testanalyses may include metallurgical, optical, chemical, electrical,SEM with X-ray dispersive analysis, and E-Beam noncontactanalysis as needed.These conclusive in-house testing and analysis techniques,are complemented by outside support, such as scanningacoustic microscopy, focused ion beam, and complete surfaceand material analysis. This allows Silicon Systems tomonitor all aspects of product manufacturing to ensure thatthe product of highest quality is shipped to our customers.3.6 WAFER LEVEL RELIABILITY PROGRAMThe primary advantage of wafer level reliability testing is thespeed at which results can be derived, thereby providingadditional response time and an early warning of processchanges. This tool provides Silicon Systems with a very rapidanalysis tool which allows for the early identification ofpossible problems and a determination of their origin.The continuous improvement approach taken at SiliconSystems uses wafer level reliability tests as tools to improvethe process, identify potential problems, determine the sourcesof any process weakness and eliminate problems upstreamin the process. This results in a focus on reliability improvementthatgoes well beyond merely determining the projectedlifetime of a product to a detailed characterization, measurementand control of the specific parameters which actuaillydetermine product lifetime.3.7 DATA COLLECTION AND PRESENTATION FORIMPROVEMENT PROJECTSData collected from each element of the Reliability programis summarized for scope and impact and distributed amongall engineering disciplines in the company. This data facilitatesimprovement and provides our customers an opportunityto review the performance of our product.3.8 RELIABILITY METHODSThe Reliability Program utilizes a number of stress tests thatare presently being used to define performance levels of ourproducts. Many of these stress tests are per MIL-STD-883Das shown in Table 1.3.9 RELIABILITY PREDICTION METHODOLOGYAt Silicon Systems, the Arrhenius model is used to relate afailure rate at an accelerated temperature test condition to anormal use temperature condition.The model basically states FR = A exp(-Ea/KT)Where:FRAEaKTSECTION 4:Failure rateConstantActivation Energy (eV)4.1 ESD PREVENTIONBoltzmann's constant 8.62 x 10- 5 eVI degree KAbsolute temperature (degree K)ELECTROSTATIC DISCHARGEPROGRAMSilicon Systems recognizes that the protection of ElectrostaticDischarge (ESD) sensitive devices from damage byelectrical transients and static electricity is vital. ESD safeprocedures are incorporated throughout all operations whichcome in contact with these devices. Continuous improvementin the ESD protection levels is being accomplishedthrough the incorporation of increasingly robust protectiondevices during the circuit design process as well as work areaimprovements_Silicon Systems' quality activity incorporates several protectionmeasures forthe control of ESD. Some of the preventivemeasures include handling of parts at static safe-guardedworkstations, the wearing of wrist straps dudng all handlingoperations, the use of conductive lab coats in all test areasand all areas which handle parts and the packaging ofcomponents in conductive or anti-static containers.•2-5

NOTES2-6

Section 3K-SERIESSINGLE-CHIPMODEM FAMILYI3

IntroductionSilicon Systems' K-Series Family of One-Chip ModemsSilicon Systems is a leader in the design and manufacturingof CMOS VLSI modems. Currently, SiliconSystems offers the most extensive line of one-chipmodem ICs available, with high-performance, costeffectivedesigns suitable for a wide range of applications.Silicon Systems' fully compatible modem ICfamily has redefined the modem IC as a universalcomponent which can be easily integrated into anysystem. Designs can be upgraded to meet differentstandards and speeds by simply substituting one K­Series IC for another. Using a K-Series family modemIC in your application eliminates product obsolesence,and minimizes development costs.The Silicon Systems modem IC family consists of fourbasic products:1. The SSI 73K222L, a multi-mode device whichcombines both Bell 212AJ1 03 and V.22N.21 capabilityin one chip, with operating modes at 0 - 30,600 and 1200 bit/so2. The SSI 73K222U which combines the functionalityof the 73K222L with the industry standard16C450 UART.3. The SSI 73K224L, a major technological breakthroughwhich provides 2400 bit/s V.22bis operationin addition to V.22N.21 and Bell 212AJ103modes in a single IC.4. The SSI 73K322L provides CCID V.22N.21 plusV.23 Videotex modes.addition, an innovative bus structure makes a separatecontroller unnecessary in dedicated integral designs.All K-Series devices are available in low-power versions.This feature allows optimal performance withsingle +5V supply operation and is unique to SiliconSystems' products.Silicon Systems' single-chip modem IC family isdesigned to be the most effective solution for a widevariety of modem applications. The products providefor a full range of communications standards andspeeds up to 2400 bit/so Moreover, features can beextended to include additional modes and higheroperating speeds without impacting existing designs.Take advantage of these capabilities. Design fortomorrow's needs today by using Silicon Systems'K-Series modem IC family.K-Series Modem Design ManualThe Silicon Systems K-Series Modem Design Manualcontains a large body of application literature for theK-Series family of single chip modem products. Thismanual is intended as a tutorial for those users whomay be designing with modems for the first time, andalso as a helpful guide for more experienced modemdesigners.K·SERIESMODEMDESIGNMANUALNew additions to Silicon Systems' modem IC familyextend the available operating modes and providefeatures which greatly simplify integral modem design.The SSI 73K324L offers V.22bis, V.22N.21 and V.23operating modes on one chip. These products dramaticallyreduce external circuitry required for dedicatedintegral modem designs.Silicon Systems' one-chip modem IC products representtechnical achievements unmatched in the industry.An advanced Digital Signal Processor resides onthe same chip with sophisticated analog circuitry in theSSI 73K224L and SSI73K324L products. "U" versionsof the K-Series devices integrate an industry standardUART with full modem capability on a single chip. InThe K-Series Modem Design Manual is availablethrough our worldwide network of representatives anddistributors.3-0

SSI73K212LBell 212A/103Single-Chip ModemJanuary 1994DESCRIPTIONThe SSI 73K212L is a highly integrated single-chipmodem IC which provides the functions needed toconstruct a typical Bell 212A full-duplex modem.Using an advanced CMOS process that integratesanalog, digital and switched-capacitor filter functionson a single substrate, the SSI73K212L offers excellentperformance and a high level of functional integrationin a single 28-Lead PLCC, 28- or 22-pin 01 P configuration.The SSI 73K212L operates from a single +5Vsupply.The SSI 73K212L includes the OPSK and FSK modulator/demodulatorfunctions, call progress and handshaketone monitor test modes and a OTMF dialer.This device supports all Bell 212A modes of operationallowing both synchronous and asychronous communications.Test features such as analog loop, digital loop, andremote digitalloopback are provided. Internal patterngenerators are also included for self-testing. The SSI73K212L is designed to appear to the systems designeras a microprocessor peripheral, and will easilyinterface with popular one-chip microprocessorsFEATURESOne-chip Bell 212A and 103 standard compatiblemodem data pumpFull-duplex operation at 0-300 bitls (FSK) or1200 bitls (OPSK)Pin and software compatible with otherSSI K-Series 1-chip modemsInterfaces directly with standard microprocessors(8048, 80C51 typical)Serial or parallel microprocessor bus for controlSerial port for data transferBoth synchronous and asynchronous modes ofoperationCall progress, carrier, precise answer tone andlong loop detectorsOTMF generatorsTest modes available: ALB, OL, ROL, Mark, Space,Alternating bit patternsPrecise automatic gain control allows 45 dBdynamic rangeCMOS technology for low power consumptionusing 30 mW @ 5VSingle +5V supplyI(Continued)BLOCK DIAGRAMPIN DIAGRAMADf>-MJ7AD VIA 0---__ALE D--~os D--~RESETTXAClKXTl1XTl2ADOAD1AD2AD3GNDRXAVREFRESETISETRXClKRXDm 0------1AD4ADSTXD~D D-----------~RXD n--------------1AD6AD7EXClKALEINTWRTXARDVDDCAUTION: Use handling procedures necessaryfor a static sensitive component.0194 - rev.3-1

SSI73K212LBell 212A/1 03Single-Chip ModemDESCRIPTION (Continued)(80C51 typical) for control of modem functions throughits 8-bit multiplexed address/data bus or serial controlbus. An ALE control line simplifies address demultiplexing.Data communications occurs through a separateserial port only.The SSI73K212L is ideal for use in either free standingor integral system modem products where full-duplex1200 bit/s data communications over the 2-wireswitched telephone network is desired. Its high functionality,low power consumption and efficient packagingsimplify design requirements and increase systemreliability. A complete modem requires only the additionof the phone line interface, a control microprocessor,and RS-232 level convertor for a typical system.The SSI73K212L is part of SSi's K-Series family of pinand function compatible single-chip modem products.These devices allow systems to be configured forhigher speeds and Bell or CCITT operation with only asingle component change.OPERATIONASYNCHRONOUS MODEData transmission for the DPSK mode requires thatdata ultimately be transmitted in a synchronous fashion.The SSI 73K212L includes ASYNC/SYNC andSYNC/ASYNC converters which delete or insert stopbits in order to transmit data within a 0.01% rate. Inasynchronous mode the serial data comes from theTXD pin into the ASYNC/SYNC converter. TheASYNC/SYNC converter accepts the data provided onthe TXD pin which normally must be 1200 bitls + 1.0%,- 2.5%. The rate converterwill then insert or delete stopbits in orderto output a signal which is 1200 bitls ± .01 %(±.01% is the required synchronous data rateaccuracy).The serial data stream from the ASYNC/SYNC converteris passed through the data scrambler and ontothe analog modulator. The data scrambler can bebypassed under processor control when unscrambleddata must be transmitted. The ASYNC/SYNC rateconverter and the data scrambler are bypassed in allFSK modes. If serial input data contains a break signalthrough one character (including start and stop bits) thebreak will be extended to at least 2· N + 3 bits long(where N is the number of transmitted bits/character).Serial data from the demodulator is passed firstthrough the data descrambler and then through theSYNC/ASYNC rate converter. The SYNC/ASYNCconvertor will reinsert any deleted stop bits and transmitoutput data at an intra-character rate (bit-to-bittiming) of no greaterthan 1219 bit/so An incoming breaksignal (lOW through two characters) will be passedthrough without incorrectly inserting a stop bit.SYNCHRONOUS MODEThe Bell 212A standard defines synchronous operationonly at 1200 bitls. Operation is similar to that of theasynchronous mode except that data must be synchronizedto a provided clock and no variation in datatransfer rate is allowable. Serial input data appearing atTXD must be valid on the rising edge of TXCLK.TXCLK is an internally derived 1200 Hz Signal ininternal mode and is connected internally to theRXCLK pin in slave mode. Receive data at the RXD pinis clocked out on the falling edge of RXCLK. TheASYNCH/SYNCH converter is bypassed when synchronousmode is selected and data is transmitted outat the same rate as it is input.DPSK MODULATOR/DEMODULATORThe SSI 73K212L modulates a serial bit stream intodibit pairs that are represented by four possible phaseshifts as prescribed by the Bell 212A standard. Thebaseband signal is then filtered to reduce intersymbolinterference on the bandlimited 2-wire telephone line.Transmission occurs using either a 1200 Hz (originatemode) or 2400 Hz carrier (answer mode). Demodulationis the reverse of the modulation process, with theincoming analog signal eventually decoded into di-bitsand converted back to a serial bit stream. The demodulatoralso recovers the clock which was encoded intothe analog signal during modulation. Demodulationoccurs using either a 1200 Hz carrier (answer mode orALB originate mode) or a 2400 Hz carrier (originatemode or ALB answer mode). The SSI73K212L uses aphase locked loop coherent demodulation techniquefor optimum receiver performance.FSK MODULATOR/DEMODULATORThe FSK modulator produces a frequency modulatedanalog output signal using two discrete frequencies torepresent the binary data. In the Bell 1 03, the standardfrequencies of 1270 and 1070 Hz (originate, mark and3-2

SSI73K212LBell 212A/1 03Single-Chip Modemspace) or 2225 and 2025 Hz (answer, mark and space)are used. V.21 mode uses 980 and 1180 Hz (originate,mark and space) or 1650 and 1850 Hz (answer, markand space). Demodulation involves detecting the receivedfrequencies and decoding them into theappropriate binary value. The rate converter andscrambler/descrambler are bypassed in the 1 03 mode.PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and provide compromise delay equalizationand rejection of out-of-band signals in thereceive channel. Amplitude and phase equalizationare necessary to compensate for distortion of thetransmission line and to reduce intersymbol interferencein the bandlimited receive signal. The transmitsignal filtering approximates a 75% square root ofraised Cosine frequency response characteristic.AGCThe automatic gain control maintains a signal level atthe input to the demodulators which is constant towithin 1 dB. It corrects quickly for increases in signalwhich would cause clipping and provides a totalreceiver dynamic range of >45 dB.EXCLK. WR is then pulsed low and data transferredinto the selected register occurs on the rising edge ofWR.SPECIAL DETECT CIRCUITRYThe special detect circuitry monitors the receivedanalog Signal to determine status or presence of carrier,call-progress tones, answer tone and weak receivedsignal, (long loop condition). An unscrambledmark request signal is also detected when the receiveddata out oft he DPSK demodulator before the descrambierhas been highfor165.5ms±6.5ms minimum. Theappropriate detect register bit is set when one of theseconditions changes and an interrupt is generated for all 3purposes except long loop. The interrupts are disabled(masked) when the enable interrupt bit is set to O.DTMF GENERATORThe DTMF generator will output one of 16 standardtone pairs determined by a 4-bit binary value and TXDTMF mode bit previously loaded into the tone register.Tone generation is initiated when the DTMF modeis selected using the tone register and the transmitenable (CRO bit D1) is changed from 0 to 1.PARALLEL BUS INTERFACEFour 8-bit registers are provided for control, optionselect and status monitoring. These registers are addressedwith the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as four consecutive memory locations.Two control registers and the tone register areread/write memory. The status detect register is readonly and cannot be modified except by modemresponse to monitored parameters.SERIAL COMMAND INTERFACEThe serial command mode allows access to theSSI 73K212L control and status registers via a serialcommand port (22-pin version only). In this mode theAO, A 1 and A21ines provide register addresses for datapassed through the data pin under control of the RDand WR lines. A read operation is initiated when the RDline is taken low. The next eight cycles of EXCLK willthen transfer out eight bits of the selected addresslocation LSB first. A write takes place by shifting in eightbits of data LSB first for eight consecutive cycles of3-3

SSI73K212LBell 212A/103Single-Chip ModemPIN DESCRIPTIONPOWERNAME 28·PIN 22·PINGND 28 1VDD 15 11VREF 26 21ISET 24 19TYPEII0IDESCRIPTIONSystem Ground.Power supply input, 5V ± 10% (?3K212l). Bypass with .1and 22 f..lF capacitors to ground.An internally generated reference voltage. Bypass with0.1 f..lF capacitor to GND.Chip current reference. Sets bias current for op-amps. Thechip current is set by connecting this pin to VDD through a2 MQ resistor. ISET should be bypassed to GND with a0.1 f..lF capacitor.PARALLEL MICROPROCESSOR INTERFACEALE 12 - IADO-AD? 4-11 - I/OCS 20 - IClK 1 2 0INT 1? 13 0RD 14 - IAddress latch enable. The falling edge of ALE la~ches theaddress on ADO-AD2 and the chip select on CS.Address/data bus. These bidirectional tri-state multiplexedlines carry information to and from the internalregisters.Chip select. A low during the falling edge of ALE on this pinallows a read cycle or a write cycle to occur. ADO-AD? willnot be driven and no registers will be written if CS (latched)is not active. The state of CS is latched on the falling edgeof ALE.Output clock. This pin is selectable under processor controlto be either the crystal frequency (for use as a processorclock) or 16 x the data rate for use as a baud rate clock inDPSK modes only. The pin defaults to the crystal frequencyon reset.Interrupt. This open drain output signal is used to inform theprocessor that a detect flag has occurred. The processormust then read the detect register to determine whichdetect triggered the interrupt. INT will stay low until theprocessor reads the detect register or does a full reset.Read. A low requests a read of the SSI 73K212l internalregisters. Data cannot be output unless both RD and thelatched CS are active or low.3-4

SSI73K212LBell 212A/1 03Single-Chip ModemPARALLEL MICROPROCESSOR INTERFACE (Continued)NAME 2S-PIN 22-PIN TYPE DESCRIPTIONRESET 25 20 I Reset. An active high signal on this pin will put the chip intoan inactive state. All control register bits (CRO, CR1 , Tone)will be reset. The output of the CLK pin will be set to thecrystal frequency. An internal pull down resistor permitspower on reset using a capacitor to VDD.WR 13 - I Write. A low on this informs the SSI 73K212L that data isavailable on ADO-AD7 for writing into an internal register.Data is latched on the rising edge of WR. No data is writtenunless both WR and the latched CS are low.SERIAL MICROPROCESSOR INTERFACEAO-A2 - 5-7 I Register Address Selection. These lines carry registeraddresses and should be valid during any read or writeoperation.DATA - 8 I/O Serial Control Data. Data for a read/write operation isclocked in or out on the falling edge of the EXCLK pin. Thedirection of data flow is controlled by the RD pin. RD lowoutputs data. RD high inputs data.RD - 10 I Read. A low on this input informs the SSI 73K212L thatdata or status information is being read by the processor.The falling edge of the RD signal will initiate a read from theaddressed register. The RD signal must continue for eightfalling edges of EXCLK in order to read all eight bits of thereferenced register. Read data is provided LSB first. Datawill not be output,unless the RD signal is active.WR - 9 I Write. Alowonthis input informs the SSI73K212L that dataor status information has been shifted in through the DATApin and is available for writing to an internal register. Thenormal procedure for a write is to shift in data LSB first onthe DATA pin for eight consecutive falling edges of EXCLKand then to pulse WR low. Data is written on the rising edgeofWR.Note:In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with thepins; AD, A 1 , A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2,respectively.I3-5

SSI73K212LBell 212A/1 03Single-Chip ModemDTE USER INTERFACENAME 28-PIN 22-PINEXCLK 19 15RXCLK 23 18RXD 22 17TXCLK 18 14TXD 21 16TYPEI000IDESCRIPTIONExternal Clock. This signal is used in synchronous transmissionwhen the external timing option has been selected.In the external timing mode the rising edge of EXCLK isused to strobe synchronous DPSK transmit data applied tothe TXD pin. Also used for serial control interface.Receive Clock. The falling edge of this clock output iscoincident with the transitions in the serial received dataoutput. The rising edge of RXCLK can be used to latch thevalid output data. RXCLK will be valid as long as a carrieris present.Received Data Output. Serial receive data is available onthis pin. The data is always valid on the rising edge ofRXCLK when in synchronous mode. RXD will output constantmarks if no carrier is detected.Transmit Clock. This signal is used in synchronous transmissionto latch serial input data on the TXD pin. Data mustbe provided so that valid data is available on the rising edgeof the TXCLK. The transmit clock is derived from differentsources depending upon the synchronization modeselection. In Internal Mode the clock is generated internally.In External Mode TXCLK is phase locked to the EXCLK pin.In Slave Mode TXCLK is phase locked to the RXCLK pin.TXCLK is always active.Transmit Data Input. Serial data for transmission is appliedon this pin. In synchronous modes, the data must be validon the rising edge of the TXCLK clock. In asynchronousmodes (1200 bitls or 300 baud) no clocking is necessary.DPSK data must be 1200 bitls +1%, -2.5%.ANALOG INTERFACE AND OSCILLATORRXA 27 22 ITXA 16 12 0XTL1 2 3 IXTL2 3 4 IReceived modulated analog signal input from the telephoneline interface.Transmit analog output to the telephone line interface.These pins are for the internal crystal oscillator requiringa 11.0592 MHz parallel mode crystal and two load capacitorsto Ground. Consult crystal manufacturer for propervalves. XTL2 can also be driven from an external clock.3-6

SSI73K212LBell 212A/1 03Single-Chip ModemREGISTER DESCRIPTIONSFour a-bit internal registers are accessible for controland status monitoring. The registers are accessed inread or write operations by addressing the AO, A 1 andA2 address lines in serial mode, or the ADO, AD1 andAD2 lines in parallel mode. In parallel mode the addresslines are latched by ALE. Register CRO controlsthe method by which data is transferred over the phoneline. CR1 controls the interface between the microprocessorand the SSI 73K212L internal state. DR is adetect register which provides an indication of monitoredmodem status conditions. TR, the tone controlregister, controls the DTMF generator, answer andguard tones and RXD output gate used in the modeminitial connect sequence. All registers are read/writeexcept for DR which is read only. Register control andstatus bits are identified below:REGISTER BIT SUMMARYCROICONTROLENABLEREGISTER CRl 001 DETECT1 INTERRUPTDETECTRECEIVEREGISTER DR 010 DATABYPASS CLK TEST TESTSCRAMBLER CONTROL RESET MODE MODE1 0UNSCR. CARRIER ANSWER CALL LONGMARKS DETECT TONE PROGRESS LOOPTONECONTROL TR 011REGISTERTRANSMITDTMF DTMF3 DTMF2 DTMFl DTMFOCONTROLREGISTER CR2 1002CONTROLREGISTER CR3 101310REGISTER 10 110NOTE: When a register containing reserved controlbits is written into, the reserved bits must beprogrammed as O's.3-7

SSI73K212LBell 212A/1 03Single-Chip ModemREGISTER ADDRESS TABLEOOOO=PWR DOWN0OO1-INT SYNCH0010-EXT SYNCH0011=SLAVE SYNCH0100=ASYNCH 8 BITSICHAR0101=ASYNCH 9 BITSICHAR0110=ASYNCH 10 BITSICHAR0111 =ASYNCH 11 BITS/CHAR1100=FSKO=DISABLETXA OUTPUT1=ENABLETXAOUTPUTO=ANSWER1=ORIGINATEO-XTAL1=16 X DATARATE OUTPUTATCLK PIN INDPSKMODEONLY00XX=73K212L. 322L. 321 L01 XX=73K221 L. 302L10XX=73K222L1100=73K224L1110=73K324L1101 =73K312L3-8

SSI73K212LBell 212A/1 03Single-Chip ModemCONTROL REGISTER 005 04 03 02 01 DOTRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 3 MODE 2 MODE 1 MODE 0 ENABLE ORIGINATEBIT NO.NAMECONDITIONDESCRIPTIONDOAnswer/OriginateoSelects answer mode (transmit in high band, receivein low band).01TransmitEnableoSelects originate mode (transmit in low band, receive inhigh band).Enables tranTXA.TXA.Note: Answer tone and OTMF TX control require TXenable.•05,04,03,02TransmitModeo 000Selects power down mode. All functionsdisabled except digital interface.000o 0oInternal synchronous mode. In this mode TXCLK is aninternally derived 1200 Hz signal. Serial input dataappearing at TXO must be valid on the rising edge ofTXCLK. Receive data is clocked out of RXO on thefalling edge of RXCLK.External synchronous mode. Operation is identical tointernal synchronous, but TXCLK is connected internallyto EXOLK pin, and a 1200 Hz clock must besupplied externally.o 0o o 0o oo ooSlave synchronous mode. Same operation as othersynchronous modes. TXCLK is connected internally tothe RXCLK pin in this mode.Selects OPSK asynchronous mode - 8 bits/character(1 start bit, 6 data bits, 1 stop bit).Selects OPSK asynchronous mode - 9 bits/character(1 start bit, 7 data bits, 1 stop bit).Selects OPSK asynchronous mode - 10 bits/character(1 start bit, 8 data bits, 1 stop bit).Selects OPSK asynchronous mode - 11 bits/character(1 start bit, 8 data bits, Parity and 1 stop or 2 stop bits).3-9

SSI73K212LBell 212A/1 03Single-Chip ModemCONTROL REGISTER 107 06TRANSMIT TRANSMITCR1 PATTERN PATTERN001 1 005ENABLEDETECTINTER.04 03 02 01 DOBYPASS ClK RESET TEST TESTSCRAMB CONTROL MODE MODE1 0BIT NO. NAME CONDITION01 DO01, DO Test Mode 0 00 11 01 102 Reset 003 ClK Control 0(Clock Control)04 Bypass 0Scrambler05 Enable Detect 0Interrupt1111DESCRIPTIONSelects normal operating mode.Analog loopback mode. loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same center frequency as the transmitter. Tosquelch the TXA pin. transmit enable bit must be low.Selects remote digital loopback. Received data islooped back to transmit data internally, and RXO isforced to a mark. Data on TXO is ignored.Selects local digital loopback. Internally loops TXOback to RXO and continues to transmit data carrier atthe TXA pin.Selects normal operation.Resets modem to power down state. All control registerbits (CRO, CR1. Tone) are reset to zero. The outputof the ClK pin will be set to the crystal frequency onreset.Selects 11.0592 MHz crystal echo output at ClK pin.Selects 16 X the data rate. output at ClK pin in OPSKmodes only.Selects normal operation. OPSK transmn data is passedthrough scrambler.Selects Scrambler Bypass. Bypass OPSK data isrouted around scrambler in the t~ansmit path.--Disables interrupt at INT pin.Enables INT output. An interrupts will be generatedwith a change in status of DR bits 01-04. The answertone and call progress detect interrupts are maskedwhen the TX enable bit is set. Carrier detect is maskedwhen TX OTMF is activated. All interrupts will bedisabled if the device is in power down mode.3-10

SSI73K212LBell 212A/1 03Single-Chip ModemCONTROL REGISTER 1 (Continued)07 06 05TRANSMIT TRANSMIT ENABLECR1 PATTERN PATTERN OETECT001 1 0 INTER.BIT NO. NAME CONDITION07 0607,06 Transmit 0 0PatternDETECT REGISTER0 11 01 104 03 02 01 00BYPASS ClK TEST TESTSCRAMB CONTROL RESET MOOE MOOE1 0DESCRIPTIONSelects normal data transmission as controlledby the state of the TXO pin.Selects an alternating mark/space transmit pattern formodem testing.Selects a constant mark transmit pattern.Selects a constant space transmit pattern.IBIT NO. NAME CONDITION.00 lONG lOOP 0DESCRIPTIONIndicates normal received signal.01 CAllPROGRESSOETECT02 ANSWER 0TONEDETECT03 CARRIER 0DETECT04 UNSCRAM- 0BlEOMARKIndicates presence of call progress tones. The callprogress detection circuitry is activated by energy inthe 350 to 620 Hz call progress band.No answer tone detected.Indicates detection of 2225 Hz answer tone. Thedevice must be in originate mode for detection ofanswer tone.No carrier detected in the receive channel.Indicated carrier has been detected in the receivedchannel.No unscrambled mark.Indicates detection of unscrambled marks in thereceived data. A valid indication requires thatunscrambled marks be received for> 165.5 ± 6.5 ms.3-11

SSI73K212LBell 212A/1 03Single-Chip ModemDETECT REGISTER (Continued)D5D4D3D2D1DORECEIVEDATAUNSCR.MARKCARR.DETECTANSWERTONECALLPROG.LONGLOOPBIT NO.NAMECONDITIONDESCRIPTIOND5RECEIVEDATAContinuously outputs the received data stream. Thisdata is the same as that output on the RXO pin, but itis not disabled when RXD is tri-stated.06,07Not used.TONE REGISTERD7RXDTR OUTPUT011 CONTR.05TRANSMITANSWERTONED4 03 D2 D1 DOTRANSMITDTMF DTMF3 DTMF2 DTMF 1 DTMFOBIT NO.NAMECONDITIONDESCRIPTIOND3, D2,D1, DODTMF03 D2 D1 DOo 0 0 0-1 1 1 1Programs 1 of 16 DTMF tone pairs that will betransmitted when TX DTM F and TX enable bit (CRO, bitD1) are set. Tone encoding is shown below:KEYBOARD DTMF CODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGHo 000 0 941 16333-12

SSI73K212LBell 212A/1 03Single-Chip ModemTONE REGISTER (Continued)TR01107RXOOUTPUTCONTR.05 04 03 02 01 00TRANSMIT TRANSMIT OTMF 3 OTMF 2 OTMF 1 OTMFOANSWER OTMFTONEBIT NO.NAMECONDITIONDESCRIPTION040507TRANSMITOTMFTRANSMITANSWERTONERXO OUTPUTCONTROLooDisable OTMF.Activates OTMF. The selected OTMF tones aretransmitted continuously when this bit is high (withTransmit Enable, CRO-01). TX OTMF overrides allother transmit functions.Enables answer tone generator. A 2225 Hz answertone will be transmitted continuously when the TransmitEnable bit is set in CRO. The device must be inanswer mode.Enables RXO pin. Receive data will be output onRXO.•Oisables RXO pin. The RXO pin reverts to a highimpedance with internal, weak pull-up resistor.10 REGISTER1011007100610051004100310 .BIT NO.NAMECONDITIONDESCRIPTION07 06 05 04Indicates Oevice:07, 06, 05 Oevice04 IdentificationSignature73K321L3-13

SSI73K212LBell 212A/1 03Single-Chip ModemELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETERVDD Supply VoltageStorage TemperatureSoldering Temperature (10 sec.)Applied VoltageRATING14 V-65 to 150°C260°C-0.3 to VDD + 0.3 VNote: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSP~RAMETER CONDITIONS MIN NOM MAX UNITSVDD Supply Voltage 4.5 5 5.5 VTA, Operating Free-Air -40 +85 °CTemperatureClock Variation (11.0592 MHz) Crystal or -0.01 +0.01 %external clockExternal Components (Refer to Application section for placement.)VREF Bypass capacitor (External to GND) 0.1 IJ.FBias setting resistor (Placed between VDD 1.8 2 2.2 MQand ISET pins)ISET Bypass capacitor (ISET pin to~ND) 0.1 IJ.FVDO Bypass capacitor 1 (External to Gr'JD) 0.1 IJ.FVDO Bypass capacitor 2 (External to GNO) 22 IJ.FXTL 1 Load CapaCitor Depends on crystal characteristics; 40 pFXTL2 Load Capacitor from pin to GND 20--3-14

SSI73K212LBell 212A11 03Single-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN NOM MAX UNITS100, Supply Current ISET Resistor = 2 MQIDDA, Active ClK = 11.0592 MHz 8 12 rnA--1001, Power-down ClK = 11.0592 MHz 4 rnA1002, Power-down ClK = 19.200 kHz 3 rnADigital InputsVIH, Input High VoltageReset, XTl1 , XTl2 3.0 VDD VAll other inputs 2.0 VDD VVll, Input low Voltage 0 0.8 VIIH, Input High Current VI = VIH Max 100 ~•Ill, Input low Current VI = Vil Min -200 ~Reset Pull-down Current Reset = VDD 1 50 ~Input Capacitance All Digital Input Pins 10 pFDigital OutputsVOH, Output High Voltage 10H MIN = -0.4 rnA 2.4 VDD VVOL, Output low Voltage 10 MAX=1.6 rnA 0.4 VVOL, ClK Output 10 = 3.6 rnA 0.6 VRXD Tri-State Pull-up Curr. RXD=GND -1 -50 ~CMAX, ClK Output Maximum Capacitive load 15 pF3-15

SSI73K212LBell 212AJ1 03Single-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING(TA = -40°C to + 85°C, VDD = recommended range unless otherwise noted.)PARAMETERS CONDITIONS MINPSK ModulatorCarrier Suppression Measured at TXA 55Output Amplitude TX scrambled marks -11FSK Mod/DemodOutput Freq. Error ClK = 11.0592 MHz -0.35Transmit level Transmit Dotting Pattern -11Harmonic Distortionin 700-2900 Hz bandOutput Bias DistortionTHD in the alternate bandDPSK or FSKTransmit Dotting PatternInAlB@ RXDTotal Output Jitter Random Input in ALB @ RXD -15DTMF GeneratorFreq. Accuracy -.25Output Amplitude low-Band, DPSK Mode -10Output Amplitude High-Band, DPSK Mode -8Twist High-Band to low-Band, 1.0DPSK modeLong Loop Detect DPSK or FSK -38Dynamic RangeCall Progress DetectorRefer to Performance CurvesDetect level 2-Tones in 350-600 Hz band -34Reject level2-Tones in 350-600 Hz bandDelay Time -70 dBmO to -30 dBmO STEP 27Hold Time -30 dBmO to -70 dBmO STEP 27Hysteresis 2Note: Parameters expressed in dBmO refer to the following definition:o dB loss in the Transmit path to the line.2 dB gain in the Receive path from the line.NOMMAX-10.0 -9+.35-10.0 -9-60 -50±8-------+15+.25-9 -8-7 -62.0 3.045---Refer to the Basic Box Modem diagram in the Applications section for the DAA design.-280-418080UNITSdBdBmO%dBmOdB%%%dBmOdBmOdBdBmOdBdBmOdBmOmsmsdB3-16

SSI73K212LBell 212A/1 03Single-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMINNOM MAX UNITScarrier DetectThresholdDPSK or FSK receive data-49-42 dBmODelay Time-70 dBmO to -30 dBmO STEP1545 msHysteresisSingle tone detected23 dBHold Time-30 dBmO to -70 dBmO STEP1024 msAnswer Tone DetectorDetect LevelDelay TimeHold TimeDetect Freq. RangeOutput Smoothing FilterTXA pin Output ImpedanceIn FSK mode-70 dBmO to -30 dBmO STEP-30 dBmO to -70 dBmO STEP-492010-2.5---"- --- -..-42 dBmO45 ms30 ms+2.5 %---200 300 Q•Output loadTXA pin; FSK SingleTone out for THD = -50 dbin .3 to 3.4 KHz1050 pF~kQSpurious Freq. CompoFrequency = 76.8 KHzFrequency = 153.6 KHz-------39 dBmO-45 dBmOClock NoiseCarrierVCOTXA pin; 76.8 KHz------1.0 mVmsCapture RangeCapture TimeOriginate or Answer-10 Hz to +10 Hz CarrierFreq. Change Assum.-10._._-+10 Hz40 100 ms-- .. ~-Recovered ClockCapture RangeData Delay Time% of frequencycenter frequency(center at 1200 Hz)Analog data in at RXA pin toreceive data valid at RXD pin-625 +625 ppm-----30 50 ms3-17

SSI73K212LBell 212A/1 03Single-Chip ModemELECTRICAL SPECIFICATION (Continued)DYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSTiming (Refer to Timing Diagrams)TALTLATLCTCLTRDTLLTRDFTRWTWWTOWTWOTCKDTCKWTDCKTACTCATWHCONDITIONSCSI Addr. setup before ALE lowCS/Addr. hold after ALE lowALE low to RD/WR lowRD/WR Control to ALE highData out from RD lowALE widthData float after RD highRDwidthWRwidthData setup before WR highData hold after WR highData out after EXCLK lowWR after EXCLK lowData setup before EXCLK lowAddress setup before control**Address hold after control**Data Hold after EXCLK* Maximum time applies to parallel version only.** Control for setup is the falling edge of RD or WR.Control for hold is the falling edge of RD or the rising edge of WR.MIN NOM MAX UNITS30 ns20 ns40---ns10 ns0 160--ns60 ns0-80 ns200 25000 ns140 25000* ns.. _-150 ns20 ns200 ns--150 nsf----150 ns------50 ns50 ns20 ns3-18

SSI73K212LBell 212A/1 03Single-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE~TlC JRD --\-WRL TAL.. 'JTRWF4c.L TCl j+ TlC.L TWW .I--~TlA TRD TRDF I TWD~ ~ I .. TOW ~ .. • ~IADO-AD7 --K ADDRESS }------K READ DATA}------K ADDRESS ~~cs -=1- -4- -~- -4-•READ TIMING DIAGRAM (SERIAL VERSION)EXClKRDAO-A2DATA ---f-WRITE TIMING DIAGRAM (SERIAL VERSION)EXClK-----r-------------------------------------r-~HTWWAO-A2 ---+----------------TCKWI LI, TAC , ITCADATA3-19

SSI73K212LBell 212A/1 03Single-Chip ModemAPPLICATlONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit di~grams forK -Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a DAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes.Two typical DAA arrangementsare shown: one for a split ±5 or±12 voltdesign and one for a single 5 volt design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one tor a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039/48 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version can• be used with other microcontroJlers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the serial mode, as explained in the datasheet pin description.In most applications the controJlerwiJl monitor the serialdata for commands from the DTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent overthe sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.RS232LEVELCONVERTERSCA I-f>.+-=C:----!CB I-

SSI73K212LBell 212A/1 03Single-Chip ModemDIRECT ACCESS ARRANGEMENT (OAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing at the transformer, making the transmitsignal common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This circuit(Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a single 5V supply. BecauseDTMF tones utilize a higher amplitude than data, thesesignals will clip if a single-ended drive approach isused. The bridged driver uses an extra op-amp (U1 A)to invert the signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-amp then supplies half the drive signalto the transformer. The receive amplifier (U1 C) picksoff its signal at the junction of the impedance matchingresistor and the transformer. Because the bottom leg ofthe transformer is being driven in one direction by U1 Aand the resistor is driven in the opposite direction at thesame time by U1 B, the junction of the transformer andresistor remains relatively constant and the receiveSignal is unaffected.DESIGN CONSIDERATIONSSilicon Systems 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.ICl390pFR437.4K 1%* Note: Op-amp U1must be rated forsingle 5V operation.R10 & R11 valuesdepend on Op-ampused.+5VC6O.lnF~~~\r'AI~~~~~VRlMOVV250L20VOLTAGEREFERENCEHOOK >---------'RING ~--------------------~FIGURE 2: Single SV Hybrid Version3-21

SSI73K212LBell 212A/1 03Single-Chip ModemUnlike digital logic circuitry, however, modem designsmust properly contend with precise frequency tolerancesand very low level analog signals, to ensureacceptable performance. Using good analog circuitdesign practices will generally result in a sound design.Following are additional recommendations whichshould be taken into consideration when starting newdesigns.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01% accuracy.I n order for a parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LA YOUT CONSIDERATIONSGood analog/digital design rules must be used tocontrol system noise in orderto obtain highest performancein modem designs. The more digital circuitrypresent on the PC board, the more this attention tonoise control is needed. The modem should be treatedas a high impedance analog device. A 22 mF electrolyticcapacitor in parallel with a 0.1 mF ceramic capacitorbetween VDD and GND is recommended. Liberaluse of ground planes and larger traces on power andground are also highly favored. High speed digitalcircuits tend to generate a significant amount of EMI(Electro-Magnetic Interference) which must be minimizedin order to meet regulatory agency limitations.To accomplish this, high speed digital devices shouldbe locally bypassed, and the telephone line interfaceand K-Series device should be located close to eachother near the area of the board where the phone lineconnection is accessed. To avoid problems, powersupply and ground traces should be routed separatelyto the analog and digital functions on the board, anddigital signals should not be routed near low level orhigh impedance analog traces. The analog and digitalgrounds should only connect at one point near the K­Series device ground pin to avoid ground loops. The K­Series modem IC's should have both high frequencyand low frequency bypassing as close to the packageas possible.MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line simulator, operatingunder computer control. All tests were run fullduplex,using a Concord Data Systems 224 as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and all signal-to-noise (SIN) ratios reflecttotal power measurements similar to the CCITT V.56measurement specification. The individual tests aredefined as follows.SER vs. SINThis test measures the ability of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a DPSK modem will exhibitbetter BER-performance test curves receiving in thelow band than in the high band.SER vs. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamicrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels. The width of the "bowl" ofthese curves, taken at the BER point, is the measure ofdynamic range.3-22

SSI73K212LBell 212A/1 03Single-Chip Modem10'2SSI73K212LBER vs SIGNAL TO NOISEI HIGH BAND RECEIVE ~,40dBm\ I DPS1~~ci~~~~ION\10-3\'~10-4\~ ~f-- C2\'¥--r-t--,----,Clor3002~ ~~ ----l ~~1\ '\\\\10,5 \\"'1\ '1\ \10,6 \ \2 4 6 B 10 12 1410'210'310 410,510'612SSI73K212LBER vs CARRIER OFFSETI HIGH BAND RECEIVE r-L DPSK OPERATION--300211.8dBSlN1\I C211.3dBSlN \-- -10- -t ~ -~r-10- ~ ~-8 4 0 ,4 ,8 -12ISIGNAL TO NOISE (dB)CARRIER OFFSET (HZ)10'2*SS173K212LBERvs RECEWE LEVELI HIGH BAND RECEIVE rIDPSK OPERATIONC2lINE10'2*SSI 73K212LBER vs PHASE JITTERI HIGH BAND RECEIVE t-I DPSK OPERATION10'310'3 •10 4 SIN 10,8 dB10'5\ /10'410'5= ~ 3002 11.5 dB SIN ./~ ./'~ ~ /k:::: r:::: - f.- \I C2 10.8 dB SIN I r--~SIN15 dB10,610 0 ,10 -20 -30 -40 -50RECEIVE LEVEL (dBm)10,60 4 8 12 16 20 24PHASE JITTER (0 PEAK)*"EO On" Indicates bit CR1 04 is set for additional phase equalization.3-23

SSI73K212LBell 212A/1 03Single-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.GNDA1RXAVREFRESETISETRXClKRXDTXDEXCLKTXClKINTTXAClKXTl1XTL2ADOAD1AD2AD3AD4AD5ADSAD?ALEWRRDGNDRXAVREFRESETISETRXClKRXDTXDcsEXClK400-MilGOO-Mil28-Pin22-Pin DIP 28-Pin DIP PLCCTXAVDD4 3 2 1 28 27 262524PLCC PINOUTS 238 ARE THE SAME AS 22THE 28-PIN DIP 2110 2011 1912 13 14 15 16 17 18ORDERING INFORMATIONPART DESCRIPTION ORDER NO. PKG.MARK28-pinPlastic Dual-In-Line 73K212L-IP 73K212L-IPPlastic Leaded Chip Carrier 73K212L -IH 73K212L -IH22-pinPlastic Dual-In-Line 73K212SL -IP 73K212SL - IPCeramic Dual-In-Line 73K212SL - IC 73K212SL - ICNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69140194 - rev.3-24Protected by the following Patents (4,691,172) (4,777,453)©1989 Silicon Systems, Inc.

SSI73K221LCCITT V.22, V.21Single-Chip ModemJanuary 1994DESCRIPTIONThe 881 73K221 L is a highly integrated single-chipmodem IC which provides the functions needed toconstruct a CCITT V.22 and V.21 compatible modem,capable of 1200 or 0-300 bitls full-duplex operationover dial-up lines. The 881 73K221 L is an enhancementof the 881 73K212L single-chip modem withperformance characteristics suitable for European andAsian telephone systems. The 881 73K221 L produceseither 550 or 1800 Hz guard tone, recognizes andgenerates a2100 Hz answer tone, and allows V.21 for300 Hz F8K operation. The 881 73K221 L integratesanalog, digital, and switched-capacitor array functionson a single substrate, offering excellent performanceand a high level of functional integration in a single 28-or 22-pin DIP configuration. The 881 73K221 L, operatesfrom a single +5 volt supply.The 881 73K221 L includes the DP8K and F8K modulator/demodulatorfunctions, call progress and handshaketone monitor test modes, and a tone generatorcapable of producing DTMF, answer and 550 or1800 Hz guard tone. This device supportsV.22 (Except mode v) and V. 21 modes of operation,(Continued)BLOCK DIAGRAMFEATURESOne-chip CCITT V.22 and V.21 standard compatiblemodem data pumpFull-duplex Operation at 0-300 bitls (FSK) or 600and 1200 bitls (DPSK)Pin and software compatible with otherSSI K-Series 1-chip modemsInterfaces directly with standard microprocessors(8048, 80C51 typical)Serial (22-pin DIP) or parallel (28-pin DIP orPLCC) microprocessor bus for controlSerial port for data transferBoth Synchronous and Asynchronous modes ofoperationCall progress, carrier, preCise answer tone(2100 Hz), and long loop detectorsDTMF, and 550 or 1800 Hz guard tone generatorsTest modes available: ALB, DL, RDL, Mark,Space, Alternating bit patternsPrecise automatic gain control allows 45 dBdynamic rangeSpace efficient 22- or 28-pin DIP or 28 Pin PLCCpackagesCMOS technology for low power consumptionusing 30 mW @ 5VSingle +5 volt supplyPIN DIAGRAMIADO·AD7'.----,"1lID o--~Wli o--~ALE o--~os O--~RESET O--~TXDRXDo-------~o--------L_----.JClKXTllXTl2ADOADlAD2AD3AD4ADSAD6AD7ALEWRRDRXAVREFRESETISETRXClKRXDTXDEXClKINTTXAVDDCAUTION: Use handling procedures necessaryfor a static sensitive component.0194 - rev. 3-25

SSI73K221LCCITT V.22, V.21Single-Chip ModemDESCRIPTION (Continued)allowing both synchronous and asynchronous communications.The SSI 73K221 L is designed to appearto the systems designer as a microprocessor peripheral,and will easily interface with popular one-chipmicroprocessors (80C51 typical) for control of modemfunctions through its 8-bit multiplexed address/databus or alternatively via the serial control bus. An ALEcontrol line simplifies address demultiplexing. Datacommunications occurs through a separate serial portonly.The SSI73K221 L is ideal for use in either free standingor integral system modem products where full-duplex1200 bit/s data communications over the 2-wireswitched telephone network is desired. Its high functionality,low power consumption and efficient packagingsimplify design requirements and increase systemreliability. A complete modem requires only the additionof the phone line interface, a control microprocessor,and RS-232 level converter for a typical system.The SSI 73K221 L is part of Silicon Systems' K-Seriesfamily of pin and function compatible single-chip modemproducts. These devices allow systems to beconfigured for higher speeds and Bell or CCITT operationwith only a single component change.OPERATIONASYNCHRONOUS MODEData transmission for the DPSK mode requires thatdata ultimately be transmitted in a synchronousfashion, The SSI 73K221 L includes ASYNC/SYNCand SYNC/ASYNC converters which delete or insertstop bits in order to transmit data at a regular rate. InAsynchronous mode the serial data comes from theTXD pin into the ASYNC/SYNC rate converter. TheASYNC/SYNC rate converter accepts the data providedon the TXD pin which normally must be 1200 or600 bitls + 1.0%, - 2.5%. The rate converter will theninsert or delete stop bits in order to output a signalwhich is 1200 or 600 bitls ± 0.01 %.The serial data stream from the ASYNC/SYNC converteris passed through the data scrambler and ontothe analog modulator. The data scrambler can bebypassed under processor control when unscrambleddata must be transmitted. The ASYNC/SYNC rateconverter and the data scrambler are bypassed in allFSK modes. If serial input data contains a break signalthrough one character~(including start and stop bits) thebreak will be extended to at least 2· N + 3 bits long(where N is the number of transmitted bits/character).Serial data from the demodulator is passed firstthrough the data descrambler and then through theSYNC/ASYNC rate converter. The SYNC/ASYNCconvertor will reinsert any deleted stop bits and transmitoutput data at an intra-character rate (bit-to-bittiming) of no greaterthan 1219 bit/so An incoming breaksignal (low through two characters) will be passedthrough without incorrectly inserting a stop bit.The SYNC/ASYNC converter also has an extendedOverspeed mode which allows selection of an outputrange of either +1% or +2.3%. In the extendedOverspeed mode, stop bits are output at 7/8 the normalwidth.SYNCHRONOUS MODEThe CC ITT V .22 standard defines synchronous operationat 600 and 1200 bit/s. The Bell 212A standarddefines synchronous operation only at 1200 bitls.Operation is similar to that of the Asynchronous modeexcept that data must be synchronized to a providedclock and no variation in data transfer rate is allowable.Serial input data appearing at TXD must be valid on therising edge of TXCLK.TXCLK is an internally derived signal in Internal modeand is connected internally to the RXCLK pin in Slavemode. Receive data at the RXD pin is clocked out onthe falling edge of RXCLK. The ASYNC/SYNC converteris bypassed when Synchronous mode isselected and data is transmitted at the same rate as itis input.DPSK MODULATOR/DEMODULATORThe SSI 73K221 L modulates a serial bit stream intodibit pairs that are represented by four possible phaseshifts as prescribed by the V.22 standard. Thebaseband signal is then filtered to reduce intersymbolinterference on the bandlimited 2-wire telephone line.Transmission occurs on either a 1200 Hz (Originatemode) or 2400 Hz carrier (Answer mode). Demodulationis the reverse of the modulation process, with theincoming analog signal eventually decoded into di-bitsand converted back to a serial bit stream. The demodulatoralso recovers the clock which was encoded intothe analog signal during modulation. Demodulation3-26

SSI73K221LCCITT V.22, V.21Single-Chip Modemoccurs using either a 1200 Hz carrier (Answer mode orALB Originate mode) or a 2400 Hz carrier (Originatemode or ALB Answer mode). The SSI 73K221 L usesa phase locked loop coherent demodulation techniquefor optimum performance.FSK MODULATOR/DEMODULATORThe FSK modulator produces a frequency modulatedanalog output signal using two discrete frequencies torepresent the binary data. V.21 mode uses 980 and1180 Hz (originate, mark and space) or 1650 and1850 Hz (answer, mark and space). Demodulationinvolves detecting the received frequencies anddecoding them into the appropriate binary value. Therate converter and scrambler/descrambler are bypassedin the V.21 mode.PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and provide compromise delay equalizationand rejection of out-of-band signals in the receivechannel. Amplitude and phase equalization arenecessary to compensate for distortion of the transmissionline and to reduce intersymbol interference in theband limited receive signal. The transmit signal filteringapproximates a 75% square root of raised Cosinefrequency response characteristic.AGCThe automatic gain control maintains a signal level atthe input to the demodulators which is constant towithin 1 dB. It corrects quickly for increases in signalwhich would cause clipping and provides a totaldynamic range of >45 dB.PARALLEL BUS INTERFACEFour 8-bit registers are provided for control, optionselectand status monitoring. These registers areaddressed with the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as four consecutive memory locations.Two control registers and the tone register areread/write memory. The detect register is read only andcannot be modified except by modem response tomonitored parameters.SERIAL COMMAND INTERFACEThe serial Command mode allows access to. theSSI 73K221 L control and status registers via a serialcommand port (22-pin version only). In this mode theAO , A 1 and A2lines provide register addresses for datapassed through the data pin under control of the RDand WR lines. A read operation is initiated when the RDline is taken low. The first bit is available after RD isbrought low and the next seven cycles of EXCLK willthen transfer out the remaining seven bits of the selectedaddress LSB first. A write takes place by shiftingin eight bits of data LSB first for eight consecutivecycles of EXCLK. WR is then pulsed low and datatransferred into the addressed register on the risingedge of WR.SPECIAL DETECT CIRCUITRYThe special detect circuitry monitors the receivedanalog signal to determine status or presence of carrier,call-progress tones, answer tone and weakreceived signal (long loop condition). An unscrambledmark signal is a Iso detected w he n the received data outof the DPSK demodulator before the descrambler hasbeen mark for 165.5 ms ± 6.5 ms minimum. Theappropriate detect register bit is set when one of theseconditions changes and an interrupt is generated for allconditions except long loop. The interrupts are disabled(masked) when the enable interrupt bit is setto O.DTMF GENERATORThe DTMF generator will output one of 16 standardtone pairs determined by a 4-bit binary value and TXDTMF mode bit previously loaded into the tone register.Tone generation is initiated when the DTMF modeis selected using the tone register and the transmitenable (CRO bit D1) is changed from 0 to 1.•3-27

SSI73K221LCCITT V.22, V.21Single-Chip ModemPIN DESCRIPTIONPOWERNAME 28·PIN 22·PINGND 28 1VDD 15 11VREF 26 21ISET 24 19TYPEII0IDESCRIPTIONSystem Ground.Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 gFcapacitors to ground.An internally generated reference voltage. Bypass with0.1 J.lF capacitor to GND.Chip current reference. Sets bias current for op-amps. Thechip current is set by connecting this pin to VDD through a2 MQ resistor. ISET should be bypassed to GND with a0.1 J.lF capacitor.PARALLEL MICROPROCESSOR INTERFACEALE 12 - IADO-AD7 4-11 - I/OCS 20 - IClK 1 2 0INT 17 13 0RD 14 - IRESET 25 20 IAddress latch enable. The falling edge of ALE latches theaddress on ADO-AD2 and the chip select on CS.Address/data bus. These bidirectional tri-state multiplexedlines carry information to and from the internalcontrol registers.Chip select. A low on this pin during the falling edge of ALEallows a read cycle or a write cycle to occur. ADO-AD7 willnot be driven and no registers will be written if CS (latched)is not active. The state CS is a latched on the falling edgeof ALE.Output clock. This pin is selectable under processor controlto be either the crystal frequency (for use as a processorclock) or 16 x the data rate for use as a baud rate clock inDPSK modes only. The pin defaults to the crystal frequencyon reset.I nterrupt. This open drain output signal is used to inform theprocessor that a detect flag has occurred. The processormust then read the detect register to determine whichdetect triggered the interrupt. INT will stay low until theprocessor reads the detect register or does a full reset.Read. A low requests a read of the SSI 73K221 l internalregisters. Data cannot be output unless both RD and thelatched CS are active or low.Reset. An active high Signal on this pin will put the chip intoan inactive state. All control register bits (CRO, CR1, Tone)will be reset. The output of the ClK pin will be set to thecrystal frequency. An internal pull down permits power onreset using a capacitor to VDD.3-28

SSI73K221LCCITT V.22, V.21Single-Chip ModemPIN DESCRIPTION (Continued)PARALLEL MICROPROCESSOR INTERFACE (Continued)NAME 28·PIN 22·PIN TYPE DESCRIPTIONWR 13 - I Write. A low on this pin informs the SSI 73K221 L that datais available on ADO-AD7 for writing into an internal register.Data is latched on the rising edge of WR. No data is writtenunless both WR and the latched CS are low.SERIAL MICROPROCESSOR INTERFACEAO-A2 - 5-7 I Register Address Selection. These lines carry registeraddresses and should be valid during any read or writeoperation.DATA - 8 I/O Serial Control Data. Data for a read/write operation isclocked in or out on the falling edge of the EXCLK pin. Thedirection of data flow is controlled by the RD pin. RD lowoutputs data. RD high inputs data.RD - 10 I Read. A low on this input informs the SSI73K221 L that dataor status information is being read by the processor. Thefalling edge of the RD signal will initiate a read from theaddressed register. The RD signal must continue for eightfalling edges of EXCLK in order to read all eight bits of thereferenced register. Read data is provided LSB first. Datawill not be output unless the RD signal is active.WR - 9 I Write. A low on this input informs the SSI 73K221 L that dataor status information has been shifted in through the DATApin and is available for writing to an internal register. Thenormal procedure for a write is to shift in data LSB first onthe DATA pin for eight consecutive falling edges of EXCLKand then to pulse WR low. Data is written on the rising edgeofWR.Note:In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with thepins; AD, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2,respectively.I3-29

SSI73K221LCCITT V.22, V.21Single-Chip ModemPIN DESCRIPTION (Continued)DTE USER INTERFACENAME 28·PIN 22·PINEXCLK 19 15RXCLK 23 18RXD 22 17TXCLK 18 14TXD 21 16TYPEI000IDESCRIPTIONExternal Clock. This signal is used in synchronous transmissionwhen the external timing option has been selected.In the External Timing mode the rising edge of EXCLK isused to strobe synchronous DPSK transmit data applied tothe TXD pin. Alternately used for serial control interface.Receive Clock. The falling edge of this clock output iscoincident with the transitions in the serial received dataoutput. The rising edge of RXCLK can be used to latch thevalid output data at RXD. RXCLK will be valid as long as acarrier is present in DPSK synchronous modes.--Received Digital Data Output. Serial receive data is availableon this pin. The data is always valid on the rising edgeof RXCLK when in Synchronous mode. RXD will outputconstant marks if no carrier is detected.Transmit Clock. This signal is used in DPSK synchronoustransmission to latch serial input data on the TXD pin. Datamust be provided sothat valid data is available onthe risingedge of the TXCLK. The transmit clock is derived fromdifferent sources depending upon the Synchronizationmode selection. In Internal Mode the clock is generatedinternally. In External Mode TXCLK is phase locked to theEXCLK pin. In Slave Mode TXCLK is phase locked to theRXCLK pin. TXCLK is always active.Transmit Data Input. Serial data for transmission is appliedto this pin. In Synchronous modes, the data must be validon the rising edge of the TXCLK. In Asynchronous modes(1200/600 bitls or 300 baud) no clocking is necessary.DPSK data must be 1200/600 bit/s +1%, -2.5% or +2.3%,-2.5 % in extended Overspeed mode.ANALOG INTERFACE AND OSCILLATORRXA 27 22 ITXA 16 12 0XTL1 2 3 IXTL2 3 4 IReceived modulated analog signal input from the telephoneline interface.Transmit analog output to the telephone line interface.These pins are for the internal crystal oscillator requiringan 11.0592 MHz Parallel mode crystal. Load capacitorsshould be connected from XTL 1 and XTL2 to Ground. XTL2can also be driven from an external clock.3-30

SSI73K221LCCITT V.22, V.21Single-Chip ModemREGISTER DESCRIPTIONSFour 8-bit internal registers are accessible for controland status monitoring. The registers are accessed inread or write operations by addressing the AO and A 1address lines in Serial mode, orthe ADO and AD1linesin Parallel mode. In Parallel mode ADO and AD1 linesare latched by ALE. Register CRO controls the methodby which data is transferred over the phone line. CR1controls the interface between the microprocessor andthe 551 73K221 L internal state. DR is a detect registerwhich provides an indication of monitored modemstatus conditions. TR, the tone control register, controlsthe DTMF generator, answer and guard tones andRXD output driver used in the modem initial connectsequence. All registers are read/write except for DRwhich is read only. Register control and status bits areidentified below:REGISTER BIT SUMMARYCROICONTROLENABLEREGISTER CR1 001 DETECT1 INTERRUPTDETECTRECEIVEREGISTER DR 010 DATABYPASS CLK TEST TESTSCRAMBLER CONTROL RESET MODE MODE1 0UNSCR. CARRIER ANSWER CALL LONGMARKS DETECT TONE PROGRESS LOOPTONECONTROL m 011REGISTERTRANSMIT DTMF11 DTMFOIDTMF DTMF3 DTMF2 OVERSPEED GUARDICONTROLREGISTER CR2 1002CONTROLREGISTER CR3 101310REGISTER 10 110NOTE:When a register containing reservedcontrol bits is written into, the reserved bitsmust be programmed as O's.3-31

SSI73K221LCCllT V.22, V.21Single-Chip ModemREGISTER ADDRESS TABLE0=1200 BrTlS DPSK1=600 BIT/S DPSKOOOO=PWR DOWN0001=INT SYNCH0010=EXT SYNCH0011 .SLAVE SYNCH0100=ASYNCH 8 BITs/CHAR0101 =ASYNCH 9 BITSICHAR0110=ASYNCH 10 BITS/CHAR0111 =ASYNCH 11 BITS/CHAR1100=FSKO=DISABLETXA OUTPUT1=ENABLETXAOUTPUTO=ANSWER1=ORIGINATEO=DISABLE1=ENABLEO-NORMAL O=XTAL O=NORMAL1=BYPASS 1=16 X DATA 1=RESETSCRAMBLER RATE OUTPUTATCLK PIN INDPSKMODEONLY0=1800 Hz G.T.1 =550 Hz G.T.00XX=73K212L. 322L. 321 L01 XX=73K221 L. 302L10XX=73K222L1100=73K224L1110-73K324L1101 =73K312L3-32

SSI73K221LCCITT V.22, V.21Single-Chip ModemIICONTROL REGISTER 004D7D5CRO MOOUL. TRANSMIT TRANSMIT000 OPTION MODE 3 MODE 2BIT NO. NAME CONDITIONDO Answer/ 0Originate01 Transmit 01Enable 105 04 03 0205,04,03, Transmit 0 0 0 002 Mode0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 103 02 01 DOTRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 1 MOOEO ENABLE ORIGINATEDESCRIPTIONSelects Answer mode (transmit in high band, receivein low band).Selects Originate mode (transmit in low band, receivein high band).'")I!:::"l1P.!:: transmit output at TXAEnables transmit output at TXA.Note: TX Enable must be set to 1 to allow AnswerToneand OTMF transmission.Selects Power Down mode. All functions disabledexcept digital interface.Internal Synchronous mode. In this mode TXCLK is aninternally derived 1200 Hz signal. Serial input dataappearing at TXO must be valid on the rising edge ofTXCLK. Receive data is clocked out of RXO on thefalling edge of RXCLK.External Synchronous mode. Operation is identicaltointernal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 1200 Hz ± 0.01 % clock mustbe supplied externally.Slave Synchronous mode. Same operation as otherSynchronous modes. TXCLK is connected internally tothe RXCLK pin in this mode.Selects OPSK Asynchronous mode - 8 bits/character(1 start bit, 6 data bits, 1 stop bit).Selects OPSK Asynchronous mode - 9 bits/character(1 start bit, 7 data bits, 1 stop bit).Selects DPSK Asynchronous(1 start bit, 8 data bits, 1 stop bit)- 10 bits/characterSelects DPSK Asynchronous mode - 11 bits/character(1 start bit, 8 data bits, Parity and 1 stop bit).I0UI-'t;IQUUII3-33

SSI73K221LCCITT V.22, V.21Single-Chip ModemCONTROL REGISTER 0 (Continued)D7 D5 D4 D3 D2 D1 DOCRO MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/000 OPTION MODE 3 MODE 2 MODE 1 MODE 0 ENABLE ORIGINATEBIT NO.NAMECONDITIONDESCRIPTIONSelects:D7ModulationOptiono XDPSK mode at 1200 bit/soDPSK mode at 600 bit/soX = Don't careCONTROL REGISTER 1D7 D6 D5TRANSMIT TRANSMIT ENABLECR1 PATTERN PATTERN DETECT001 1 0 INTER.D4 D3 02BYPASS ClKSCRAMB CONTROL RESET01 DOTEST TESTMODE MODE1 0BIT NO. NAME CONDITIOND1 DO01, DO Test Mode 0 00 11 01 1D2 Reset 003 ClK Control 0(Clock Control)11DESCRIPTIONSelects normal Operating mode.Analog loopback mode. loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same center frequency as the transmitter. Tosquelch the TXA pin, transmit enable must be forcedlow.Selects remote digital loopback. Received data islooped back to transmit data internally, and RXD isforced to a mark. Data on TXD is ignored.Selects local digital loopback. Internally loops TXDback to RXD and continues to transmit carrier fromTXA pin.Selects normal operation.Resets modem to power down state. All controlregister bits (CRO, CR1, Tone) are reset to zero. Theoutput of the ClK pin will be set to the crystalfrequency.Selects 11.0592 MHz crystal echo output at ClKpin.Selects 16 Xthe data rate, output at ClK pin in DPSKmodes only.3-34

SSI73K221LCCITTV.22, V.21Single-Chip ModemCONTROL REGISTER 1 (Continued)07 06 05TRANSMIT TRANSMIT ENABLECR1 PATTERN PATTERN DETECT001 1 0 INTER.BIT NO. NAME CONDITION04 Bypass 0Scrambler05 Enable Detect 0Interrupt11D7 D6D7,D6 Transmit 0 0PatternDETECT REGISTER0 11 01 104 0302 01 DOBYPASS CLK TEST TESTSCRAMB CONTROL RESET MODE MODE1 0DESCRIPTIONSelects normal operation. DPSK data is passedthrough scrambler.Selects Scrambler Bypass. Bypass DPSK data isrouted around scrambler in the transmit path.Disables interrupt at INT pin.Enables INT output. An interrupts will be generatedwith a change in status of DR bits D1-D4. The answertone and call progress detect interrupts are maskedwhen the TX enable bit is set. Carrier detect is maskedwhen TX DTMF is activated. All interrupts will bedisabled if the device is in Power Down mode.---Selects normal data transmission as determinedby the state of the TXD pin.Selects an alternating mark/space transmit pattern formodem testing.Selects a constant mark transmit pattern.Selects a constant space transmit pattern.IDR010D5RECEIVEDATAD4 D3 D2 D1 DOUNSCR. CARR. ANSWER CALLMARK DETECT TONE PROG.LONGLOOPBIT NO. NAME CONDITION DESCRIPTIONDOLong Loop01 Call Progress I-----------+----~____= _____________ _______IDetectIndicates presence of call progress tones. The callprogress detection circuitry is activated by energy inthe 350 to 620 Hz call progress band.3-35

-~--.-.--SSI73K221LCCITT V.22, V.21Single-Chip ModemDETECT REGISTER (Continued)0504 03 02 01 DODR010RECEIVEDATAUNSCR. CARR. ANSWER CALLMARK DETECT TONE PROG.LONGLOOPBIT NO.NAMECONDITIONDESCRIPTION02AnswerToneDetectIndicates detection of 2100 Hz answer tone. Thedevice must be in Originate mode for detection ofanswer tone.03CarrierDetectIndicates carrier has been detected in the receivedchannel.04UnscrambledMarkIndicates detection of unscrambled marks in thereceived data. This may be used in the V.22 connectsequence orfor requesting a remote modem to configureitself for remote digitalloopback. A valid indicationmeans that unscrambled marks have been receivedfor> 165.5 ± 6.5 ms.05ReceiveDataContinuously outputs the received data stream. Thisdata is the same as that output on the RXD pin, but itis not disabled when RXD is tri-stated.TONE REGISTER07 06RXD TRANSMITTR OUTPUT GUARD011 CONTR. TONEBIT NO.NAME00 OTMF 01Guard Tone01 OTMF 1105TRANSMITANSWERTONECONDITION06 04 00X 1 XX 0 0X 0 104 010 00 104 03 02 01 DOTRANSMIT DTMF 11 DTMF 01OTMF OTMF3 OTMF2 OVER- GUAROSPEEODESCRIPTION00 interacts with bits 06, 05, and 04 as shown.Transmit OTMF tones._.._"-----Transmits 1800 Hz guard tone.Transmits 550 Hz guard tone.01 interacts with 04 as shown.Asynchronous OPSK 1200 or 600 bitls +1.0% - 2.5%Asynchronous OPSK 1200 or 600 bitls +2.3% -2.5%.3-36

551 73K221LCCITT V.22, V.21Single-Chip ModemTONE REGISTER (Continued)07 06 05RXO TRANSMIT TRANSMITTR OUTPUT GUARD ANSWER011 CONTR. TONE TONE04 03TRANSMITDTMFDTMF302 01 00DTMF 11 DTMF 01DTMF2 OVER- GUARDSPEEDBIT NO. NAME CONDITION03 02 01 DO03,02, DTMF 3, 0 0 0 0-01, DO 2,1,0 1 1 1 104 Transmit 0DTMF105 Transmit 0AnswerTone1DESCRIPTIONPrograms 1 of 16 DTMF tone pairs that will betransmitted when TX DTM F and TX enable bit (CRO, bit01) is set. Tone encoding is shown below:KEYBOARD DTMF CODE TONESEQUIVALENT 03 02 01 DO LOW HIGH1 0 0 0 1 697 12092 0 0 1 0 697 13363 0 0 1 1 697 14774 0 1 0 0 770 12095 0 1 0 1 770 13366 0 1 1 0 770 14777 0 1 1 1 852 12098 1 0 0 0 852 13369 1 0 0 1 852 14770 1 0 1 0 941 1336* 1 0 1 1 941 1209# 1 1 0 0 941 1477A 1 1 0 1 697 1633B 1 1 1 0 770 1633C 1 1 1 1 852 16330 0 0 0 0----941 1633Disable DTMF.Activates DTMF. The selected DTMF tones are transmittedcontinuously when this bit is high. TX DTMFoverrides all other transmit functions. Modem must bein DPSK mode during DTMF transmission.Disables answer tone generator.Enables answer tone generator. A 2100 Hz answertone will be transmitted continuously when theTransmit Enable bit is set in CRO. The device must bein Answer mode.I3-37

SSI73K221LCCITI V.22, V.21Single-Chip ModemTONE REGISTER (Continued)07 06RXO TRANSMITTR OUTPUT GUARD011 CONTR. TONEBIT NO.NAME06 TX Guard0710 REGISTER(TransmitGuard Tone)RXO OutputControl05TRANSMITANSWERTONECONDITION010104 03 02 01 DOTRANSMIT OTMF 11 OTMF 01OTMF OTMF3 OTMF2 OVER- GUARDSPEEDDESCRIPTIONDisables guard tone generator.Enables guard tone generator (See DO forselection of guard tones}.Enables RXO pin. Receive data will be output onRXO.Disables RXO pin. The RXO pin becomes a highimpedance with internal weak pull-up resistor.101100710061005100410BIT NO.NAMECONDITIONDESCRIPTION07.06.05 Device04 IdentificationSignature07 06 05 04Indicates Device:~----------1-------------------------------------~3-38

----~-----SSI73K221LCCITT V.22, V.21Single-Chip ModemELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETERRATINGVDD Supply Voltage 14Storage Temperature -65 to 150Soldering Temperature (10 sec.) 260Applied Voltage-0.3 to VDD+0.3--~ .. ---UNITV°C°C- --~~-~----VNote: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITSVDD Supply voltage 4.5 5 5.5 VTA, Operating Free-Air -40 +85 °CTemperatureClock Variation (11.0592 MHz) Crystal or -0.01 +0.01 %external clock----- -External Components (Refer to Application section for placement.)VREF Bypass Capacitor (External to GND) 0.1 ~F-----Bias setting resistor (Placed between VDD 1.8 2 2.2 MQand ISET pins)ISET Bypass Capacitor (ISET pin to GND) 0.1 ~F--".VDD Bypass Capacitor 1 (External to GND) 0.1 ~FVDD Bypass CapaCitor 2 (External to GND) 22 ~FXTL 1 Load CapaCitor Depends on crystal characteristics;---_.--_.40 pFXTL2 Load CapaCitor from pin to GND 20--_.. _--•3-39

SSI73K221LCClll V.22, V.21Single-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VOO = recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN100, Supply Current ISET Resistor = 2 MQ100A, Active ClK = 11.0592 MHz1001, Power-down ClK = 11.0592 MHzIOD2, Power-down ClK = 19.200 KHzDigital InputsVIH, Input High VoltageReset, XTl1 , XTL2 3.0All other inputs 2.0Vll, Input low Voltage 0IIH, Input High Current VI = VIH MaxIll, Input low Current VI = Vil Min -200Reset Pull-down Current Reset = VOO 1I nput CapacitanceAll Digital Input PinsDigital OutputsVOH, Output High Voltage 10H MIN = -0.4 mA 2.4VOL, Output low Voltage 10 MAX = 1.6 mAVOL, ClK Output10=3.6mARXD Tri-State Pull-up Curro RXO = GNO -1CMAX, ClK OutputMaximum Capacitive loadNOM MAX UNITS8 12 mA---------~f-------1-----_.-4 mA3 mAVOOVOOVV0.8 V100 f.!Af.!A50 f.!A10 pFVOOV0.4 V0.6 V-50 f.!A15 pF3-40

SSI73K221LCCITT V.22, V.21Single-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)PARAMETERS CONDITIONS MIN NOM MAX UNITSPSK ModulatorCarrier Suppression Measured at TXA 55l_-~:]Output Amplitude TX scrambled marks -11 -9 dBmOFSK Mod/DemodOutput Freq. Error ClK = 11.0592 MHz -0.35 + 0.35 %Transmit level Transmit Dotting Pattern -11 -10 -9 dBmOHarmonic Distortion TH D in the alternate band -60 -50 dBin 700-2900 Hz band DPSK or FSKdBIOutput Bias Distortion Transmit Dotting Pattern ±8%InAlB@ RXDTotal Output Jitter Random Input in ALB @ RXD -15----_._-.+15 %DTMF Generator (Modem must be in DPSK mode to meet specifications)Freq. Accuracy - 0.25 + 0.25 %------_..Output Amplitude low Group, DPSK Mode -10 -9 -8 dBmOOutput Amplitude High Group, DPSK Mode -8 -7 -6 dBmOTwist High-Group to low-Group 1.0 2.0 3.0 dBLong Loop Detect DPSK or FSK -38 -28 dBmODynamic Range Refer to Performance Curves 45 dBCall Prog ress DetectorDetect level 2-Tones in 350-600 Hz band -34 0 dBmOReject level 2-Tones in 350-600 Hz band -41 dBmODelay Time -70 dBmO to -30 dBmO STEP 27 80 msHold Time -30 dBmO to -70 dBmO STEP 27 80 ms-~---"- --Hysteresis 2 dBNote:Parameters expressed in dBmO refer to the following definition:5V Versiono dB loss in the Transmit path to the line.2 dB gain in the Receive path from the line.Refer to the Basic Box Modem diagram in the Applications section for the DAA design.3-41

SSI73K221LCCITT V.22, V.21Single-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMINNOM MAX UNITSCarrier DetectThresholdDelay TimeHysteresisHold TimeAnswer Tone DetectorDPSK or FSK receive data-70 dBmO to -30 dBmO STEPSingle tone detected-30 dBmO to -70 dBmO STEP-49152103°f:dBmOmsdBmsDetect LevelDelay TimeHold TimeNot in V.21 mode-70 dBmO to -30 dBmO STEP-30 dBmO to -70 dBmO STEP-49.52010J :~dBmOmsmsDetect Freq. Range-2.5+2.5 %Output Smoothing FilterOutput loadTXA pin; FSK Single10knTone out for THO = -50 dbin 0.3 to 3.4 KHz50 pFSpurious Freq. CompoFrequency = 76.8 kHz-39 dBmOFrequency = 153.6 kHz-45 dBmOOutput ImpedanceTXA pin200 300 nClock NoiseTXA pin; 76.8 kHz1.0 mVmsCarrierVCOCapture RangeCapture TimeRecovered ClockOriginate or Answer-10 Hz to +10 Hz CarrierFrequency Change-10J+10 Hz40 100 msCapture RangeData Delay TimeAnalog data in at RXA pin toreceive data valid at RXD pin-625+625 ppm1--30 50 ms3-42

~ -SSI73K221LCCITT V.22, V.21Single-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERS CONDITIONS MINGuard Tone GeneratorTone Accuracy 550 or 1800 Hz -20Tone Level 550 Hz -4.0(Below DPSK Output) 1800 Hz -7.0Harmonic Distortion550 Hz700 to 2900 Hz 1800 HzTiming (Refer to Timing Diagrams)TAL CSI Addr. se!up before ALE low 30TLA CS/Addr. hold after ALE low 20TLC ALE low to RD/WR low 40TCL RD/WR Control to ALE high 10NOM MAX UNITS+20 Hz-3.0 -2.0 dB-6.0 -5.0 dB-50 dBTRD Data out from RD low 0------ - ---160 nsTLL ALE width 60 ns------ --------- ---.------- --60 dBTRDF Data float af~er RD high 0 80 nsTRW RDwidth 200 25000 nsTWW WRwidth 140 25000* ns-----TOW Data setue}~~!.ore WR high 150 nsTWO Data hold aft~r WR high 20 nsTCKD Data out after EXCLK low 200 ns"-_ ... -.TCKW WR after EXCLK low 150 ns-.----_. - --TDCK Data setup before EXCLK low 150 ns----~TAC Address setup before control** 50 ns------TCA Address hold after control** 50--nsTWH Data hold after EXCLK 150 ns-------- ----* Maximum time applies to parallel version only.-"----- -----~------** Control for setup is the falling edge of RD or WR.Control for hold is the falling edge of RD or the rising edge of WR.-----nsnsnsnsI3-43

SSI73K221LCCITT V.22, V.21Single-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE~TLC TRW TCLAD~r--'r-WRADO-AD?rTLC .L TWW J4-TLA TRD TRDFI.~DTAL TDW .J.'.I ~ ~---K ADDRESS ~ READ DATA ~ ADDRESS ~TA)tcs~- -~- -i- -J-READ TIMING DIAGRAM (SERIAL VERSION)EXCLKRDI LI'-----+---------------rAO-A2::.-,r------+------------------------j-------DATA --+WRITE TIMING DIAGRAM (SERIAL VERSION)EXCLK__ t--______________ -t--------\HTWWAO-A2 -----+--------------------TCKWI L~ /TCADATA3-44

SSI73K221LCCITT V.22, V.21Single-Chip ModemAPPLICATIONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK-Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a DAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes. Two typical DMarrangements are shown: one for a split ±5 or ±12 voltdesign and one for a single 5 volt design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one for a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039/48 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontrollers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the Serial mode, as explained in the datasheet pin description.In most applications the controllerwill monitor the serialdata for commands from the DTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent over the sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.ICl390pFCA H>-+-,",=,,~CB '"""'-~.----;CC ........ ~-r--=--;CD H>-+-=~WRALEcsSSIK-SERIESLOWPOWERFAMILYBA 1>11--'.:.:::'--+---+-t--t----;----jBB01.DODBus. usMC145406JVRIMOVV250L2022KFIGURE 1: Basic Box Modem with Dual-Supply Hybrid3-45

SSI73K221LCCITT V.22, V.21Single-Chip ModemDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp bybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing at the transformer, making the transmitsignal Common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This circuit(Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a single 5 volt supply. BecauseDTMF tones utilize a higher amplitude than data, theseSignals will clip if a single-ended drive approach isused. The bridged driver uses an extra op-amp (U1 A)to invert the signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-C}.mp then supplies half the drive signalto the transformer. The receive amplifier (U1 C) picksoff its signal at the junction of the impedance matchingresistor and the transformer. Because the bottom leg ofthe transformer is being driven in one direction by U1 Aand the resistor is driven in the opposite direction at thesame time by U1 B, the junction of the transformer andresistor remains relatively constant and the receivesignal is unaffected.DESIGN CONSIDERATIONSSilicon Systems 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.Cl390pF'C30.1 nF~I--------______ ---1RING ~--------------------------~FIGURE 2: Single 5V Hybrid Version3-46

SSI73K221LCCITT V.22, V.21Single-Chip ModemUnlike digital logic circuitry, however, modem designsmust properly contend with precise frequency tolerancesand very low level analog signals, to ensureacceptable performance. Using good analog circuitdesign practices will generally result in a sound design.Following are additional recommendations whichshould be taken into consideration when starting newdesigns.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a Parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01% accuracy.I n order for a Paralle I mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LA YOUT CONSIDERATIONSGood analogldigital design rules must be used tocontrol system noise in orderto obtain highest performancein modem designs. The more digital circuitrypresent on the PC board, the more this attention tonoise control is needed. The modem should be treatedas a high impedance analog device. A 22 mF electrolyticcapacitor in parallel with a 0.1 mF ceramic capacitorbetween VDD and GND is recommended. Liberaluse of ground planes and larger traces on power andground are also highly favored. High speed digitalcircuits tend to generate a significant amount of EMI(Electro-Magnetic Interference) which must be minimizedin order to meet regulatory agency limitations.To accomplish this, high speed digital devices shouldbe locally bypassed, and the telephone line interfaceand K-Series device should be located close to eachother near the area of the board where the phone lineconnection is accessed. To avoid problems, powersupply and ground traces should be routed separatelyto the analog and digital functions on the board, anddigital signals should not be routed near low level orhigh impedance analog traces. The analog and digitalgrounds should only connect at one point near the K­Series device grou nd pin to avoid ground loops. The K­Series modem IC's should have both high frequencyand low frequency bypassing as close to the packageas possible.3-47MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line simulator, operatingunder computer control. A" tests were run fu"­duplex, using a Concord Data Systems 224 as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and a" signal-to-noise (SIN) ratios reflecttotal power measurements similar to the CCITT V.56measurement specification. The individual tests aredefined as follows.BER vs. SINThis test measures the ability of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a DPSK modem will exhibitbetter BER-performance test curves receiving in thelow band than in the high band.BER vs. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamicrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels. The width of the "bowl" ofthese curves, taken at the BER point, is the measure ofdynamic range.I

SSI73K221LCCITT V.22, V.21Single-Chip Modem·SS173K221LBER vs SIGNAL TO NOISE10- 2 1 HIGH BAND RECEIVE ~-40dBm\ 1 DPSK OPERATION\ ,.......L..,10-3 \ \~ ~~600 \'1\ 1 BPS r--C2I~ k\- f--\,\\ ~~ H-~C1or3002....--.----,~ f\ 'c2 '\ ~~ ~10-4 r-- ~ r--\ \ \\1'"" K,Cl or300~ I\'l\~\ r ~ \ \\10- 5 \ ,\ \\1\\,\ 'l1 '1\ \1\ 1111\10- 6 1 \ 1 \ \ 1\2 4 6 8 10 12 14SIGNAL TO NOISE (dB)·SSI 73K221 LBER vs CARRIER OFFSET10- 2 I HIGH BAND RECEIVE ~I DPSK OPERATION10- 310-410- 5300211.8dB SINI C211.3dBSlN1\\ l- I--,.....l-- I- t! I-- 1--1-l-I-- I-"'r-10- 6 12 8 4 0 -4 -8 -12CARRIER OFFSET (HZ)·SSI 73K221 LBER vs RECEIVE LEVEL10- 2 1 HIGH BAND RECEIVE ~DPSK OPERATIONI C2L1NE10-2·SS173K221LBER vs PHASE JITTERr HIGH BAND RECEIVE J-I DPSK OPERATION10-310-310-410-5SlN~ 10_8 dB\ V10-4 :-- ~ 300211.5dB SINr--f\.V..... l/ :c-: ./10-5 I--:::::: ~ ~ I-- \L! L C210.8dB SIN J f--f--SlN-15dB10- 6 I I10 0 -10 -20 -30 -40 -50RECEIVE LEVEL (dBm)10- 6 0 4 8 12 16 20 24PHASE JITTER (0 PEAK)• "EO On" Indicates bit CR1 04 is set for additional phase equalization.3-48

551 73K221LCCITT V.22, V.21Single-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.GNDXTl1AlRXAVREFRESETISETRXCLKRXDTXDEXCLKCLKXTL1XTL2ADOAD1AD2AD3AD4ADSADSAD7GNDRXAVREFRESETISETRXCLKRXDTXDCSEXCLKTXCLK4 3 2 128272650= 2524PLCC PINOUTS 23ARE THE SAME AS 22THE 28-PIN DIP 21ITXCLKALEINT10 20RDtNTWRTXA11 19VDDTXARDVDD12 13 14 15 16 17 18400-Mil22-Pln DIP600-Mil28-Pin DIP28-PinPLCCORDERING INFORMATIONPART DESCRIPTIONSSI 73K221 L with Parallel Bus Interface28-Pin DIP28-Pin PLCCSSI 73K212L with Serial Interface22-Pin DIPORDER NO.73K221L -IP73K221L -IH73K221 SL - IPPKG.MARK73K221L -IP73K221L-IH73K221 SL - IPNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the rightto make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify thatthe data sheetis current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69140194 - rev.3-49Protected by the following Patents (4,691,172) (4,777,453)©1989 Silicon Systems, Inc.

Notes:3-50

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemJanuary 1994DESCRIPTIONThe 551 73K222L is a highly integrated single-chipmodem IC which provides the functions needed toconstruct a CCITT V.22, V.21 and Bell 212A compatiblemodem, capable of 1200 bitls full-duplex operationover dial-up lines. The 551 73K222L is an enhancementof the 551 73K212L single-chip modemwhich adds V.22 and V.21 modes to the Bell 212A and103 operation of the 551 73K212L. In Bell212A mode,the 551 73K222L provides the normal Bell 212A and103 functions and employs a 2225 Hz answer tone.The 551 73K222L in V.22 mode produces either 550 or1800 Hz guard tone, recognizes and generates a2100 Hz answer tone, and allows 600 bitls V.22 or0-300 bitls V.21 operation. The 551 73K222L integratesanalog, digital, and switched-capacitor arrayfunctions on a single substrate, offering excellent performanceand a high level of functional integration in asingle 28- or 22-pin DIP configuration. The551 73K222L operates from a single +5V supply.The 551 73K222L includes the DP5K and F5K modulator/demodulatorfunctions, call progress and handshaketone monitor and a tone generator capable of(Continued)FEATURESOne-chip CCITT V.22, V.21, Bell 212A and 103standard compatible modem data pumpFull-duplex operation at 0-300 bltls (FSK) or 600 and1200 bltls (OPSK)Pin and software compatible with otherSSI K-Series 1-chip modemsInterfaces directly with standard microprocessors(8048, 80C51 typical)Serial or parallel microprocessor bus for controlSerial port for data transferBoth synchronous and asynchronous modes ofoperation including V.22 extended overspeedCall progress, carrier, precise answer tone (2100 or2225 Hz), and long loop detectorsOTMF, and 550 or 1800 Hz guard tone generatorsTest modes available: ALB, OL, ROL, Mark, Space,Alternating bit patternsPrecise automatic gain control allows 45 dBdynamic rangeCMOS technology for low power consumption using30mW@5VSingle +5 volt supplyIBLOCK DIAGRAMPIN DIAGRAMADO-AD7RD:~ g::=:::lcsRESETRXARESETINT 0-----1TXD o--------.-tRXD 0---------1AD4AD5ADSAD7ALEWRRDCAUTION: Use handling procedures necessaryfor a static sensitive component.0194 - rev.3-51

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemDESCRIPTION (Continued)tone required for European applications. This devicesupports V.22 (except mode v) and V. 21 modes ofoperation, allowing both synchronous and asynchronouscommunications. Test features such as analogloop, digital loop, and remote digital loopback aresupported. Internal pattern generators are alsoincluded for self-testing. The SSI73K222L is designedto appearto the systems designer as a microprocessorperipheral, and will easily interface with popularone-chip microprocessors (80C51 typical) for controlof modem functions through its 8-bit multiplexedaddressldata bus or serial control bus. An ALE controlline simplifies address demultiplexing. Data communicationsoccurs through a separate serial port only.The SSI73K222L is ideal for use in either free standingor integral system modem products where full-duplex1200 bitls data communications over the 2-wireswitched telephone network is desired. Its high functionality,low power consumption and efficient packagingsimplify design requirements and increase systemreliability. A complete modem requires only the additionof the phone line interface, a control microprocessor,and RS-232 level converter for a typical system.The SSI 73K222L is part of Silicon Systems' K-Seriesfamily of pin and function compatible single-chipmodem products. These devices allow systems to beconfigured for higher speeds and Bell or CCITT operationwith only a single component change.OPERATIONASYNCHRONOUS MODEData transmission for the DPSK mode requires thatdata ultimately be transmitted in a synchronous fashion.The SSI 73K222L includes ASYNC/SYNC andSYNC/ASYNC converters which delete or insert stopbits in order to transmit data within a ±0.01% rate. Inasynchronous mode the serial data comes from theTXD pin into the ASYNC/SYNC converter. TheASYNC/SYNC converter accepts the data provided onthe TXD pin which normally must be 1200 or 600 bitls+ 1.0%, -2.5%. The converter will then insert or deletestop bits in orderto output a signal which is 1200 or 600bitls ± 0.01 % (± 0.01 % is required synchronous datarate accuracy).The serial data stream from the ASYNC/SYNC converteris passed through the data scrambler and ontothe analog modulator. The data scrambler can bebypassed under processor control when unscrambleddata must be transmitted. The ASYNC/SYNC converterand the data scrambler are bypassed in all FSKmodes. If serial input data contains a break signalthrough one character (including start and stop bits) thebreak will be extended to at least 2 • N + 3 bits long(where N is the number of transmitted bits/character).Serial data from the demodulator is passed firstthrough the data descrambler and then through theSYNC/ASYNC converter. The SYNC/ASYNC convertorwill reinsert any deleted stop bits and transmitoutput data at an intra-character rate (bit-to-bit timing)of no greater than 1219 bit/so An incoming break signal(low through two characters) will be passed throughwithout incorrectly inserting a stop bit.The SYNC/ASYNG converter also has an extendedoverspeed mode which allows selection of anoverspeed range of either +1% or +2.3%. In the extendedoverspeed mode, stop bits are output at 7/8 thenormal width.SYNCHRONOUS MODEThe CCITT V.22 standard defines synchronous operationat 600 and 1200 bit/so The Bell 212A standarddefines synchronous operation only at 1200 bit/soOperation is similar to that of the asynchronous modeexcept that data must be synchronized to a providedclock and no variation in data transfer rate is allowable.Serial input data appearing at TXD must be valid on therising edge of TXCLK.TXCLK is an internally derived signal in internal modeand is connected internally to the RXCLK pin in slavemode. Receive data at the RXD pin is clocked out onthe falling edge of RXCLK. The ASYNCH/SYNCHconverter is bypassed when synchronous mode isselected and data is transmitted out at the same rate asit is input.DPSK MODULATOR/DEMODULATORThe SSI 73K222L modulates a serial bit stream intodi-bit pairs that are represented by four possible phaseshifts as prescribed by the Be1l212AorV.22 standards.The baseband signal is then filtered to reduce intersymbolinterference on the band limited 2-wire3-52

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip Modemtelephone line. Transmission occurs using either a1200 Hz (originate mode) or 2400 Hz carrier (answermode). Demodulation is the reverse of the modulationprocess, with the incoming analog signal even~uallrdecoded into di-bits and converted back to a senal bitstream. The demodulator also recovers the clockwhich was encoded into the analog signal duringmodulation. Demodulation occurs using either a1200 Hz carrier (answer mode or ALB originate mode)or a 2400 Hz carrier (originate mode or ALB answermode). The SSI 73K222L uses a phase locked loopcoherent demodulation technique for optimumreceiver performance.FSK MODULATOR/DEMODULATORThe FSK modulator produces a frequency modulatedanalog output signal using two discrete frequencies torepresent the binary data. In Bell 103, the standardfrequencies of 1270 and 1070 Hz (originate, mark andspace) or 2225 and 2025 Hz (answer, mark and space)are used. V.21 mode uses 980 and 1180 Hz (originate,mark and space), or 1650 and 1850Hz (answer, markand space). Demodulation involves detecting the receivedfrequencies and decoding them into theappropriate binary value. The rate converter andscrambler/descrambler are bypassed in the 103 orV.21 modes .. PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and provide compromise delay equalizationand rejection of out-of-band signals in thereceive channel. Amplitude and phase equalizationare necessary to compensate for distortion of thetransmission line and to reduce intersymbol interferencein the bandlimited receive signal. The transmitsignal filtering approximates a 75% square root ofraised Cosine frequency response characteristic.AGCThe automatic gain control maintains a signal level atthe input to the demodulators which is constant towithin 1 dB. It corrects quickly for increases in signalwhich would cause clipping and provides a totalreceiver dynamic range of >45 dB.PARALLEL BUS INTERFACEFour 8-bit registers are provided for control, optionselect and status monitoring. These registers are addressedwith the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as four consecutive memory locations.Two control registers and the tone register areread/write memory. The detect register is read only andcannot be modified except by modem response tomonitored parameters.SERIAL COMMAND INTERFACEThe serial command interface allows access to theSSI 73K222L control and status registers via a serialcommand port (22-pin version only). In this mode theAO ,A 1 and A21ines provide register addresses for datapassed through the data pin under control of the RDand WR lines. A read operation is initiated when the RDline is taken low. The first bit is available after RD isbrought low and the next seven cycles of EXCLK willthen transfer out seven bits of the selected addressLSB first. A write takes place by shifting in eight bits ofdata LSB first for eight consecutive cycles of EXCLK.WR is then pulsed low and data transferred into theaddressed register occurs on the rising edge of WR.This interface mode is also supported in the 28-pinpackages. See serial control interface pin description.SPECIAL DETECT CIRCUITRYThe speCial detect circuitry monitors the received a~alogsignal to determine status or presence of car.ner,call-progress tones, answer tone and weak receivedsignal (long loop condition). An unscrambled markrequest signal is also detected when the received dataout of the DPSK demodulator before the descramblerhas been high for 165.5 ms ± 6.5 ms minimum. Theappropriate detect register bit is set when one of theseconditions changes and an interrupt is generated for allpurposes except long loop. The interrupts are disabled(masked) when the enable interrupt bit is set to O.DTMF GENERATORThe DTMF generator will output one of 16 standardtone pairs determined by a 4-bit binary value and TXDTMF mode bit previously loaded into the tone register.Tone generation is initiated when the DTMF mod~is selected using the tone register and the transmitenable (CRO bit D1) is changed from 0 to 1.I3-53

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemPIN DESCRIPTIONPOWERNAME 28-PIN 22-PINGND 28 1VDD 15 11VREF 26 21ISET 24 19TYPEII0IDESCRIPTIONSystem Ground.Power supply input, 5V ±10% (73K222l). Bypass with .1and 22 JlF capacitors to GND.An internally generated reference voltage. Bypass with.1 JlF capacitor to ground.Chip current reference. Sets bias currentforop-amps. Thechip current is set by connecting this pin to VDD through a2 MQ resistor. ISET should be bypassed to GND with a.1 JlF capacitor.PARALLEL MICROPROCESSOR INTERFACEALE 12 - IADO-AD7 4-11 - I/OCS 20 - IClK 1 2 0INT 17 13 0RD 14 - IRESET 25 20 IAddress latch enable. The falling edge of ALE latches theaddress on ADO-AD2 and the chip select on CS.Address/data bus. These bidirectional tri-state multiplexedlines carry information to and from the internalregisters.Chip select. A low on this pin during the falling edge of ALEallows a read cycle or a write cycle to occur. ADO-AD7 willnot be driven and no registers will be written if CS (latched)is not active. The state of CS is latched on the falling edgeof ALE.Output clock. This pin is selectable under processor controlto be either the crystal frequency (for use as a processorclock) or 16 x the data rate for use as a baud rate clock inDPSK modes only. The pin defaults tothe crystal frequencyon reset.I nterrupt. This open drain output signal is used to inform theprocessor that a detect flag has occurred. The processormust then read the detect register to determine whichdetect triggered the interrupt. INT will stay low until the~rocessor reads the detect register or ~oes a full reset.Read. A low requests a read of the SSI 73K222l internalregisters. Data cannot be output unless both RD and thelatched CS are active or low.Reset. An active high signal on this pin will put the chip intoan inactive state. All control register bits (CRO, CR1, Tone)will be reset. The output of the ClK pin will be set to thecrystal frequency. An internal pull down resistor permitspower on reset using a capacitor to VDD.3-54

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemPIN DESCRIPTION (Continued)PARALLEL MICROPROCESSOR INTERFACE (Continued)NAME 28-PIN 22-PIN TYPE DESCRIPTIONWR 13 - I Write. A low on this informs the SSI 73K222L that data isavailable on ADO-AD? for writing into an internal register.Data is latched on the rising edge of WR. No data is writtenunless both WR and the latched CS are low.SERIAL MICROPROCESSOR INTERFACEAO-A2 - 5-7 I Register Address Selection. These lines carry registeraddresses and should be valid during any read or writeoperation.DATA - 8 I/O Serial Control Data. Data for a read/write operation isclocked in or out on the falling edge of the EXCLK pin. Thedirection of data flow is controlled by the RD pin. RD lowoutputs data. RD high inputs data.RD - 10 I Read. A low on this input informs the SSI ?3K222L thatdata or status information is being read by the processor.The falling edge of the RD signal will initiate a read from theaddressed register. The RD signal must continue for eightfalling edges of EXCLK in order to read all eight bits of thereferenced register. Read data is provided LSB first. Datawill not be output unless the RD signal is active.WR - 9 I Write. A low on this input informs the SSI?3K222L that dataor status information has been shifted in through the DATApin and is available for writing to an internal register. Thenormal procedure for a write is to shift in data LSB first onthe DATA pin for eight consecutive falling edges of EXCLKand then to pulse WR low. Data is written on the rising edgeof WR.Note:In the serial, 22-pin version, the pins ADO-AD?, ALE and CS are removed and replaced with thepins; AO, A 1 , A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.The serial control mode is provided in the parallel control versions by tying ALE high and CS low.In this configuration AD? becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,respectively.I3-55

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemPIN DESCRIPTION (Continued)DTE USERNAME 28·PIN 22·PINEXCLK 19 15RXCLK 23 18RXD 22 17TXCLK 18 14TXD 21 16TYPEI000IDESCRIPTIONExternal Clock. This signal is used in synchronous transmissionwhen the external timing option has been selected.In the external timing mode the rising edge of EXCLK isused to strobe synchronous DPSK transmit data applied toon the TXD pin. Also used for serial control interface.Receive Clock. The falling edge of this clock output iscoincident with the transitions in the serial received dataoutput. The rising edge of RXCLK can be used to latch thevalid output data. RXCLK will be valid as long as a carrieris present.Received Data Output. Serial receive data is available onthis pin. The data is always valid on the rising edge ofRXCLK when in synchronous mode. RXD will output constantmarks if no carrier is detected.Transmit Clock. This signal is used in synchronous transmissionto latch serial input data on the TXD pin. Data mustbe provided so that valid data is available on the rising edgeof the TXCLK. The transmit clock is derived from differentsources depending upon the synchronization mode selection.In Internal Mode the clock is generated internally. InExternal Mode TXCLK is phase locked to the EXCLK pin.In Slave Mode TXCLK is phase locked to the RXCLK pin.TXCLK is always active.Transmit Data Input. Serial data fortransmission is appliedon this pin. In synchronous modes, the data must be validon the rising edge of the TXCLK clock. In asynchronousmodes (1200/600 bitls or 300 baud) no clocking is necessary.DPSK data must be 1200/600 bitls +1%, -2.5% or+2.3%, -2.5 % in extended overspeed mode.ANALOG INTERFACE AND OSCILLATORRXA 27 22 ITXA 16 12 0XTL1 2 3 IXTL2 3 4 IReceived modulated analog signal input from the telephoneline interface.Transmit analog output to the telephone line interface.These pins are for the internal crystal oscillator requiringa 11.0592 MHz parallel mode crystal. Load capacitorsshould be connected from XTL 1 and XTL2 to Ground.XTL2 can also be driven from an external clock.3-56

SSI73K222LV.22, V.21, Bell 212ASingle-Chip ModemREGISTER DESCRIPTIONSFour 8-bit internal registers are accessible for controland status monitoring. The registers are accessed inread or write operations by addressing the AO, A 1 andA2 address lines in serial mode, or the ADO, AD1 andAD2 lines in parallel mode. In parallel mode the addresslines are latched by ALE. Register CRO controlsthe method by which data is transferred over the phoneline. CR1 controls the interface between the microprocessorand the SSI 73K222L internal state. DR is adetect register which provides an indication of monitoredmodem status conditions. TR, the tone controlregister, controls the DTMF generator, answer andguard tones and RXD output gate used in the modeminitial connect sequence. All registers are read/writeexcept for DR which is read only. Register control andstatus bits are identified below:REGISTER BIT SUMMARYCRO 000ICONTROLENABLE BYPASS CLK TEST TESTREGISTER CRl 001 DETECT SCRAMBLER CONTROL RESET MODE MODE1 INTERRUPT 0DETECTRECEIVEREGISTER DR 010 DATAUNSCR. CARRIER ANSWER CALL LONGMARKS DETECT TONE PROGRESS LOOPTONECONTROL m 011REGISTERTRANSMITDTMF1!DTMF DTMF3 DTMF2 OVERSPEEDCONTROLREGISTER CR2 1002CONTROLREGISTER CR3 1013IDREGISTER ID 110NOTE:When a register containing reserved controlbits is written into, the reserved bits must beprogrammed as O's.3-57

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemREGISTER ADDRESS TABLE0.1200 Bms DPSK1-600 BITIS DPSKO=BEll 103 FSK1=V.21 FSKOOOO=PWR DOWN0001-INT SYNCH0010=EXT SYNCH0011.SlAVE SYNCH0100-ASYNCH 8 BITSICHAR01 01.ASYNCH 9 BITSICHAR0110_ASYNCH 10 BITSICHAR0111_ASYNCH 11 BITSICHAR1100.FSKO=DISABlETXAOUTPUT1=ENABlETXAOUTPUTO=ANSWER1=ORIGINATEO=XTAl1-16XDATARATE OUTPJJTATClK PIN INDPSKMODEONLY0=2225 Hz A.T.1800 Hz G.T.1=2100 Hz A.T.500 Hz G.T.OOXX-73K212l. 322l. 321l01 XX-73K221l. 302l10XX-73K222l1100=73K224l1110_73K324l11 01 =73K312l3-58

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemCONTROL REGISTER 004 03 0201 DOCROM:~" II r II TRA~~MITTRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/000 UI"' I :i:~, ':i:; :::i: MODE 3 MODE 2 MODE 1 MODE 0 ENABLE ORIGINATEBIT NO. NAME \,;UNUIIIUN Ut:.~I~HI'" IIUNDO Answer/ 0 Selects answer mode (transmit in high band, receiveOriginatein low band).1 Selects originate mode (transmit in low band, receivein high band).01 Transmit 0 ni~;:!hlp.~ transmit outputEnable1 Enables transmit output at TXA.Note: TX Enable must be set to 1 to allow Answer Toneand OTMF Transmiission.05 04 03 0205,04,03, Transmit 0 0 0 0 Selects power down mode. All functions disabled02 Mode except digital interface.0 0 0 1 Internal synchronous mode. In this mode TXCLK is aninternally derived 1200 Hz signal. Serial input dataappearing at TXO must be valid on the rising edge ofTXCLK. Receive data is clocked out of RXO on thefalling edge of RXCLK.0 a 1 a External synchronous mode. Operation is identical tointernal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 1200 Hz ± 0.01 % clock mustbe supplied externally.a a 1 1 Slave synchronous mode. Same operation as othersynchronous modes. TXCLK is connected internally tothe RXCLK pin in this mode.0 1 a a Selects PSK asynchronous mode - 8 bits/character(1 start bit, 6 data bits, 1 stop bit).a 1 0 1 Selects PSK asynchronous mode - 9 bits/character(1 start bit, 7 data bits, 1 stop bit).a 1 1 a Selects PSK asynchronous mode - 10 bits/character(1 start bit, 8 data bits, 1 stop bit).a 1 1 1 Selects PSK asynchronous mode - 11 bits/character(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).I1 1 a a Selects FSK II06 0 Not used; must be written as a "0."3-59

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemCONTROL REGISTER 0 (Continued)CRO MODUL.000 OPTIOND7 D5 D4 D3 02 01 DOTRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 3 MODE 2 MODE 1 MODE 0 ENABLE ORIGINATEBIT NO. NAME CONDITION DESCRIPTIOND7ModulationOptionx = Don't careCONTROL REGISTER 107 06 D5 D4 03 02 01 DOTRANSMIT TRANSMIT ENABLE BYPASS ClK TEST TESTCR1 PATTERN PATTERN DETECT SCRAMB CONTROL RESET MODE MODE001 1 0 INTER. 1 0BIT NO. NAME CONDITION DESCRIPTIOND1 DO01, DO Test Mode 0 0 Selects normal operating mode.0 1 Analog loopback mode. loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same center frequency as the transmitter. Tosquelch the TXA pin, transmit enable must be forcedlow.1 0 Selects remote digital loopback. Received data islooped back to transmit data internally, and RXD isforced to a mark. Data on TXD is ignored.1 1 Selects local digital loopback. Internally loops TXDback to RXD and continues to transmit carrier fromTXApin.D2 Reset 0 Selects normal operation.1 Resets modem to power down state. All controlregister bits (CRO, CR1, Tone) are reset to zero. Theoutput of the ClK pin will be set to the crystalfrequency.03 ClK Control 0 Selects 11.0592 MHz crystal echo output at ClK(Clock Control)pin.1 Selects 16 X the data rate, output arClK pin in DPSKmodes only.3-60

SSI73K222LV.22, V.21, Bell 212ASingle-Chip ModemCONTROL REGISTER 1 (Continued)D7 D6 D5TRANSMIT TRANSMIT ENABLECR1 PATTERN PATTERN DETECT001 1 0 INTER.BIT NO. NAME CONDITIOND4 Bypass 0ScramblerD5 Enable Detect 011D7 D6D7,D6 Transmit 0 0PatternDETECT REGISTER0 11 01 1D4 D3 D2 D1 DOBYPASS ClK TEST TESTSCRAMB CONTROL RESET MODE MODE1 0DESCRIPTIONSelects normal operation. DPSK data is passedthrough scrambler.Selects Scrambler Bypass. Bypass DPSK data isrouted around scrambler in the transmit path.Disables interrupt at INT pin.Enables INT output. An interrupts will be generatedwith a change in status of DR bits D1-D4. The answertone and call progress detect interrupts are maskedwhen the TX enable bit is set. Carrier detect is maskedwhen TX DTMF is activated. All interrupts will bedisabled if the device is in power down mode.Selects normal data transmission as controlled by thestate of the TXD pin.Selects an alternating mark/space transmit pattern formodem testing.Selects a constant mark transmit pattern.Selects a constant space transmit pattern.ID5D4D3D2D1DORECEIVEDATAUNSCR.MARKCARR.DETECTANSWERTONECAllPROG.lONGlOOPBIT NO.NAMECONDITIONDESCRIPTIONDOlong loopD1CallProgressDetectIndicates presence of call progress tones. The callprogress detection circuitry is activated by energy inthe 350 to 620 Hz call progress band.3-61

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemDETECT REGISTER (Continued)05 0403 0201DORECEIVEDATAUNSCR.MARKCARR.DETECTANSWERTONECALLPROG.LONGLOOPBIT NO.NAMECONDITIONDESCRIPTION02030405AnswerToneDetectCarrierDetectUnscrambledMarkDetectReceiveDataIndicates detection of 2225 Hz answer tone in Bellmode or 21 00 Hz in CCITT mode. The device must bein originate mode for detection of answer tone. ForCCITT answer tone detection, bit DO of the ToneR r must be set to a 1.Indicates carrier has been detected in the receivechannel.Indicates detection of unscrambled marks inthe received data. A· valid indication requires thatunscrambled marks be received for> 165.5 ± 6.5 ms.Continuously outputs the received data stream. Thisdata is the same as that output on the RXO pin, but itis not disabled when RXO is tri-stated.TONE REGISTER07 060504 03 02 01 DORXO TRANSMIT TRANSMIT TRANSMIT OTMF 11 OTMF 01TR OUTPUT GUARD ANSWER OTMF OTMF3 OTMF2 OVER- ANSWERI011 CONTR. TONE TONE SPEED GUARDBIT NO. NAME CONDITION DESCRIPTIONDO06 05 04 DO DO interacts with bits 06, OS, and 04 as shown.OTMF 01X X 1 X Transmit OTMF tones.AnswerlGuard Tone X 0 0 0 Detects 2225 Hz in originate mode.X 1 0 0 Transmits 2225 Hz in answer mode (8ell).X 0 0 1 Detects 2100 Hz in originate mode.X 1 0 1 Transmits 2100 Hz in answer mode (CCITT).1 0 0 0 Select 1800 Hz guard tone.1 0 0 1 Select 550 Hz guard tone.04 01 01 interacts with 04 as shown.01 OTMF 11 0 0 Asynchronous OPSK +1.0% -2.5%.Overspeed 0 1 Asynchronous OPSK +2.3% -2.5%.3-62

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemTONE REGISTER07 06 05RXO TRANSMIT TRANSMITTR OUTPUT GUARD ANSWER011 CONTR. TONE TONEBIT NO. NAME CONDITIOND3 D2 D1 DOD3, D2, DTMF 3, 0 0 0 0-D1,DO 2,1,0 1 1 1 1D4 Transmit 0DTMF1D5 D4 DOD5 Transmit 0 0 XAnswerTone1 0 01 0 104 D3 D2 D1 DOTRANSMIT DTMF 11 DTMF 01DTMF DTMF3 DTMF2 OVER- ANSWERISPEED GUARDDESCRIPTIONPrograms 1 of 16 DTMF tone pairs that will betransmitted when TX DTM F and TX enable bit (CRO, bitD1) are set. Tone encoding is shown below:KEYBOARD DTMF CODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGH1 0 0 0 1 697 12092 0 0 1 0 697 13363 0 0 1 1 697 14774 0 1 0 0 770 1209- -5 0 1 0 1 770 13366 0 1 1 0 770 14777 0 1 1 1 852 12098 1 0 0 0 852 13369 1 0 0 1 852 14770 1 0 1 0 941 1336---~* 1 0 1 1 941 1209# 1 1 0 0 941 1477A 1 1 0 1 697 1633B 1 1 1 0 770 1633C 1 1 1 1 852 1633D 0 0 0 0------941 1633Disable DTMF.Activates DTMF. The selected DTMF tones aretransmitted continuously when this bit is high. TXDTMF overrides all other transmit functions.D5 interacts with bits D4 and DO as shown.Disables answer tone generator.Enables answer tone generator. A 2225 Hz answertone will be transmitted continuously when the TransmitEnable bit is set in CRO. The device must be inanswer mode.Likewise a 2100 Hz answer tone will be transmitted.I3-63

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemTONE REGISTER (Continued)07 06RXO TRANSMITTR OUTPUT GUARD011 CONTR. TONE05TRANSMITANSWERTONE04 03 02 01 DOTRANSMIT DTMF 11 DTMF 01DTMF DTMF3 DTMF2 OVER- ANSWERISPEED GUARDBIT NO.NAMECONDITIONDESCRIPTION06TransmitGuard Tone01Disables guard tone generator.Enables guard tone generator (See DO for selectionof guard tones).D7RXD OutputControl0Enables RXD pin. Receive data will be output onRXD.1Disables RXD pin. The RXD pin reverts to a highimpedance with internal weak pull-up resistor.10 REGISTER0706D5D410110IDID1010BIT NO.NAMECONDITIONDESCRIPTIOND7,06 DeviceIdentificationSignatureD7 06 D5 D4Indicates Device:~----------4---------~~------------------------~3-64

-~SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETERVDD Supply VoltageStorage TemperatureSoldering Temperature (10 sec.)Applied VoltageRATING14V-65 to 150°C260°C-0.3 to VDD+0.3V-------------Note: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITSVDD Supply voltage 4.5 5 5.5 VT A, Operating Free-Air -40 +85 °CTemperature----- - ---Clock Variation (11.0592 MHz) Crystal or -0.01 +0.01 %external clockExternal Components (Refer to Application section for placement.)VREF Bypass Capacitor (External to GND) 0.1 IlFBias setting resistor (Placed between VDD 1.8 2 2.2 Mnand ISET pins)ISET Bypass Capacitor (ISET pin to GND) 0.1 IlFVDD Bypass Capacitor 1 (External to GND) 0.1 IlFVDD Bypass Capacitor 2 (External to GND) 22 IlFXTL 1 Load Capacitor Depends on crystal characteristics; 40 pFXTL2 Load Capacitor from pin to GND 20I3-65

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN100, Supply Current ISET Resistor = 2 MnIDDA, ActiveClK = 11.0592 MHz1001, Power-down ClK = 11.0592 MHz1002, Power-down ClK = 19.200 KHzDigital InputsVIH Input Hiah VoltaaeReset, XTl1, XTl2 3.0All other inputs 2.0Vll, Input low Voltage 0IIH, Input High Current VI = VIH MaxIll, Input low Current VI = Vil Min -200Reset Pull-down Current Reset = VDD 1Input CapacitanceAll Digital Input PinsDigital OutputsVOH, Output High Voltage IOH MIN = -0.4 rnA 2.4VOL, Output low Voltage 10 MAX = 1.6 rnAVOL, ClK Output10 = 3.6 rnARXD Tri-State Pull-up Curro RXD = GND -1CMAX, elK OutputMaximum Capacitive loadNOM MAX UNITS--8 12 mA1--VDD-- -4 rnA3 mAVDDVV0.8 V100 J.IAJ.IA50 J.IA10 pFVDDV0.4 V0.6 V-50 J.IA15 pF3-66

~----SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)PARAMETERS CONDITIONS MIN NOM MAX UNITSPSK ModulatorCarrier Suppression Measured at TXA 55-1~o=fOutput Amplitude TX scrambled marks -11 -9 dBmOFSK Mod/DemodOutput Freq. Error ClK = 11.0592 MHz -0.35 +.35 %Transmit level Transmit Dotting Pattern -11 -10.0 -9 dBmOHarmonic Distortion THD in the alternate band -60 -50 dBin 700-2900 Hz band DPSK or FSKdBIOutput Bias Distortion Transmit Dotting Pattern ±8%in ALB@ RXDTotal Output Jitter Random Input in ALB @ RXD -15 +15DTMF GeneratorFreq. Accuracy -.25 +.25 %Output Amplitude low Band, DPSK Mode -10 -9 -8 dBmOOutput Amplitude High Band, DPSK Mode -8 -7 -6 dBmOTwist High-Band to Low-Band, DPSK Mode 1.0 2.0 3.0 dBLong Loop Detect DPSK or FSK -38 -28 dBmO-----Dynamic Range Refer to Performance Curves 45 dB---.~~-.----Call Prog ress Detector---Detect level 2-Tones in 350-600 Hz band -34 0 dBmO-.-.-~Reject level 2-Tones in 350-600 Hz band -41 dBmO--Delay Time -70 dBmO to -30 dBmO STEP 27 80 msHold Time -30 dBmO to -70 dBmO STEP 27 80 msHysteresis 2 dB----Note: Parameters expressed in dBmO refer to the following definition:o dB loss in the Transmit path to the line.2 dB gain in the Receive path from the line.Refer to the Basic Box Modem diagram in the Applications section for the DAA design.%3-67

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCarrier DetectThresholdDelay TimeHysteresisHold TimeAnswer Tone DetectorDetect LevelDelay TimeHold TimeDetect Freq. RangeOutput Smoothing FilterOutput loadSpurious Freq. CompoTXA pin Output ImpedanceClock NoiseCarrlerVCOCapture RangeCapture TimeRecovered ClockCapture RangeData Delay TimeCONDITIONSDPSK or FSKreceive data-70 dBmO to -30 dBmO STEPSingle tone detected-30 dBmO to -70 dBmO STEPNot in V.21 mode-70 dBmO to -30 dBmO STEP-30 dBmO to -70 dBmO STEPTXA pin; FSK SingleTone out for THD = -50 dbin .3 to 3.4 KHzFrequency = 76.8 kHzFrequency = 153.6 kHzTXA pin; 76.8 KHzOriginate or Answer-10 Hz to +10 Hz CarrierFreq. Change Assum.% of frequencycenter frequency(center at 1200 Hz)Analog data in at RXA pin toreceive data valid at RXD pinMIN NOM MAX UNITS-49 -42 dBmO15 45 ms2 3.0 dB10 24 ms-49.5 -42 dBmO20 45 ms10 30 ms-2.5 +2.5 %10 kG50 pF-39 dBmO-45 dBmO200 300 G1.0 mVrms-10 +10 Hz40 100 ms-625 +625 ppm.30 50 ms3-68

-~SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemELECTRICAL SPECIFICATIONS (Continued)DYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSGuard Tone GeneratorTone AccuracyTone level(Below DPSK Output)Harmonic DistortionCONDITIONS550 Hz1800 Hz550 Hz1800 Hz550 Hz700 to 2900 Hz 1800 HzTiming (Refer to Timing Diagrams)TALTLATlCTClTRDTlLTRDFTRWTWWTOWTWOTCKDTCKWTDCKTACTCATWHCS/Addr. setup before ALE LowCSI Addr. hold after ALE LowALE Low to RDIWR LowRD/WR Control to ALE HighData out from RD LowALE widthData float after RD HighRDwidthWRwidthData setup before WR HighData hold after WR HighData out after EXCLK LowWR after EXClK lowData setup before EXClK LowAddress setup before control*Address hold after control*Data Hold after EXCLK* Control for setup is the falling edge of RD or WR.Control for hold is the falling edge of RD or the rising edge of WR.MIN NOM MAX UNITS----- -----------20 +20 Hz-4.0 -3.0----2.0 dB-7.0 -6.0-----5.0 dB-50 dB-----60 dB--,----30 ns20-----c---ns40 ns10 ns0 140 ns60 ns0 200 ns200 25000 ns140 25000 ns150 ns20 ns200 ns----150 ns150 ns50 ns50 ns20I3-69

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE ~:... TlC .. ~ TRWRD -rWRTlATRD1 TCl-,1-TRDFL TAL .tJ ~ ~rTlC.L TWW J+I TWDI~ TOW ~ ~ .~IADO-AD7 --K ADDRESS }---K READ DATA}---K ADDRESS ~~READ TIMING DIAGRAM (SERIAL VERSION)EXClKRDcs ~- -~- -i- -~-~~--------------r-AO-A2DATA --+WRITE TIMING DIAGRAM (SERIAL VERSION)EXClKHTWW-----+--------------------------------------~~TCKW I ~F TACAO-A2. ---+-------------------------\+TCADATA3-70

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemAPPLICATIONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK-Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a DAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes. Two typical DAA arrangementsare shown: one for a split ±5 or ±12volt design and one for a single 5 volt design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one for a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039/48 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontrollers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the serial mode, as explained in the datasheet pin description.In most applications the controller will monitorthe serialdata for commands from the DTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent over the sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.IRS232LEVELCONVERTERSCl390 pFCA '"">-.j....:.!!.:,-----"CB ......... ".,...-~CC ......... ,-.-------,CD H>t-='----1iNAALEC§SSIK·SERIESLOWPOWERFAMILYRXA f..-.----l f.-----~BABBDADODBI~~~--+--t--r-----j

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing at the transformer, making the transmitsignal common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This circuit(Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a single 5V supply. BecauseDTMF tones utilize a higher amplitude than data, thesesignals will clip if a single-ended drive approach isused. The bridged driver uses an extra op-amp (U 1 A)to invert the signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-amp then supplies half the drive signalto the transformer. The receive amplifier (U1 C) picksoff its signal at the junction of the impedance matchingresistor and the transformer. Because the bottom leg ofthe transformer is being driven in one direction by U1 Aand the resistor is driven in the opposite direction at thesame time by U1 B, the junction of the transformer andresistor remains relatively constant and the receivesignal is unaffected.DESIGN CONSIDERATIONSSilicon Systems' 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.Cl390pFR437.4K 1%• C3O.lnF

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemUnlike digital logic circuitry, modem designs mustproperly contend with precise frequency tolerancesand very low level analog signals, to ensure acceptableperformance. Using good analog circuit design practiceswill generally result in a sound design. Followingare additional recommendations which should betaken into consideration when starting new designs.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01% accuracy.In order for a parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LAYOUT CONSIDERATIONSGood analogldigital design rules must be used tocontrol system noise in orderto obtain highest performancein modem designs. The more digital circuitrypresent on the PC board, the more this attention tonoise control is needed. The modem should be treatedas a high impedance analog device. A 22 mF electrolyticcapacitor in parallel with a 0.1 mF ceramic capacitorbetween VDD and GND is recommended. Liberaluse of ground planes and larger traces on power andground are also highly favored. High speed digitalcircuits tend to generate a significant amount of EMI(Electro-Magnetic Interference) which must be minimizedin order to meet regulatory agency limitations.To accomplish this, high speed digital devices shouldbe locally bypassed, and the telephone line interfaceand K-Series device should be located close to eachother near the area of the board where the phone lineconnection is accessed. To avoid problems, powersupply and ground traces should be routed separatelyto the analog and digital functions on the board, anddigital signals should not be routed near low level orhigh impedance analog traces. The analog and digitalgrounds should only connect at one pOint near theK-Series device ground pin to avoid ground loops. TheK-Series modem IC's should have both high frequencyand low frequency bypassing as close to thepackage as possible.MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line Simulator, operatingunder computer control. All tests were run fullduplex,using a Concord Data Systems 224 as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and all signal-to-noise (SIN) ratios reflect 3total power measurements similar to the CCITT V.56measurement specification. The individual tests aredefined as follows.BER vs. SINThis test measures the ability of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a DPSK modem will exhibitbetter BER-performance test curves receiving in thelow band than in the high band.BER vs. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamicrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels. The width of the "bowl" ofthese curves, taken at the BER point, is the measure ofdynamic range.3-73

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip Modem*SSI 73K222LBER vs SIGNAL TO NOISE10- 2 1 HIGH BAND RECEIVE~~dBm\ , DPSK OPERATION\ ---L.10-3 \ \~ I~~600\1\ "I r- BPS C2~ k\- f--\~\ ~~ H'c;';~2~~ rr- ~ \: ~\- H ~10-

SSI73K222LV.22, V.21 , Bell 212ASingle-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.GNDXTL1XTL2A1A2WR 9ADVDDRXAVREFRESETISETRXCLKRXDTXDEXCLKTXCLKjNfTXAClKXTl1XTl2ADOAD1AD2AD3A04ADSAD6AD?ALEWRRDGNDRXAVREFRESETISETRXClKRXDTXDcsEXClKTXClKINTTXAVDD4 3 2 12827262524PlCC PINOUTS 23ARE THE SAME AS 22THE 28-PIN DIP 2110 2011 1912 13 14 15 16 17 18I400-MII22-Pln DIP6OO-MII28-Pin DIP28-PinPLCCORDERING INFORMATIONPART DESCRIPTIONORDER NO.PKG.MARKSSI 73K222L with Parallel Bus Interface28-Pin Dip28-Pin PLCCSSI 73K222L with Serial Interface22-Pin Sip73K222L-IP73K222L-IH73K222SL-IP73K222SL-IC73K222L-IP73K222L-IH73K222SL-IP73K222SL-ICNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69140194 - rev.3-75Protected by the following Patents (4,691,172) (4,777,453)©1989 Silicon Systems, Inc.

Notes:3-76

SSI73K222USingle-Chip Modemwith UARTDecember 1993DESCRIPTIONThe SSI 73K222U is a compact, high-performancemodem which includes a 8250N16C450 compatibleUART with the 1200 bitls modem function on a singlechip. Based on the SSI 73K222L 5V low power CMOSmodem IC, the SSI 73K222U is the perfect modemlUART component for integral modem applications. It isideal for applications such as portable terminals andlaptop computers. The SSI 73K222U is the first fullyfeatured modem IC which can function as an intelligentmodem in integral applications without requiring aseparate dedicated microcontroller. It provides for datacommunication at 1200, 600, and 300 biVs in a multimodemanner that allows operation compatible withboth Bell 212N103 and CCITT V.22N.21 standards.The digital interface section contains a high speedversion of the industrystandard 8250N16C450 UART,commonly used in personal computer products. Aunique feature of the SSI 73K222U is that the UARTsection can be used without the modem function,providing an additional asynchronous port at no addedcost. The 551 73K222U is designed in CMOS teChnologyand operates from a single +5V supply. AvailablepaGkaging includes 40-pin DIP or 44-pin PLCC forsurface mount applications.BLOCK DIAGRAMTXD XTL1 XTL2 ClKFEATURES• Modem/UART combination optimized for integral busapplications• Includes features of SSI 73K222L single-chip modem• Fully compatible 16C450/8250 UART with 8250B or8250A selectable interrupt emulation• High speed UARTwili interface directlywith high clockrate bus with no wait states• Single-port mode allows full modem and UARTcontrolfrom CPU bus, with no dedicated microprocessorrequired• Dual-port mode suits conventional designs using localmicroprocessor for transparent modem operation• Complete modem functions for 1200 bitls (Bell 212A,V.22) and 0-300 bitls (Bell 103, V.21)• Includes DTMF generator, carrier, call-progress andprecise answer-tone detectors for intelligent dialingcapability• On chip 2-wire/4-wire hybrid driver and off-hook relaybuffer• Speaker output with four-level software driven volumecontrol• Low power CMOS (40 mW) with power down mode(15 mW)• Operates from single +5V supplyPIN DIAGRAMIUDOUDIUD2UD3UD4UDSUD6UD7UAOUAIUA2DOSTRDISTRC528250A I 16C450UARTTXAlTXA2RXASPKRf-...'-----4-1 (CTS)! MAOf------+i (DSR)! MAt1------4-.. (UA3) !MA21------4-1 DATA!(DTR)RD!(ADS)WR!(N!C)1------4-1 (DCD)!DClKf------+i (RTS)!iNf>----1-... OHRELAYDRIVERINTRPT (Ai) J1f'RST RESET RXD VDD VREF GND ISET STNDlN1293- rev. 3-77Parentheses indicate single·port mode.CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI73K222USingle-Chip Modemwith UARTFUNCTIONAL DESCRIPTIONThe 551 73K222U integrates an industry standard8250/16C450 UART fu nction with the modem capabilityprovided by the 551 73K222l single chip modem IC.The 551 73K222U is designed specifically for integralmicroprocessor bus intelligent modem products. Thesedesigns typically require the standard 8250 or higherspeed 16450 UART to perform parallel-to-serial andserial-to-parallel conversion process necessary to interfacea parallel bus with the inherently serial modemfunction. The 551 73K222U provides a highly integrateddesign which can eliminate multiple componentsin any integral bus modem application, and isideal for internal PC modem applications.The 551 73K222U includes two possible operatingmodes. In the dual-port mode, the device is suitable forconventional plug-in modem card designs which use aseparate local microprocessor for command interpretationand control of the modem function. In this mode,a dedicated microcontroller communicates with the551 73K222U using a separate serial command port.In the single-port mode the main CPU can control boththe UART and modem function using the parallel databus.This allows very efficient modem design with nolocal microprocessor required for dedicated applicationssuch as laptop PC's or specialized terminals.To make designs more space effiCient, the551 73K222U includes the 2-wire to 4-wire hybriddrivers, off-hook relay -driver, and an audio monitoroutput with software volume control for audible callprogress monitoring. As an added feature the UARTfunction can be used independent of the modem function,providing an added asynchronous port in a typicalPC application with no additional circuitry required.UART FUNCTION (16C450)The UART section of the 551 73K222U is completelycompatible with the industry standard 16C450 and the8250 UART devices. The bus interface is identical tothe 16450, except that only a single polarity for thecontrol signals is supported. The register contents andaddresses are also the same as the 16C450. To insurecompatibility with all existing releases of the 8250UART deSign, external Circuitry normally used in PCapplications to emulate 8250B or 8250A interrupt operationhas been included on the 551 73K222U.A select line is then provided to enable the desiredinterrupt operation. The UART used in the551 73K222U can be used with faster bus read andwrite cycles than a conventional 16C450 UART. Thisallows it to interface directly with higher clock ratemicroprocessors with no need for external circuitry togenerate wait states.The primary function of the UARTis to perform parallelto-serialconversion on data received from the CPUand serial-to-parallel conversion on data received fromthe internal modem or an external device. The UARTcan program the numberof bits per character, parity bitgeneration and checking, and the number of stop bits.The UART also provides break generation and detection,detection of error conditions, and reporting ofstatus at any time. A prioritized maskable interrupt isalso provided.The UART block has a progammable baud rate generatorwhich divides an internal 1.8432 MHz clock togenerate a clock at 16x the data rate. The data rate forthe transmit and receive sections must be the same.For DPSK modulation, the data rate must be 1200 Hzor 600 Hz. For F5K modulation, the data rate must be300 Hz or less. The baud generator can create a clockthat supports digital transfer at up to 115.2 kHz. Theoutput of the baud generator can be made available atthe ClK pin under program control.MODEM FUNCTION (881 73K222L)The modem section of the SSI 73K222U provides allnecessary analog functions required to create a singlechip Bell 212A1103 and CCID V.22IV.21 modem,controlled by the system CPU or a local dedicatedmicroprocessor. Asynchronous 1200 bitls DPSK (Bell212A and V.22) and 300 baud FSK (Bell 1 03 and V.21)modes are supported.The modem portion acts as a peripheral to the microprocessor.In both modes of operation, control informationis stored in register memory at specific addresslocations. Inthe single-port mode, the modem sectioncan be controlled through the 16C450 interface, withno external microcontroller required. The primary analogblocks are the DPSK modulator/demodulator, theFSK modulator/demodulator, the high and low bandfilters, the AGC, the special detect circuitry, and theDTMF tone ge!1erator. The analog functions are performedwith switched capacitor technology.3-78

SSI73K222USingle-Chip Modemwith UARTPSK MODULATOR / DEMODULATORThe SSI 73K222U modulates a serial bit stream intodibit pairs that are represented by four possible phaseshifts as prescribed by the Bell 212A or V.22 standard.The baseband signal is then filtered to reduce intersymbolinterference on the band limited 2-wire PSTNline. Transmission occurs using either a 1200 Hz(originate mode) or 2400 Hz carrier (answer mode).Demodulation is the reverse of the modulation process,with the incoming analog signal eventually decodedinto dibits and converted back to a serial bitstream. The demodulator also recovers the clock whichwas encoded into the analog signal during modulation.The demodulator decodes either a 1200 Hz carrier(originate carrier) or a 2400 Hz carrier (answer carrier).The SSI 73K222U uses a phase-locked-loop coherentdemodulation technique that offers inherently betterperformance than typical DPSK demodulators used byother manufacturers.FSK MODULATOR/DEMODULATORThe FSK modulator frequency modulates the analogoutput signal using two discrete frequencies to representthe binary data. In Bell 1 03, the standard frequenciesof 1270 Hz and 1070 Hz (originate mark andspace) and 2225Hz and 2025 Hz (answer mark andspace) are used. V.21 mode uses 980 Hz and 1180 Hz(originate, mark and space) or 1650 Hz and 1850 Hz(answer, mark and space). Demodulation involvesdetecting the received frequencies and decoding theminto the appropriate binary value.PASSBAND FILTERS AND EQUALIZERSA high and low band filter is included to shape theamplitude and phase response of the transmit signaland provide compromise delay equalization and rejectionof out-of-band signals in the receive channel.Amplitude and phase equalization is necessary tocompensate for distortion of the transmission line andto reduce intersymbol interference in the band limitedreceive signal. The transmit signal filtering approximatesa 75% square root of raised Cosine frequencyresponse characteristic.AGCThe automatic gain control maintains a signal level atthe input to the demodulators which is constant towithin 1 dB. It corrects quickly for increases in signalwhich would cause clipping, and provides a totaldynamic range of >45 dB.3-79SPECIAL DETECT CIRCUITRYThe special detect circuitry monitors the received analogsignal to determine status or presence of carrier,call-progress tones, answer tone, and weak receivedsignal (long loop condition). An unscrambled marksignal is also detected when the received data out ofthe DPSK demodulator before the descrambler hasbeen high for 165.5 mS ±13.5 mS. The appropriatestatus bit is set when one of these conditions changesand an interrupt is generated for all monitored conditionsexcept long loop. The interrupts are disabled(masked) when the enable interrupt bit is set to a O.DTMF GENERATORThe DTMF generator will output one of 16 standarddual-tones determined by a 4-bit binary value and TXDTMF mode bit previously loaded into the tone register.Tone generation is initiated when the DTMF modeis selected and the transmit enable (CRO bit 01) ischanged from a 0 to a 1.TEST FEATURESTest features such as analog loopback (ALB), remotedigital loopback, local digital loopback, and internalpattern generators are also included.LINE INTERFACEThe line interface ofthe SSI73K222U consists of a twoto-fourwire hybrid, and an off-hook relay driver.The two-to-four wire converter has a differential transmitoutput and requires only a line transformer and anexternal impedance matching resistor. Four-wireoperation is also available by simply using either of thetransmit output signals.The relay driver output of the SSI 73K222U is an opendrain signal capable of sinking 20 mA, which cancontrol a line closu re relay used to take the line off hookand to perform pulse dialing.AUDIO MONITORAn audio monitor output is provided which has asoftware programmable volume control. Its output isthe received signal. The audio monitor output candirectly drive a high impedance load, but an externalpower amplifier is necessary to drive a low-impedanceI

SSI73K222USingle-Chip Modemwith UARTPIN DESCRIPTIONGENERALNAME DIP PLCCTYPEDESCRIPTIONVDD 40 44GND 20 22VREF 19 21ISET 9 11XTL1 25 27XTl2 24 26ClK 21 23RESET 10 12STNDlN 15 17I +5V Supply ±1 0%, bypass with a .1 and a 22JlF capacitortoGNDI System Ground0 VREF is an internally generated reference voltage which isexternally bypassed by a 0.1 f,lF capacitor to the systemground.I The analog current is set by connecting this pin to VDDthrough a 2 Mn resistor. ISET should be bypassed to GN D.Alternatively, an internal bias can be selected by connectingISET to GND, which will result in a larger worst-casesupply current due to the tolerance of on-chip resistors.Bypass with .1 f,lF capacitpr if resistor is used.I These pins are connections for the internal crystaloscillator requiring an 11.0592 MHz crystal (9216Hz xI1200). XTl2can also be TIL driven from an external clock.0 Output Clock. This pin is selectable under processor controlto be either the crystal frequency (which might be usedas a processor clock) or the output of the baud generator.I Reset. An active signal (high) on this pin will put the chip intoan inactive state. The control register bits (except theReceiver Buffer, Transmitter Holding, and Divisor latches)will be reset. The output of the ClK pin will be set to thecrystal frequency. An internal pull-down resistor permitspower-on reset using a 0.1 JlF capacitor connected to the5V supply.I Single-port mode select (active high). In a single-portsystem there is no local microprocessor and all the modemcontrol is done through the 16C450 parallel bus interface.The local microprocessor interface is replaced with UARTcontrol signals which allow the device to function as a digitalUART as well as modem.3-80

SSI73K222USingle-Chip Modemwith UARTPIN DESCRIPTION (continued)UART INTERFACENAME DIP PLCC TYPEUAO-UA2 37-39 41-43 IUA3 12 14 IUDO-UD7 27-34 30-37 1/0DISTR 35 38 IDOSTR 36 39 ICS2 1 2 IINTRPT 5 7 0RXD 6 8 1/0DESCRIPTIONUART Address. These pins determine which of the UARTregisters is being selected during a read or write on theUART data bus. The contents of the DLAB bit in theUART's Line Control Register also control which register isreferenced. In single-port mode, UAO-UA3 are latchedwhen ADS goes high. In dual-port, only UAO-UA2 areused.(3 state) UART Data. Data or control information to theUART registers is carried over these lines.Data Input Strobe. A low on this pin requests a read of theinternal UART registers. Data is output on the DO-D7 linesif DISTR and CS2 are active.Data Output Strobe. A low on this pin requests a write of theinternal UART registers. Data on the DO-D7 lines arelatched on the rising edge of DOSTR. Data is only writtenif both DOSTR and CS2 are active.Chip Select. A low on this pin allows a read or write to theUART registers to occur. In single port mode, CS2 is latchedon ADS.(3 state) UART Interrupt. This signal indicates that aninterrupt condition on the UART side has occurred. If theEnable 8250A interrupt bit in the interrupt Enable Registeris 0 the interrupt is gated by the DISTR signal to providecompatibility with the 8250B. The output can be put in a highimpedance state with the OUT2 register bit in the ModemControl Register. In single-port mode, INTRPT also becomesvalid when a modem interrupt signal is generated bythe modem section's Detect Register.Function is determined by STNDLN pin and bit 7, ToneControl Register:STNDLND70 0 RXD outputs data received by modem.1 0 RXD is electrically an input but signal isignored.X 1 RXD is a serial input to UART.I3-81

-~SSI73K222USingle-Chip Modemwith UARTPIN DESCRIPTION (continued)UART INTERFACE (continued)TXD 7 9ANALOG I LINE INTERFACENAME DIP PLCCTXA1 3 4TXA2 4 5RXA 16 18SPKR 17 19OH 18 200TYPE00I00Function is determined by STNDLN pin and bit 7, ToneControl Register:-~.--- ---"'._-STNDLN D70 0 TXD is a serial output of UART.1 0 TXD is forced to a mark.X 1 TXD is a serial output of UART.DESCRIPTION(differential) Transmitted Analog. These pins provide theanalog output signals to be transmitted to the phone line.The drivers will differentially drive the impedance of the linetransformer and the line matching resistor. An externalhybrid can also be built using TXA 1 as a single endedtransmit signal.Received Analog. This pin inputs analog information that isbeing received by the two-to-four wire hybrid. This inputcan also be taken directly from an external hybrid.Speaker Output. This pin outputs the received signal througha programmable attenuator stage, which can be used forvolume control and disabling the speaker.--Off-hook relay driver. This signal is an open drain outputcapable of sinking 20mA and is used for controlling a relay.The output is the complement of the OH register bit in CR3.3-82

SSI73K222USingle-Chip Modemwith UARTPIN DESCRIPTION (continued)UART CONTROL INTERFACE (STNDLN = 1)(See Figure 1: Single-port mode)NAME DIP PLCC TYPEADS 23 25 IUA3 12 14 ICTS 14 16 IDSR 13 15 IDCD 11 13 IDTR 22 24 0RTS 2 3 0RI 8 10 IDESCRIPTIONAddress Strobe. ADS is used to latch address and chipselect to simplify interfacing to a multiplexed Address/DataBus. UAO-UA3 and CS2 are latched when the ADS signalgoes high.UART Address Bit 3. UA3 is used in single-port mode toaddress the modem registers from the 16C450 interface.If UA3 is 0, the normal 16C450 registers are addressed byUAO-UA2 and if UA3 is 1, the modem registers are addressed.UA3 is latched when ADS goes high.Clear to Send. This pin is the complement of CTS bit in theModem Status Register. The signal is used in modemhandshake control to signify that communications havebeen established and that data can be transmitted.Data Set Ready.This pin is the complement of DSR bit inthe Modem Status Register.The signal is used in modemhandshake to signify that the modem is ready to establishcommunications.Data Carrier Detect. This pin is the complement of DCD bitin the Modem Status Register. The signal is used in modemcontrol handshake to signify that the modem is receiving acarrier.Data Terminal Ready.The DTR output is programmedthrough a bit in the Modem Control Register. The signal isused in modem handshake to signify that the 16C450 isavailable to communicate.Request to Send. The RTS output is programmed througha bit in the Modem Control Register. The signal is used inmodem handshake to signify that the 16C450 has data totransmit.Ring Indicator. This Indicates that a telephone ringingsignal is being received. This pin is the complement of theRI bit in the Modem Status Register.I3-83

SSI73K222USingle-Chip Modemwith UARTPIN DESCRIPTION (continued)MICROPROCESSOR INTERFACE (STNDLN = 0)(See Figure 2: Dual-port mode)NAME DIP PLCC TYPE DESCRIPTIONMAO-MA2 12-14 14-16 I Modem Address Control. These lines carry registeraddresses for the modem registers and should be validthroughout any read or write operation.DATA 22 24 I/O Serial Control Data. Serial control data to be read/written isclocked in/out on the falling edge of the DCLK pin. Thedirection of data transfer is controlled by the state of the RDpin. If the RD pin is active (low) the DATA line is an output.Conversely, if the RD pin is inactive (high) the DATA line isan input.RD 23 25 I Read. A low on this input informs the SSI 73K222U thatcontrol data or status information is being read by theprocessor from a modem register.WR 26 28 I Write. A low on this input informs the SSI 73K222U thatcontrol dataor status information is available for writing intoa modem register. The procedure for writing is to shift indata LSB first on the DATA pin for eight consecutive cyclesof DCLK and then to pulse WR low. Data is written on therising edge of WR.DCLK 11 13 I Data Clock. The falling edge of this clock is used to strobecontrol data for the modem registers in or out on the DATApin. The normal procedure for a write is to shift in data LSBfirst on the DATA pin for eight consecutive cycles of DCLKand then to pulse WR low. Data is written on the rising edgeof WR. The falling edge of the RD signal must continue foreight cycles of DCLK in order to read all eight bits of thereference register. Read data is provided LSB first. Datawill not be output unless the RD signal is active.INT 2 3 0 (with weak pull-up) Modem Interrupt. This output signal isused to inform the modem processor that a change in amodem detect flag has occurred. The processor must thenread the Modem Detect Register to determine which detecttriggered the interrupt. INTwili stay active until the processorreads the Modem Detect Register or does a full reset.mPRST* 8 10 0 Microprocessor Reset. This output signal is used to providea hardware reset to the microprocessor. This signal ishigh if the RESET pin is high or the MCR bit D3 (OUT1) bitis set.* NOTE: The mPRST pin is an upgraded function which was not included in the initial definition of theSSI 73K222U.3-84

CfSIlSII;rn;iXDII'fSNCOHRELAYDRIVERVOO VREF GN> ISET999 9I I?1.8432 MHZRiO----+--lCS2jjSTiiill5SfR(.oJCoU1ADiIIn the single-port mode, the SSI 73K222U is designed to beaccessed only by the main CPU,using the same parallel bus utilizedfor data transfer. This mode is enabled when the STNDLN pin is ata logic "1". Inthe single port mode, internal registers are accessedby the main CPU to configure both the UART section and theFIGURE 1:Single-Port Modemodem function, eliminating the need for a separate microcontroller.In this mode, multiplexed pins provide the eTS, DSR, DTR,OED and RI signals normally associated with the UART function. Aseparate pin, ADS, is used for bus control.en:::J(Qlen(1)°en~~­::; "'C .......'::rs:Wc:O"»Q.N:D(1)~-43c:

CS2iiiSi'R0i5STI'i.... Ail WROIGITAllOOPBACKlNi',-------'IC5R"'LAYDRIVER\{)IJ VF£F GNO ISET999 9I POWER I?1.1432 MHZSPKR-:::s_=e~~:::J"'CC ~C:(i)w»1".... 01\)oN:::J"'1\)-I _. I\)"ac:3:oa.(I)3CA)~FIGURE 2:Dual-Port ModeThe dual-port mode allows use of a dedicated microprocessor forcontrol of the modem function, and is enabled when the STNDLNpin = "0". This mode is useful for conventional plug-in card modemdesigns where it is necessary to make the modem function transparentto the main CPU. In this mode, the SSI 73K222U's multiplexedpins form the serial command bus usedto communicate withthe external microprocessor. The RI, CTS, DSR, DTR, and DCDlogic functions must then be implemented using ports from thededicated microprocessor.The serial control interface allows access to the control and statusregisters via a serial command port. In this mode the MAO, MA1,and MA2 lines provide register addresses for data passed throughthe DATA pin under control of the RD and WR lines. A read operationis initiated when the RD line is taken low. The next eightcycles of DCLK will then transfer out eight bits of the selectedaddress location LSB first. A write takes place by shifting in eightbits of data LSB first for eight consecutive cycles of DCLK. WR isthen pulsed low and data transfer into the selected register occurson the rising edge of WR.

SSI73K222USingle-Chip Modemwith UARTUART CONTROL REGISTER OVERVIEWDATA BIT NUMBERUARTREGISTER ADDRESS 07 06 05 04 03 02 01 DOUA3-UAO*RECEIVERBUFFER0000RBRBIT7BIT6 BIT 5 BIT4 BIT3 BIT2 BIT 1BITOREGISTER DLABzO (MSB) (LSB)I (READ ONL YJTRANSMITHOLDING0000THRBIT7BIT6 BIT5 BIT4 BIT 3 BIT2 BIT 1BITOREGISTER DLAB=O (MSB) (LSB)('

SSI73K222USingle-Chip Modemwith UARTMODEM CONTROL REGISTER OVERVIEWADDRESSDATA BIT NUMBERSTNDLNREGISTER0 1D7 D6 D5 D4 03 02MA2· UA3·_MAO llAOCONTROLCHARACTER CHARACTERMODULATION MODULATION POWERREGISTER CAO 000 10000OPTIONSIZE 1 SIZEOMODEON0 (READ ONLY) (READ ONLY)01 DOTRANSMIT ORIGINATE!ENABLE ANSWERCONTROL TRANSMIT TRANSMIT ENABLEREGISTER CRl 001 1001 PATTERN PATTERN DETECT1 1 0 INTERRUPTBYPASSSCRAMBLERCLKCONTROLRESETTESTTESTMODE MODE1 0DETECTREGISTERDEVICE DEVICERECEIVEUNSCR.ANSWERDR 010 1010CARRIERSIGNATURE SIGNATURE MARK TONEDATADETECT1 0DETECTDETECTCALLPROGRESSDETECTLONGLOOPDETECTTONETRANSMIT TRANSMITRXDITXDCONTROL TONE 011 1011GUARD ANSWERCONTROLREGISTER TONE TONETRANSMIT DTMF DTMFDTMF 3 2DTMF1DTMFOGUARD!ANS~TONECONTROLREGISTER CR2 100 1100 RESERVED FOR FUTURE USE2CONTROL SPEAKER SPEAKERREGISTER CR3 101 1101 VOLUME VOLUME OFF·HOOK X X X3 1 0XXSCRATCHREGISTERSCR 110 1110 BIT7 BIT6 BITS BIT4 BIT3 BIT2BIT 1BITOUARTCONTROL UCR 111 1111REGISTERREQUEST DATADATARINGTXCLKX TO SEND TERM. READYCARRIERINDICATOR(READ ONLY) (RTS) (DTR) DETECT (DCD)(RI)(READ ONLY) (READ ONLY)DATASETREADY(DSR)CLEARTOSEND(CTS)3-88

SSI73K222USingle-Chip Modemwith UARTUART REGISTER BIT DESCRIPTIONSUART SECTIONRECEIVER BUFFER REGISTER (RBR) (READ ONLY)STNDLN: 0ADDRESS: UA2 - UAO = 000, DLAB = 01UA3 - UAO = 0000, DLAB = 0This read only register contains the parallel received data with start, stop, and parity bits (if any) removed. Thehigh order bits for less than 8 data bits/character will be set to O.TRANSMIT HOLDING REGISTER (THR) (WRITE ONLY)STNDLN: 0 1ADDRESS: UA2 - UAO = 000, DLAB = 0 UA3 - UAO = 0000, DLAB = 0This write only register contains the parallel data to be transmitted. The data is sent LSB first with start, stop,and parity bits (if any) added to the serial bit stream as the data is transferred.INTERRUPT ENABLE REGISTER (IER)STNDLN: 0 1ADDRESS: UA2 - UAO = 001, DLAB = 0 UA3 - UAO = 0001, DLAB = 0IThis 8-bit register enables the four types of interrupts of the UART to separately activate the chip Interrupt(INTRPT) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of theInterrupt Enable Register. Similarly, by setting the appropriate bits of this register to a logic 1, selectedinterrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and theactive (high) INTRPT output fromthe chip. All other system functions operate in their normal manner, includingthe setting of the Line Status and Modem Status Registers.BIT NO. NAME CONDITION DESCRIPTIONDO Received Data 1 This bit enables the Received Data Available Interruptwhen set to logic 1 .D1 Transmitter Holding 1 This bit enables the Transmitter Holding RegisterRegister Empty Empty Interrupt, when set to logic 1..-D2 Receiver Line 1 This bit enables the Receiver Line Status Interrupt,Status Interrupt when set to logic 1 .D3 Modem Status 1 This bit enables the Modem Status Register Interruptwhen set to interrupt_logic 1.D4 8250N16450 1/0 Set for compatibility with 8250N16C450 UARTS.Reset this bit to disable the gating of the INTRPTinterrupt line with the OISTR signal which isneeded for 8250B compatibility.05 - D7 Not Used 0 These three bits are always logic O.3-89

SSI73K222USingle-Chip Modemwith UARTINTERRUPT 10 REGISTER (UR) (READ ONLY)STNDLN: 0 1ADDRESS: UA2· UAO = 010 UA3· UAO = 0010UART SECTIONThe IIR register gives prioritized information as to the status of interrupt conditions. When accessed, the IIRfreezes the highest priority interrupt pending and no other interrupts are acknowledged until the particularinterrupt is serviced by the CPU.BIT NO. NAME CONDITION DESCRIPTIONDO Interrupt Pending 0 This bit can be used in either a hardwired priortizedor polled environment to indicate whether an interruptis pending. When bit 0 is a logic 0, an interruptis pending and the IIR contents may be used as apointer to the appropriate interrupt service routine.1 When bit 0 is a logic 1 , no interrupt is pending.01,02 Interrupt 10 bits 0, 1 Table below These two bits of the II R are used to identify thehighest priority interrupt pending as indicated inthe following table.03 - 07 Not Used 0 These five bits of the II R are always logic O.INTERRUPT PRIORITY TABLE02 01 DO PRIORITY TYPE SOURCE RESET0 0 1 - None None -.-1 1 0 Highest Receiver Line Status Overrun Error, Reading the LineParity Error, Status RegisterFraming Error orBreak Interrupt1 0 0 Second Receive Data Receive Data Reading the Rcvr.Available Available Buffer Register0 1 0 Third Transmit Holding Transmit Holding Reading IIR Registe~Register Empty Register Empty (if source of interrupt)or Writing to TransmitHolding Register0 0 0 Fourth Modem Status Clear to Send or Reading the ModemData Set Ready or Status RegisterRing Indicator orData Carrier Det.3-90

--~--.SSI73K222USingle-Chip Modemwith UARTLINE CONTROL REGISTER (LCR)STNDLN: 0ADDRESS: UA2 - UAO = 0111UA3 - UAO = 0011UART SECTIONThe user specifies the format of the asynchronous data communications exchange via the Line ControlRegister. In addition to controlling the format, the user may retrieve the contents of the Line Control Registerfor inspection. This feature simplifies system programming and eliminates the need for separate storage insystem memory of the line characteristics.BIT NO. NAME CONDITION DESCRIPTION00 Word Length Select ° Bits DO and 01 select the number of data bits percharacter as shown:01 Word Length Select 1 01 00 Word Length0 0 5 bits0 1 6 bits-.-1 0 7 bits1 1 a bits02 Number of Stop Bits o or 1 This bit specifies the number of stop bits in eachtransmitted character. If bit 2 is a logic 0, one stopbit is generated in the transmitted data. If bit 2 is alogic 1 when a 5-bitword length is selected via bitso and 1 , one-and-a-half stop bits are generated. Ifbit 2 is a logic 1 when either a 6, 7, or a-bit wordlength is selected, two stop bits are generated.The receiver checks the first stop bit only, regardlessof the number of stop bits selected.03 Parity Enable 1 This bit is the Parity Enable bit. When bit 3 is a logic1, a parity bit is generated (transmit data) orchecked (receive data) between the last data wordbit and stop bit of the serial data. (The parity bit isused to produce an even or odd number of 1'swhen the data word bits and the parity bit aresummed).04 Even Parity Select 1 or 0 This bit is the Even Parity Select bit. When bit 3 isa logic 1 and bit 4 is a logic 0, an odd number oflogic 1's are transmitted or checked in the dataword bits and parity bit. When bit 3 is a logic 1 andbit 4 is a logic 1, an even number of logic 1's aretransmitted or checked.I3-91

-~---~---SSI.73K222USingle-Chip Modemwith UARTLINE CONTROL REGISTER (LCR) (Continued)UART SECTIONBIT NO. NAME CONDITIONDESCRIPTION05 Stick Parity 1 or 005 040 00 11 01 106 Set Break 107 Divisor Latch Access 1Bit (DLAB)This bit is the Stick Parity bit. When bit 3 is a logic1 and bit 5 is a logic 1 , the parity bit is transmittedand checked by the receiver as a logic 0 if bit 4 isa logic 1 or as a logic 1 if bit 4 is a logic o.ParityODD ParityEVEN ParityMARK ParitySPACE ParityOutput of modem is set to a spacing state. Whenthe modem is transmitting DPSK data if the SetBreak bit is held for one full character (start, data,parity, stop) the ~reak will be extended to 2 N + 3space bits (where N = # data bits + parity bit + 1start + 1 stop). Any data bits generated during thistime will be ignored. See note below.This bit is the Divisor Latch Access Bit (DLAB). Itmust be set high (logic 1) to access the DivisorLatches of the baud generator during a Read orWrite operation. It must be set low (logic 0) toaccess the Receiver Buffer, the Transmitter HoldingRegister, or the Interrupt Enable Register.NOTE: This feature enables the CPU to alert a terminal in a computer communications system. If thefollowing sequence is followed, no erroneous or extraneous characters will be transmitted becauseof the break.1. Load an all O's pad character in response to THRE.2. Set break in response to the next THRE.3. Wait for the Transmitter to be idle. (TSRE = 1), and clear break when normal transmission hasto be restored.During the break, the Transmitter can be used as a character timer to accurately establish thebreak duration.3-92

SSI73K222USingle-Chip Modemwith UARTMODEM CONTROL REGISTER (MCR)STNDLN: 0 1ADDRESS: UA2-UAO=100 UA3 - UAO = 0100UART SECTIONThe MCR register controls the interface with the modem. Bits 01 and DO are also available as read only bitsin the UART Control Register in the Modem Registers. In single-port mode, bits 01 and DO are availableinverted at the RTS and OTR pins.BIT NO. NAME CONDITION DESCRIPTIONDO OTR 1 This bit controls the Data Terminal Ready (OTR)output. When bit 0 is set to a logic 1, the OTRoutput is forced to a logic O. When bit 0 is reset toa logic 0, the OTR output is forced to a logic 1.01 RTS 1 This bit controls the Request to Send (RTS) output.When bit 1 is set to a logic 1 , the RTS output is forcedto a 10gicO. When bit 1 is resetto a 10gicO, the RTSoutput is forced to a logic 1.02 mPRST* 1 In single-port mode inactive unless loop = 1,(OUT1 in 16C450)then functions as below (04). In dual-port modethe mPRST pin is the logical OR of this bit and theRESET pin.03 Enable Interrupt 0 Sets INTRPT pin to high impedance if(OUT2 in 16C450) STNOLN = 1...-1 INTRPT output enabled.04 LOOP 1 This bit provides a local loop back feature for diagnostictesting of the UART portion of theSSI 73K222U. When bit 04 is set to logic 1, thefollowing occurs:1. TXO is forced to mark, RXO is ignored.2. The output of the Transmitter is looped to theReceiver.3. The four modem control inputs to the UART(CTS, OSR, OCO, and AI) are ignored and theUART signals RTS, OTR, Enable Interrupt, andmPRST are forced inactive.4. The UART signals RTS, OTR, Enable Interrupt,and mPRST are internally connected tothe four control signals CTS, OSR, OCO andRI respectively. Note that the Modem StatusRegister Interrupts are now controlled by thelower fou r bits of the Modem Control Register.The interrupts are still controlled by the InterruptEnable Register.05 - 07 0 These bits are permanently set to logic O.• Note: The mPRST bit has an upgraded function which was not included in the initial definition of the SSI 73K222U.I3-93

SSI73K222USingle-Chip Modemwith UARTLINE STATUS REGISTER (LSR)STNDLN: 0ADDRESS: UA2·UAO=1011UA3· UAO = 0101UART SECTIONThis register provides status information to the CPU concerning the data transfer.BIT NO. NAME CONDITION DESCRIPTIONDO DR 1 The Data Ready (DR) bit is set to a 1 whenever acomplete incoming character has been receivedand transferred into the Receiver Buffer Register.Data Ready is reset to 0 by reading the data in theReceiver Buffer Register or by writing a 0 into itfrom the processor.01 OE 1 The Overrun Error (OE) bit indicates that the datain the Receiver Buffer Registerwas not read by theCPU before the next character was transferred intothe Receiver Buffer Register, thereby destroyingthe previous character. The OE indicator is resetwhenever the CPU reads the contents of the LineStatus Register.02 PE 1 The Parity Error (PE) bit indicates that the receivedcharacter did not have the correct parity. The bit isreset to Owheneverthe CPU reads the Line StatusRegister.03 FE 1 The Framing Error (FE) bit indicates that the receivedcharacter did not have a valid stop bit. TheFE indicator is reset whenever the CPU reads thecontents of the Line Status Register. A framingerror will not occur in OPSK receive from themodem due to the fact that missing stop bits arereinserted.04 BI 1 The Break Interrupt (BI) bit indicates that a breakhas been received. A break occurs whenever thereceived data is held to 0 for a full data word (start+ data + stop) or for two full data words whenreceiving in OPSK mode from the modem. The BIbit is reset to 0 whenever the CPU reads the LineStatus Register.05 THRE 1 The Transmit Holding Register Empty (THRE)indicates that the Transmitter is ready to accept anew character for transmission. The THRE bit isreset when the CPU loads a character into theTransmit Holding Register.06 TSRE 1 The Transmit Shift Empty (TSRE) indicates thatboth the Transmit Holding Register and the TransmitShift Registers are empty ....._-_._-------07 - 0 Always zero.3-94

SSI73K222USingle-Chip Modemwith UARTMODEM STATUS REGISTER (MSR) (READ ONLY)STNDLN: 0 1ADDRESS: UA2 • UAO = 110 UA3 • UAO = 0110UART SECTIONThis register provides the current state of the control signals from the modem. In addition, four bits providechange information. The CTS, DSR, DCD, and RI signals come from the UART Control Register ifSTNDLN = ° and from the CTS, DSR, DCD and RI pins (inverted) if STNDLN = 1. This register is READ ONLY.The delta bits indicate whether the inputs have changed since the last time the Modem Status Register hasbeen read. In Loop Mode CTS, DSR, RI and DCD are taken from RTS, DTR, mPRST, and Enable Interruptin the Modem Control Register respectively.BIT NO. NAME CONDITION DESCRIPTIONDO DCTS 1 This bit is the Delta Clear to Send (DCTS) indicator.Bit ° indicates that the CTS input to the chiphas changed state since the last time itwas read bythe CPU.01 DDSR 1 This bit is the Delta Data Set Ready (DDSR)indicator. Bit 1 indicates that the DSR input to thechip has changed state since the last time it wasread by the CPU.02 TERI 1 This bit is the Trailing Edge of the Ring Indicator(TERI) detector. Bit 2 indicates that the RI input tothe chip has changed state.03 DDCD 1 This bit is the Delta Data Carrier Detect (DDCD)indicator. Bit 3 indicates that the DCD input to thechip has changed state.04 CTS 1 This bit is the complement of the Clear To Send(CTS) input. If STNDLN = 0, this reflects the statusof the UART Control Register bit. If bit 4 (loop) ofthe MCR is set to a 1 , this bit is equivalent to RTSin the MCR.---05 DSR 1 This bit is the complement of the Data Set Ready(DSR) input. If STNDLN = 0, this reflects the statusof the UARTControl Registerbit. If bit40fthe MCRis set to a 1, this bit is the equivalent of DTR in theMCR.06 RI 1 This bit is the complement of the Ring Indicator (RI)input. If STNDLN = 0, this reflects the status of theUART Control Register bit. If bit 4 of the MCR is setto a 1, this bit is equivalent to mPRST in the MCR.07 DCD 1 This bit is the complement of the Data CarrierDetect (DCD) If STNDLN '" 0, this reflects thestatus of the UART Control Register bit. If bit 4 ofthe MCR is setto a 1 , this bit is equivalentto EnableInterrupt in the MCR.I3-95

~--- -------~~--SSI73K222USingle-Chip Modemwith UARTSCRATCH REGISTER (SCR)STNDLN: 0ADDRESS: UA2 • UAO = 111 UA3 • UAO = 01111UART SECTIONThe Scratch Register is a dual port register which can be simultaneously accessed through both the UARTbus and the modem bus.This provides the possibility for the modem controller to communicate directly withthe central CPU. Note that if both processors write the Scratch Register, the data stored will be from whicheverprocessor last wrote the register.DIVISOR LATCH (Least significant byte) (DLL)STNDLN: 0 1ADDRESS: UA2 • UAO = 000, DLAB = 1 UA3 • UAO = 0000, DLAB = 1DIVISOR LATCH (Most significant byte) (DLM)STNDLN: 0 1ADDRESS: UA2· UAO = 001, DLAB = 1 UA3 • UAO = 0001, DLAB = 1DIVISOR LATCH VALUE VS. DATA RATEThe Divisor Latch is two 8-bit write only registers which control the rate of the programmable baud generator.The programmable baud generator generates an output clock by dividing an internal 1.8432 MHz clock by thevalue stored in the divisor latch. This output clock has a value of 16X the data rate at which the modem willoperate. This output clock is available at pin 21 under the control of bit 3 (D3) of the Modem Control Register 1.Upon loading either of the Divisor Latches the 16-bit device counter is immediately loaded, preventing longcounts on initial load. The following table shows divisor values for common data rates.DESIRED DIVISOR USED % ERROR DESIRED DIVISOR USED % ERRORDATA RATE FOR 16x DATA GENERATED DATA RATE FOR 16 x DATA GENERATEDRATE CLOCKRATE CLOCK50 1 2304 4800 2475 1 1536 7200 16110 1 1047 9600 12134.5 1 857 0.058 19200 6159 1 768 38400 3----- -----.. --------~300 1 384 56000 2 2.86600 2 192 1. Data Rate valid for FSK transmission.1200 3 96 2. Data Rate valid for halfspeed DPSK trans mis-1800 64sion.2000 58 0.69 3. Data Rate valid for normal 1200 BIT/S DPSKtransmission.2400 483600 323-96

SSI73K222USingle-Chip Modemwith UARTMODEM REGISTER BIT DESCRIPTIONSMODEM SECTIONCONTROL REGISTER (CRO)STNDLN: 0 1ADDRESS: MA2· MAO = 000 UA3· UAO = 1000BIT NO. NAME CONDITION DESCRIPTIONDO Answer/Originate 0 Selects Answer Mode (transmit in high band, receivein low band).1 Selects Originate Mode (transmit in low band,receive in high band).01 Transmit Enable 0 Disables transmit output at TXA.1 Enables transmit output at TXA.--NOTE: Answer tone and DTMF TX control requireTransmit Enable. If Transmit Enable is on, callprogress and answer tone detector interrupts aremasked.02, 03 Character Size 0, 1 These bits are read only. These bits represent thecharacter size. The character size is determinedby the UART Line Control Register and includesdata, parity (if used), one start bit, and one stop bit.03 02 Character length0 0 8-bit character0 1 9-bit character1 0 1 O-bit characte r1 1 11-bit character04 Power ON This bit controls the power down mode of theSSI 73K222U, the analog, and most digital portionsof the chip. The digital interface is activeduring power down.---------------0 Power down mode.1 Normal operation.05 Modulation Mode 0 DPSK-------------- __ ----01 FSK---- - -06 Reserved 0 Must be written as zero.07 Modulation Option 0 DPSK: 1200 biUs1 600 biUs0 FSK: 103 mode1 V.21 modeI3-97

SSI73K222USingle-Chip Modemwith UARTCONTROL REGISTER (CR1)STNDLN: 0ADDRESS: MA2 • MAO = 0011UA3· UAO = 1001MODEM SECTIONBIT NO.NAMECONDITIONDESCRIPTIONDO, 01D2D3D4Test ModeResetClK Control(Clock Control)Bypass ScramblerD1 DO0 0 Selects normal operating mode.0 1 Analog loopback Mode. loops the transmittedanalog signal back to the receiver, and causes thereceiver to use the same center frequency as theTransmitter. To squelch the TXA pin, transmitenable bit must be forced low.1 0 Selects remote digitalloopback. Received data islooped back to transmit data internally, and RXD isforced to a mark. Data in TXD is ignored.1 1 Selects half-duplex. Internally performs a logicalAND of TXD and RXD to send to the UARTreceiver. Both transmit and receive characters willoccur at the Receiver Buffer Register.0 Selects normal operation.--1 Resets modem to power down state. All ControlRegister bits (CRO, CR1, TONE) are reset to zero.The output of the clock pin will be set to the crystalfrequency.0 ClK pin output is selected to be an 11.0592 MHzcrystal echo output.1 ClK pin output is selected to be 16 x the Data Rateset by the UART divisor latch.0 Selects normal operation. DPSK data is passedthrough scrambler.1 Selects Scrambler Bypass. DPSK data is routedaround scrambler in the transmit path.3-98

SSI73K222USingle-Chip Modemwith UARTCONTROL REGISTER (CR1) (Continued)BIT NO. NAME CONDITIONDESCRIPTIONMODEM SECTION05 Enable Detect 0Interrupt06,07 Transmit Pattern 07 0610 00 11 01 1Disables interrupts generated by Detect Registerbits D1 - D4 at INT pin in dual-port mode, or atINTRPT pin in single-port mode. All interruptsnormally disabled in power down modes.Enables interrupts generated by Detect Registerbits D1 - D4 at INT pin in dual-port mode, or atINTRPT pin in single-port mode. An interrupt willbe generated with a change in status of DR bitsD1 - D4. The answer tone and call progress detectinterrupts are masked when the TX enable bit isset. Carrier detect is masked when TX DTMF isactivated. All interrupts will be disabled if thedevice is in power down mode. The interrupt isreset when the DR register is read.Selects normal data transmission as controlled bythe state of the TXD pin.Selects an alternating mark/space transmit patternfor modem testing.Selects a constant mark transmit pattern.Selects a constant space transmit pattern.I3-99

-~SSI73K222USingle-Chip Modemwith UARTDETECT REGISTER (DR)STNDLN:oADDRESS: MA2 - MAO = 0101UA3 - UAO = 1010MODEM SECTIONBIT NO.NAMECONDITIONDESCRIPTIONDOD1D2D3D4D506,07Long LoopCall Progress DetectAnswer Tone ReceivedCarrier OetectUnscrambled MarksReceive DataDevice Signature 0,10 Indicates normal received signal.1 Indicates low received signal level « -38 dBm).0 No call progress tone detected.1 Indicates presence of call progress tones. The callprogress detection circuitry is activated by energyin the normal 350 to 620 Hz call progress bandwidth.--0 No answer tone detected.1 Indicates detection of 2225 Hz answer tone in Bellmode or21 00 Hz in CCITT mode. The device mustbe in Originate Mode for detection of answer tonefor normal operation. For CCITT answer tonedetection, bit DO of the Tone Register must be set.0 No carrier detected in the receive channel.1 Carrier has been detected in the receive channel.0 No unscrambled mark detected.1 Indicates detection of unscrambled marks in thereceived data. A valid indication requires thatunscrambled marks be received for > 165.5 ±13.5 ms.Continuously outputs the received data stream.This data is the same as that output on the RXDpin, but it is not disabled when RXD is tri-stated.----07 06 Product Identified0 0 SSI 73K212U (special order only)0 1 SSI 73K221 U (special order only)1 0 SSI73K222U3-100

SSI73K222USingle-Chip Modemwith UARTTONE CONTROL REGISTER (TONE)STNDLN: 0 1ADDRESS: MA2 - MAO = 011 UA3 - UAO = 1011MODEM SECTIONThe Tone Control Register contains information on the tones that are transmitted. Tones are transmitted onlyif the Transmit Enable bit is set. The priority of the transmit tones are: 1) DTMF, 2) Answer, 3) FSK,4) Guard.BIT NO. NAME CONDITION DESCRIPTIONDO DTMF 0 / Answer/ D6 D5 D4 DO DO interacts with bits 06, 05, and 04 as shown:Guard Tone X X 1 X Transmit DTMF tones.X 1 0 0 Select 2225 Hz answer tone (Bell).X 1 0 1 Select 2100 Hz answer tone (CCITT).1 0 0 0 Select 1800 Hz guard tone.1 0 0 1 Select 550 Hz guard tone.--DO, D1, DTMF Table below Programs 1 of 16 DTM F tone pairs that will beD2,D3transmitted when TX DTMF and TX enable bit(CRO, bit D1) is set. Tone encoding is shownbelow.KEYBOARD OTMF CODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGH1 0 0 0 1 697 12092 0 0 1 0 697 1336----3 0 0 1 1 697 14774 0 1 0 0 770 12095 0 1 0 1 770 13366 0 1 1 0 770 14777 0 1 1 1 852 12098 1 0 0 0 852 13369 1 0 0 1 852 14770 1 0 1 0 941 1336* 1 0 1 1 941 1209# 1 1 0 0 941 1477A 1 1 0 1 697 1633B 1 1 1 0 770 1633C 1 1 1 1 852 1633D 0 0 0 0 941 1633I3-101

---~----SSI73K222USingle-Chip Modemwith UARTTONE CONTROL REGISTER (TONE) (Continued)D4 TX DTMF 0(Transmit DTM F) 1D5 TXANS D5 DO(Transmit Answer Tone) 0 X1 01 1D6 TX Guard 0(Transmit Guard Tone) 1D7 RXD/TXD Control STNDLN D70 01 0X 1MODEM SECTIONDisable DTMF.Activates DTMF. The selected DTMF tones aretransmitted continuously when this bit is high. TXDTMF overrides all other transmit functions.D5 interacts with bit DO as shown.Disables answer tone generator.Enables answer tone generator. A 2225 Hz answertone will be transmitted continuously whenthe transmit enable bit is set. The device must bein answer mode.Enables a 2100Hz answer tone generator, withoperation same as above.Disables guard tone generator.Enables guard tone generator. (See DO for selectionof guard tones).Function is dependant on status of STNDLN pin.RXD is output data received by modem, TXD isserial output of UART.RXD is electrically an input, but the signal isignored, TXD is forced to a mark.RXD is serial input to UART, TXD is serial outputof UART.CONTROL REGISTER (CR3)STNDLN: 01ADDRESS: MA2· MAO = 101 UA3· UAO = 1101BIT NO. NAME CONDITION DESCRIPTIONDO - 04 Not Used Not presently used.D5 Off Hook 0 Relay driver open.1 Open drain driver pulling low.D6,D7 Speaker Volume 0, 1 D7 D6 Speaker volume control status.---0 0 Speaker off0 1 -24 dB1 0 -12 dB1 1 OdB--------------3-102

SSI73K222USingle-Chip Modemwith UARTSCRATCH REGISTER (SCR)STNDLN: 0 1ADDRESS: MA2· MAO = 110 UA3· UAO = 1110MODEM SECTIONThe Scratch Register is a dual-port register which can be accessed either through the UART bus orthe modembus. It can be used for a communication path outside the data stream.UART CONTROL REGISTER (UCR)STNDLN: 0 1ADDRESS: MA2· MAO = 111 UA3· UAO = 1111The UART Control Register contains the handshaking signals necessary for the microprocessor to communicatewith the central CPU through the UART.BIT NO. NAME CONDITION DESCRIPTION00 CTS 1 In dual-port mode, CTS, OSR, OCO and RI arewriteable locations which can be read through the16C450 port in the Modem Status Register.01 OSR 102 OCO 1 In the single-port mode, 00 - 03 are ignored andthe information for the Modem Status Registercomes directly from the external pins.03 RI 104 OTR 105 RTS 1 OTR and RTS are read only versions of thesame register bits in the Modem Contol Register.---06 Not Used07 TXCLK Clock TXCLK is the clock that the UART puts out withTXO. The falling edge of TXCLK is coincident withthe transitions of data on TXO. TXCLK can also beused for the microprocessor to send synchronousdata independent of the UART by forcing datapatterns using CR1 bits 6 and 7 before the risingedge of TXCLK.NOTE: Control Register 2 (CR2) is reserved for future products and is disabled.I3-103

SSI73K222USingle-Chip Modemwith UARTELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSTA = -40°C to 85°C, VDD = 5V ± 10%, unless otherwise noted.PARAMETERRATINGUNITVDD Supply Voltage 7Storage Temperature -65 to 150Soldering Temperature (10 sec.) 260Applied Voltage -0.3 to VDD +0.3VNOTE: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETERS CONDITIONS MIN NOM MAX UNIT-~VDD, Supply Voltage 4.5 5 5.5 VTA, Operating Free-AirTemperature -40 85 °C--External Component (Refer to application drawing for placement.)VREF Bypass Capacitor 2 (VREF to GND) 0.1 /J-F--Bias Setting Resistor 1 (Placed between VDDand ISET pins) 1.8 2 2.2 MO----_.ISET Bypass Capacitor 2 ISET pin to GND 0.1 /J-FVDD Bypass Capacitor 2 (VDDto GND) 0.1 /J-FXTL 1 Load Capacitor From pin to GND 40 pFXTL2 Load Capacitor From pin to GND 20 pF- -Input Clock Variation (11.0592 MHz) -0.01 +0.01%--------Hybrid LoadingR1 See Figure 3 600 0R2 600 0C TXA Hybrid Loading 0.033 /J-F- ---------'---~~1. Optional for minimum worst case current consumption.2. Minimum for optimized system layout; may require higher values for noisy environments.V°C°C3-104

-~SSI73K222USingle-Chip Modemwith UARTDC ELECTRICAL CHARACTERISTICSTA = -40°C to +85 °C, VDD = 5V ± 10%, unless otherwise noted.PARAMETERS CONDITIONS MIN100, Supply CurrentIDDA, ActiveISET Resistor = 2MQIDDA, ActiveISET = GND1001, Power-Down ClK = 11.0592MHz1002, Power-Down ClK = 19.200KHzDigital InputsInput High Current IIH VI = VDDInput low Current III VI = 0 -200Input low Voltage VilInput High Voltage VIH Except RESET & XTl1 2.0Input High Voltage VIH RESET & XTl1 3.0Pull Down Current RESET PIN 5I nput CapacitanceDigital OutputsOutput High Voltage VOH lOUT = -1 rnA 2.4VOL UDO-UD7 and INTRPT lOUT = 3.2 mAVOL other outputslOUT = 1.6 rnAClK Output VOL lOUT = 3.2 rnAOH Output VOL lOUT = 20 rnAOH Output VOL lOUT = 10 rnAOffstate Current INTRPT pin VO= OV -20CapacitanceInputsInput CapacitanceClKMaximum capacitive load to pinAnalog PinsRXA Input ResistanceRXA I nput CapacitanceNOM MAX UNIT8 12 rnA8 15 mA3 4 rnA2 3 rnA--~.-._--_._--_._._----._--_ ..-_ .. _- ------~--100 J.lAJ.lA0.8 VVV30 J.lA10 pFVDD V0.4 V0.4 V0.6 V1.0 V0.5 V20 J.lA-----_._-- -----I ~~IpFpF-_..200 kQ25 pFI3-105

-~SSI73K222USingle-Chip Modemwith UARTDYNAMIC CHARACTERISTICS AND TIMINGTA = -40°C to +85°C, VDD = 5V ± 10%, unless otherwise noted.PARAMETERSCONDITIONSMINNOM MAX UNITDPSK ModulatorCarrier SuppressionOutput AmplitudeMeasured at TXAANS TONE 2225 or 2100 HzDPSK TX Scrambled MarksFSK Dotting PatternFSK Tone Error Bell 103 or V.21DTMF GeneratorFreq. AccuracyOutput AmplitudeOutput AmplitudeLong Loop DetectDemodulatorDynamic RangeCall Progress DetectorDetect LevelReject LevelDelay TimeHold TimeHysteresisCarrier DetectThresholdDelay TimeHysteresisHold TimeAnswer Tone DetectorDetect Level ThresholdDelay TimeHold TimeDetect Frequency RangeLow Band, not in V.21 modeHigh Band, not in V.21 modeDPSK or FSKDPSK or FSK2~Tones in 350-600 Hz Band2-Tones in 350-600 Hz Band-70dBmO to -30 dBmO Step-30dBmO to -70 dBmO StepDPSK or FSK ReceiveData-70 dBmO to -30 dBmO Step-30 dBmO to -70 dBmO StepIn FSK mode-70 dBmO to -30 dBmO STEP-30 dBmO to -70 dBmO STEP55-11-11-11-.25-10-8-40-3927272-4915210-49.52010-2.5dB-10.0 -9 dBmO,-10.0 -9 dBmO. ----10.0 -9 dBmO±5 Hz.25 %-9 -8 dBmO-7 -6 dBmO-32 dBmO45 dB- -0 dBmO-46 dBmO---80 ms--80 ms_._---dB-42 dBmO45 ms- ----3.0 dB24 ms--- ---- --42 dBmO45 ms30 ms---+2.5 %1. All units in dBmO are measured at the line input to the transformer. The interface circuit inserts an 8 dBloss in the transmit path (TXA1 - TXA2 to line), and a 3dB loss in the receive path (line to RXA).3-106

-----~-SSI73K222USingle-Chip Modemwith UARTDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMINNOM MAX UNITSpeaker OutputGain ErrorOutput Swing SPKRCarrlerVCO10KII50 pF LOAD 5% THD-12.75----f~~-..--~-dBVPCapture RangeOriginate or Answer-1010 HzCapture Time-10Hz to +10 Hz CarrierFrequency change assumed40 100 msRecovered ClockCapture RangeData Delay Time% of Center FrequencyAnalog data in at RXA pin toreceive data valid at RXD pin.-625+625 ppm30 50 ms•Guard Tone GeneratorTone Accuracy550 or 1800 Hz-20+20 HzTone Level550 HZ-4.0-3.0 -2.0 dB(Below DPSK Output)1800 HZ-7.0-6.0 -5.0 dBHarmonic Distortion700 to 2900 HZ-60 dBSERIAL BUS INTERFACE (See Figure 4)The following times are for CL = 100 pF.PARAMETERMINNOM MAX UNITTRD Data out from ReadTCKD Data out after ClockTRDF Data Float after ReadTRCK Clock High after ReadTWW Write WidthTOCK Data Setup Before ClockTCKH Data Hold after ClockTCKW Write after ClockTACR Address setup before Control 1TCAR Address Hold after Control 1TACW Address setup before WriteTCAW Address Hold after Write1. Control is later of falling edge of RD or DCLK.00200.. _------140 ns200 ns200 nsns140150_....-20------10000 nsnsns150- -------~.50~-- ---- -------- ..nsns50 ns50 ns--50 ns------ ----~------3-107

SSI73K222USingle-Chip Modemwith UARTPARALLEL BUS INTERFACE (See Figure 5) The following times are for CI = 100 pF.PARAMETER MIN MAX MIN MAX UNITDual-Port Mode Single-PortModeRC Read Cycle = TAD + TRC 240 340 - 1-----nsTDIW DISTR Width 80 80nsTODD Delay DISTR to Data (read time) 80 80 nsTHZ** DISTR to Floating Data Delay 0 50 0- -50 nsTRA Address Hold after DISTR 20 20nsTRCS Chip select hold after DISTR 20 20nsTAR* DISTR Delay after Address 20 20nsTCSR DISTR Delay after Chip Select 20 20---nsWC Write Cycle = TAW + TDOW + TWC 140 140nsTDOW DOSTR Width 80 80nsTDS Data Setup 30 50nsTDH** Data Hold 20 20nsTWA Address Hold after DOSTR 20 20 - -nsTWCS Chip select hold after DOSTR 20 20 ---- --_.nsTAW* DOSTR delay after Address 20 20 ns--------TCSW DOSTR delay after Chip Select 20 20 ns------TADS Address Strobe Width 40TAS Address Setup Time 30nsTAH Address Hold Time 0 ns--TCS Chip Select Setup Time 30nsTCH Chip Select Hold Time 0nsTRC Read Cycle Delay 40 40nsTWC Write Cycle Delay 40 40nsTAD Address to Read Data 200 300ns* TAR and TAW are referenced from the falling edge of eitherCS20rDISTRorDOSTR, which everis later.** THZ and TDH are referenced from the rising edge of CS2 or DISTR or DOSTR, which ever is earlier.ns --3-108

SSI73K222USingle-Chip Modemwith UARTTXA1R1RXA .----'1106000R21:1 (Nominal TelephoneLine Impedance)TA Hybrid LoadingAnalog Interface Hybrid LoadingIFIGURE 3: TXA Hybrid Loading Analog Interface Hybrid LoadingREAD MODEDCLKADDRESSDATAWRITE MODEDCLKADDRESSDATAFIGURE 4: Modern Serial Bus Timing3-109

SSI73K222USingle-Chip Modemwith UARTADS(STNDLN=1)ADDRESSUA2 (UA3)-UAODATAUD7-UDOFIGURE 5: UART Bus Timing3-110

SSI73K222USingle-Chip Modemwith UARTTYPICAL PERFORMANCE CHARACTERISTICSThe SSI 73K222U was designed using an integratedanalogldigital architecture that offers optimum performanceover a wide range of line conditions. TheSSI 73K222U utilizes the circuit design proven inSSl's 73K222L one-chip modem, with added enhancementswhich extend low signal level performanceand increase immunity to spurious noise typicallyencountered in integral bus applications. TheSSI 73K222U provides excellent immunity to the typesof disturbances present with usage of the dial-uptelephone network. The following curves show representativeBit Error Rate performance under variousline conditions.BER vs. SINThis test measures the ability of the modem to functionwith minimum errors when operating over noisy lines.Since some noise is generated by even the best dialuplines, the modem must operate with as Iowa SINratio as possible. Optimum performance is shown bycurves that are closest to the zero axis. A narrowspread between curves for the four line conditionsIindicates minimal variation in performance when operatingover a range of line qualities and is typical of highperformance adaptive equalization receivers. Highband receive data is typically better than low band dueto the inherent design of PSK modems.SSI73K222UBER vs SINSSI73K222UBER vs RECEIVE LEVELHIGH BAND RECEIVE~·40 dBm1--+-+-+-+-+-"\'+-"1, DPSK OPERATION~ 1..--1-.I HIGH BAND RECEIVE ~DPSK OPERATIONI C2l1NE10.3\ \ \\ l\ ~\I\\ \'1\ ,\ ' \4 6 10 12 14SIGNAL TO NOISE (dB)L.U~c(a:a:0 10-4a:a:L.UI:::CDSIN = 10.8 dB10.5 \ 1IS/N-15dB10 -10 ·20 ·30 ·40 ·50RECEIVE LEVEL (dBm)3-111

SSI73K222USingle-Chip Modemwith UARTBER vs. Receive LevelThis measures the dynamic range of the modem. Assignal levels vary widely over dial-up lines, the widestdynamic range possible is desirable. The minimumBell specification calls for 36dB of dynamic range.SIN ratios were held constant at the indicated valueswhile receive level was lowered from very high to verylow signal levels. The ''width of the bowl" of thesecurves taken at the 10· BER point is a measure of thedynamic range.BER vs. Carrier OffsetThis parameter indicates how the modem performanceis impacted by frequency shifts encountered in normalPSTN operation. Flat curves show no performancedegradation from frequency offsets. The SSI K-Seriesdevices use a 2nd order carrier tracking phase-Iockedloop,which is insensitive to carrier offsets in excess of10Hz. The Bell network specifications allow as muchas 7Hz offset, and the CCITT specifications require -modems to operate with 7Hz of offset.10- 3L.LI!;ta:!5 10-a:4a:L.LIt::CDSSI73K222UBER vs CARRIER OFFSETI HIGH BAND RECEIVE f--I DPSK OPERATIONJ 3002 11.5 dB SIN I1\-f-""-- -'C ~- -10- 5 I C2 10.8 dB SIN \~ ~-i--- .-J....-12 -4 -8 -12SIGNAL TO NOISE (dB)APPLICATIONThe SSI73K222U includes additional circuitry to greatlysimplify integral modem designs in either of two differentconfigurations. The single-port mode representsthe most efficient implementation for an integral modem.Figure 9 shows a typical schematic using thismode. In this configuration, the SSI 73K222U transfersdata and commands through the single parallelport. All modem control is provided by the main CPU,eliminating the need for an external microcontrollerand supporting components. The SSI 73K222U isunique in that access to both the UART and modemsections is possible through the UART port. Alsoshown is a separate serial port, which can be usedindependent of the modem function when the modemsection is inactive. Figure 10 shows a more conventionalintegral modem deSign, in which a local microprocessorhandles modem supervision, allowing themodem function to be transparent to the main processor.Inclusion of the hybrid drivers, audio volumecontrol, and off hook relay driver reduces componentcount for a highly efficient design. In either mode ofoperation, the SSI 73K222U's ability to operate from asingle +5 volt power supply eliminates the need foradditional supply voltages and keeps power usage toa minimum.(See Figure 9 & 10: Typical Integral ApplicationsSingle and Dual-Port Modes.)3-112

U2 +5AO AJlAl AJOA2 A29AJ A28~B~ ~~VOOIRO I 51 INTRPT GNO I 20+5~18pFC13~= XlC2~24XTL1XTL2ISET I 9C40.1 ~FSTNOALN t-I _15 ___ ~39 UAO TXO 738 UAl37 UA212 UAJ23 _ADSv'RXO 6+5OPTIONALDIGITALSERIAL PORTA4 A27A5 A26A6 A25CS2A7 A24A8 A23A9 A22SSI73K222U~WAENAll--~lOW 913OOSTRRi~1N4004R722KlOR 914DISTR08 A901 A802 A7UOO28 UOlU02R5HIFuseablc03 A6D4 A505 A406 A307 A2RESET30 U03311 U04C9MOVIV250LA20AFIGURE 9: 73K222U Typical Integral Application Single-Port ModeRs1Fus0ablcLINEen::::J(Q(I)len°en: .111SPKR~f-::::;:"'C ==~­.......::Ts:WCO"»0.1\):c(l)~~3c

U2PCBU5IAOOIA04 B24AO A31A2 A29M A27A6 A25J3COM 21NTCOM liNT+S>IVDDA73C'3~~XTLISTNDALN~C2~16pF= XIXTL2MAO I ~4C4U10.1 ~F VDDg _ lPI.O, .. 2 P1.111 TXD-------8053PS:~10 I AXD ALE r;-_ 4 Pl.3__ 5 PI.4 P3.761 Pl.7- .• -------7 PI.66! PI.5eLK 21 19 I XI+5C6, .FN/C+S>IN/CSI:S~~;:::;::::1_::::r CC .......C:iDw»1".... 01\)oN::::r1\)-I _. I\)"'Cc:s:oa.(t)3~./>.AEN 11Kd-LS04I"ITNIC 161 X2551 "I~ ,----73K222U"PAST 1-1 .::...6 ________ -lA7221:;-~~f-! SPKAC12 .OOI~_., f "n. 4 7., '"F.047.>. "R4 . 6". rr '. -1 .... J. 1 ~ ~o [~on _I\jLINEFIGURE 10: 73K222U Typical Integral Application Dual-Port Mode

SSI73K222USingle-Chip Modemwith UARTPACKAGE PIN DESIGNATIONS(Top View)VDDUAOCAUTION:Use handling procedures necessaryfor a static sensitive component.Parentheses indicate single-port mode.TXA1UA1UA2INTRPTISETRESETUD7UD6UDSUD46 5 43 42 41INTRPT 7 0 DOSTRRXD 8 DISTRTXD 9 37 UD7(R) IIl-PRST 10 36 UD6ISET 11 35 UD5(DCD)/DCLK(UA3)/MA2(DSR)/MA1(CTS)/MAOSTNDLNRXASPKRVREFUD3UD2UD1UDOWR/(N/C)XTl1XTl2RD/(ADS)DATAl (DTR)RESETUD4(DeD) I DCLK 13 33 UD3(UA3)/MA2 14 UD2(DSR)/MA1 15 UD1(CTS)/MAOUDOSTNDLN 29 N/C18 19 20 21 22 23 24 25 26 27 28-l:l..: cr:016~..: 10 N-'~ fi: z f- -'(!j u ..: Ie: f- f- I~Ul I~0 x xIii)i?f-I~Q.IGNDClK600-Mil40-Pin DIP44-PinPLCCORDERING INFORMATIONPART DESCRIPTIONORDER NO.PKG.MARKSSI73K222U40-Pin Plastic Dual-In-Line44-Pin Plastic Leaded Chip Carrier73K222U-IP73K222U-IH--73K222U-IP73K222U-IHNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-69141293 - rev. 3-115 ©1989 Silicon Systems, Inc.

Notes:3-116

SSI73K224LV.22bis/V.22/V.21 ,Bell 212A/1 03Single-Chip ModemJanuary 1994DESCRIPTIONThe SSI 73K224L is a highly integrated single-chipmodem IC which provides the functions needed toconstruct a V.22bis compatible modem, capable of2400 biVs full-duplex operation over dial-up lines. TheSSI 73K224L offers excellent performance and a highlevel of functional integration in a single 28-pin DIP.This device supports V.22bis, V.22, V.21, Bell 212Aand Bell 103 modes of operation, allowing both synchronousand asynchronous communication.TheSSI73K224L is designed to appear to the systemsdesigner as a microprocessor peripheral, and will easilyinterface with popular single-chip microprocessors(80C51 typical) for control of modem functions throughits 8-bit multiplexed address/data bus or via an optionalserial control bus. An ALE control line simplifies addressdemultiplexing. Data communications normallyoccur through a separate serial port. The SSI 73K224Lis pin and software compatible with the SSI 73K212Land SSI 73K222L single-chip modem ICs, allowingsystem upgrades with a single component change.The SSI 73K224L operates from a single +5 V supplyfor low power consumption.The SSI73K224L is ideal foruse in either free-standingor integral system modem products where full-duplex(Continued)FEATURESOne-chip mUlti-mode V.22bisN.22N.21 andBell 212A11 03 compatible modem data pumpFSK (300 bit/s), OPSK (600, 1200 bitls), or QAM(2400 bitls) encodingPin and software compatible with other551 K-Series 1-chip modemsInterfaces directly with standard microprocessors(8048, 80C51 typical)Parallel microprocessor bus for control with awide range of package optionsSelectable asynch/synch with internal bufferldebuffer and scrambler/descrambler functionsAll synchronous and asynchronous operatingmodes (internal, external, slave)Adaptive equalization for optimum performanceover all linesProgrammable transmit attenuation (16 dB, 1 dBsteps), selectable receive boost (+18 dB)Call progress, carrier, answer tone, unscrambledmark, 51, and signal quality monitorsOTMF, answer and guard tone generatorsTest modes available: ALB, OL, ROL, Mark, Space,Alternating bit, 51 patternCMOS technology for low power consumption(typically 100 mW @ 5V) with power-down mode(15 mW@5V)TTL and CMOS compatible inputs and outputsIBLOCK DIAGRAM8-BITmpBUSUFI I II I I: L ____________________________ III:AGCGAIN BOOST'I TON-E D~ET-Ec-TION-,I0194 - rev.3-117

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemDESCRIPTION (Continued)2400 bitls data communications over the 2-wireswitched telephone network is desired. Its high functionality,low power consu mption, and efficient packagingsimplify design requirements and increase systemreliability.The SSI73K224L is designed to be a complete V.22biscompatible modem on a chip. The complete modemrequires only the addition of the phone line interface, acontrol microprocessor, and RS-232 level converterfora typical system. Many functions were included tosimplify implementation of typical modem designs. Inaddition to the basic 2400 bitls QAM, 600/1200 bitlsDPSK and 300 bit/s FSK modulatorldemodulator sections,the device also includes SYNCH/ASYNCHconverters, scramblerldescrambler, call progress tonedetect, DTMF tone generator capabilities and handshakepattern detectors. V.22bis, V.22, V.21 and Bell212A1103 modes are supported (synchronous andasynchronous) and test modes are provided for diagnostics.Most functions are selectable as options andlogical defaults are provided.OPERATIONDemodulation is the reverse of the modulation process,with the incoming analog signal eventuallydecoded into di-bits and converted back to a serial bitstream. The demodulator also recovers the clockwhich was encoded into the analog signal duringmodulation.Demodulation occurs using either a1200 Hz carrier (answer mode or ALB originate mode)or a 2400 Hz carrier (originate mode or ALB answermode). Adaptive equalization is also used in DPSKmodes for optimum operation with varying lineconditions.FSK MODULATOR/DEMODULATORThe FSK modulator produces a frequency modulatedanalog output signal using two discrete frequencies torepresent the binary data. The Bell 1 03 standard frequenciesof 1270 and 1070 Hz (originate mark andspace) and 2225 and 2025 Hz (answer mark and space)are used when this mode is selected. V.21 mode uses980 and 1180 Hz (originate, mark and space) or 1650and 1850 Hz (answer, mark and space). Demodulationinvolves detecting the received frequencies and decodingthem into the appropriate binary value. The rateconverter and scramblerldescrambler are automaticallybypassed in the FSK modes.QAM MODULATOR/DEMODULATORThe SSI 73K224L encodes incoming data into quadbitsrepresented by 16 possible signal points withspecific phase and amplitude levels. The basebandsignal is then filtered to reduce intersymbol interferenceon the bandlimited telephone network. Themodulator transmits this encoded data using either a1200 Hz (originate mode) or 2400 Hz (answer mode)carrier. The demodulator, although more complex,essentially reverses this procedure while also recoveringthe data clock from the incoming signal. Adaptiveequalization corrects for varying line conditions byautomatically changing filter parameters to compensatefor line characteristics.DPSK MODULATOR/DEMODULATORThe SSI 73K224L modulates a serial bit stream intodi-bit pairs that are represented by four possible phaseshifts as prescribed by the Bell 212A1V.22 standards.The base-band signal is then filtered to reduce intersymbolinterference on the bandlimited 2-wire PSTNline. Transmission occurs on either a 1200 Hz (originatemode) or 2400 Hz carrier (answer mode).3-118PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and provide compromise delay equalizationand rejection of out-of-band signals. Amplitudeand phase equalization are necessary to compensatefor distortion of the transmission line and to reduceintersymbol interference in the band limited receivesignal. The transmit signal filtering corresponds to a75% square root of raised Cosine frequency responsecharacteristic.ASYNCHRONOUS MODEThe Asynchronous mode is used for communicationwith asynchronous terminals which may communicateat 600,1200, or 2400 biVs + 1 %, -2.5% even though themodem's output is limited to the nominal bit rate ±.01 %in DPSK and QAM modes. When transmitting in thismode the serial data on the TXD input is passedthrough a rate converter which inserts or deletes stopbits in the serial bit stream in order to output a signalthat is the nominal bit rate ±.01%. This signal is thenrouted to a data scrambler and into the analog modulatorwhere quad-biVdi-bit encoding results in the out-

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip Modemput signal. Both the rate converter and scrambler canbe bypassed for handshaking, and synchronous operationas selected. Received data is processed ina similar fashion except that the rate converter nowacts to reinsert any deleted stop bits and output data tothe terminal at no greater than the bit rate plus 1 %. Anincoming break signal (low through two characters) willbe passed through without incorrectly inserting a stopbit.The SYNC/ASYNC converter also has an extendedOverspeed mode which allows selection of an outputoverspeed range of either +1% or +2.3%. In the extendedOverspeed mode, stop bits are output at 7/8 thenormal width.Both the SYNC/ASYNC rate converter and the datadescrambler are automatically bypassed in the FSKmodes.SYNCHRONOUS MODESynchronous operation is possible only in the QAM orDPSK modes. Operation is similar to that of the Asynchronousmode except that data must be synchronizedto a provided clock and no variation in data transfer rateis allowable. Serial input data appearing at TXD mustbe valid on the rising edge of TXCLK.TXCLK is an internally derived 1200 or 2400 Hz signalin Internal mode and is connected internally to theRXCLK pin in Slave mode. Receive data at the RXD pinis clocked out on the falling edge of RXCLK. Theasynchlsynch converter is bypassed when Synchronousmode is selected and data is transmitted at thesame rate as it is input.PARALLEL BUS INTERFACEEight 8-bit registers are provided for control, optionselect, and status monitoring. These registers areaddressed with the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as seven consecutive memorylocations.Six control registers are readlwrite memory. Thedetect and 10 registers are read only and cannot bemodified except by modem response to monitoredparameters.SERIAL CONTROL INTERFACEThe serial Command mode allows access to theSSI 73K324 control and status registers via a serialcontrol port. In this mode the AO, A1, and A2 linesprovide register addresses for data passed through theDATA pin under control of the RD and WR lines. A readoperation is initiated when the RD line istaken low. Thenext eight cycles of EXCLK will then transfer out eightbits of the selected addresss location LSB first. A writetakes place by shifting in eight bits of data LSB first foreight consectuive cycles of EXCLK. WR is then pulsedlow and data transfer into the selected register occurson the rising edge of WR.DTMF GENERATORThe DTMF generator controls the sending of the sixteenstandard DTMF tone pairs. The tone pair sent isdetermined by selecting TRANSMIT DTMF (bit 04)and the 4 DTMF bits (00-03) of the TONE register.Transmission of DTMF tones from TXA is gated by theTRANSMIT ENABLE bit of CRO (bit 01) as with allother analog signals.I3-119

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemPIN DESCRIPTIONPOWERNAMEGNDVDDVREFISETTYPEIIaIDESCRIPTIONSystem Ground.Power supply input, 5V -5% +10%. Bypass with .22 IlF and 22 IlF capacitorsto GND.An internally generated reference voltage. Bypass with .22 IlF capacitor toGND.Chip current reference. Sets bias current for op-amps. The chip current is setby connecting this pin to VDD through a 2 MQ resistor. Iset should be bypassedto GND with a .22 IlF capacitor.PARALLEL MICROPROCESSOR INTERFACEALE I Address latch enable. The falling edge of ALE latches the address on ADO-AD2 and the chip select on CS.ADO- I/O / Address/data bus.These bidirectional tri-state multi-plexed lines carry infor-AD7 Tristate mation to and from the internal registers.CS I Chip select. A low on this pin allows a read cycle or a write cycle to occur. ADO-AD7 will not be driven and no registers will be written if CS (latched) is notactive. CS is latched on the falling edge of ALE.ClK a Output clock. This pin is selectable under processor control to be either thecrystal frequency (for use as a processor clock) or 16 x the data rate for useas a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystalfrequency on reset.INT 0 Interrupt. This open drain weak pullup, output signal is used to inform theprocessor that a detect flag has occurred. The processor must then read thedetect register to determine which detect triggered the interrupt. INT will stayactive until the processor reads the detect register or does a full reset.RD I Read. A low requests a read of the SSI 73K224l internal registers. Datacannot be output unless both RD and the latched CS are active or low.RESET I Reset. An active high signal on this pin will put the chip into an inactive state.All control register bits (CRO, CR1, CR2, CR3, Tone) will be reset. The outputof the ClK pin will be set to the crystal frequency. An internal pu II down resistorpermits power on reset using a capacitor to VDD.WR I Write. A low on this informs the SSI73K224l that data is available on ADO-AD7for writing into an internal register. Data is latched on the rising edge of WR.No data is written unless both WR and the latched CS are active (low).Note: The serial control mode is provided in the parallel versions by tying ALE high and CS low. In thisconfiguration AD7 becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2, respectively.3-120

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemDTE USER INTERFACENAMETYPEEXCLKIRXCLKOfTristateRXD 0TXCLKOfTristateTXDIDESCRIPTIONExternal Clock. This signal is used in synchronous transmission when theexternal timing option has been selected. In the external timing mode the risingedge of EXCLK is used to strobe synchronous transmit data available on theTXD pin. Also used for serial control interface.Receive Clock. Tri-stateable. The falling edge of this clock output is coincidentwith the transitions in the serial received data output. The rising edge ofRXCLK can be used to latch QAM or DPSK valid output data. RXCLK will beactive as long as a carrier is present.Received Digital Data Output. Serial receive data is available on this pin. Thedata is always valid on the rising edge of RXCLK when in synchronous mode.RXD will output constant marks if no carrier is detected.Transmit Clock. Tri-stateable. This signal is used in synchronous transmissionto latch serial input data on the TXD pin. Data must be provided so that validdata is available on the rising edge of the TXCLK. The transmit clock is derivedfrom different sources depending upon the synchronization mode selection. InInternal Mode the clock is generated internally. In External Mode TXCLK isphase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to theRXCLK pin. TXCLK is always active.Transmit Digital Data Input. Serial data for transmission is input on this pin. Insynchronous modes, the data must be valid on the rising edge of the TXCLKclock. In asynchronous modes (2400/1200/600 bitls or 300 baud) no clockingis necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extendedoverspeed mode.IANALOG INTERFACE AND OSCILLATORRXA I Received modulated analog signal input from the phone line.TXA 0 Transmit analog output to the phone line.XTL1 I These pins are for the internal crystal oscillator requiring a 11.0592 MHzXTL2 I/O parallel mode crystal. Two capacitors from these pins to ground are alsorequired for proper crystal operation. Consult crystal manufacturer for propervalues. XTL2 can also be driven from an external clock.3-121

SSI73K224LV.22bis/V.22/V.21 , Bell 212A/1 03Single-Chip ModemPIN DESCRIPTION (continued)SERIAL MICROPROCESSOR INTERFACENAME TYPE DESCRIPTIONAO-A2 I Register Address Selection. These lines carry register addresses and shouldbe valid during any read or write operation.DATA I/O Serial Control Data. Data for a read/write operation is clocked in or out on thefalling edge of the EXCLK pin. The direction of data flow is controlled by theRD pin. RD low outputs data. RD high inputs data.RD I Read. A low on this input informs the SSI 73K322L that data or statusinformation is being read by the processor. The falling edge of the RD signalwill initiate a read from the addresses register. The RD signal must continuefor eight falling edges of EXCLK in order to read all eight bits of the referencedregister. Read data is provided LSB first. Data will not be output unless the RDsignal is active.WR I Wrne. A low on this input informs the SSI73K322L that data or status informationhas been shifted in through the DATA pin and is available for writing to an internalregister. The normal procedure for a wrne is to shift in data LSB first on the DATApin for eight consecutive falling edges of EXCLK and then to pulse WR low. Datais wrnlen on the rising edge of WR.Note: In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the pins;AO, A1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.3-122

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemREGISTER DESCRIPTIONSEight 8-bit internal registers are accessible for controland status monitoring. The registers are accessed inread or write operations by addressing the AO, A 1 andA2 address lines in serial mode, or the ADO, AD1 andAD2 lines in parallel mode. The address lines arelatched by ALE. Register CRO controls the method bywhich data is transferred over the phone line. CR1controls the interface between the microprocessor andthe SSI73K224L internal state. DR is a detect registerwhich provides an indication of monitored modemstatus conditions. TR, the tone control register, controlsthe DTM F generator, answer and guard tones andRXD output gate used in the modem initial connectsequence. CR2 is the primary DSP control interfaceand CR3 controls transmit attenuation and receivegain adjustments. All registers are read/write exceptforDR and IDwhich are read only. Register control andstatus bits are identified below:REGISTER BIT SUMMARYCONTROLMODULAllON MODULAllONMODULAllONREGISTER CRO 000 TYPE TYPEOPllON01 0CONTROL TRANSMIT TRANSMIT ENABLEREGISTER CR1 001 PATTERN PATTERN DETECT1 1 0 INTERRUPTTRANSMIT TRANSMIT TRANSMITMODE MODE MODE2 0TRANSMITENABLEANSWER!ORIGINATEBYPASSSCRAMBLER CLK TEST TESTCONTROL RESET MODE MODE0IDETECT RECEIVE PATTERN RECEIVEREGISTER DR 010LEVEL S1DET DATAUNSCR.SPECIAL CALLMARKCARRIERTONE PROGRESSDETECTDETECTDETECT DETECTSIGNALaUALITYTONE RXD TRANSMIT TRANSMITCONTROL TR 011 OUTPUT GUARD ANSWERREGISTER CONTROL TONE TONETRANSMITDTMFDTMF1!DTMF3 DTMF2 EXTENDEDOVERSPEEDDTMFO/GUARDIANSWERCONTROLREGISTER CR2 1002CONTROLREGISTER CR3 1013SPECIALREGISTER SR 101 TX BAUDCLOCKTRANSMIT RESET TRAIN EQUALIZER16 WAYS1 DSP INHIBIT ENABLETRANSMIT TRANSMIT TRANSMIT TRANSMITATTEN. ATTEN. ATTEN. ATTEN.3 2 0TXD sa saSOURCE SELECT 1 SELECT 010REGISTER 10 110 10 10NOTE:When a register containing reserved controlbits is written into, the reserved bits must beprogrammed as O's.3-123

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemREGISTER ADDRESS TABLEOAM: 0=2400 BITISDPSK: 0=1200 BITIS1=600BITISFSK: 0=103 MODE1=V.21ggg~:~~~~ ----------'0010=EXTSYNCH001hSLAVE SYNCH0100=ASYCH 8 BITs/CHAR0101=ASYCH 9 BITs/CHAR0110=ASYCH 10 BITs/CHAR011hASYCH 11 BITs/CHAR1XOO=FSK0=1800 Hz G.T.2225 Hz ANS TONEGENERATED.1=550 HzG.T.2100 Hz ANS TONEGENERATED &DETECTED (V.21, V.22)O=ACCESS CR3 O=DSP IN O=NORMAL O=RX= TX O=DSP,=ACCESS DEMOD MODE DOTTING ,=RX='6 WAY INACTIVESPECIAL ,=DSP IN CALL hS11=DSPREGISTER PROGRESSACTIVEMODEO=ADAPTEOACTIVEhADAPT EOFROZENO=ADAPTEOIN INIT1=ADAPTEOOK TO ADAPT00XX=73K212L, 322L, 321 L01 XX=73K221 L, 302L10XX= 73K222L1100=73K224L1110=73K324L1101=73K312L3-124

---------------~SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemCONTROL REGISTER 007 0605 0403 02 01 DOCRO MOOUL. MOOUL.000 OPTION TYPE 1MOOUL. TRANSMITTYPE 0 MODE 2TRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 1 MOOEO ENABLE ORIGINATEBIT NO.NAMECONDITIONDESCRIPTION00 Answer/Originate0Selects answer mode (transmit in high band, receivein low band).1Selects originate mode (transmit in lowband,receive inhigh band).01 TransmitEnable01Disables transmit output at TXA.Enables transmit output at TXA.Note: Transmit Enable must be set to 1 to allowactivation of Answer Tone or OTMF.I05 04 03 0205,04, Transmit03,02 Mode0 0 0 0Selects power down mode. All functions disabledexcept digital interface.0 0 0 1Internal synchronous mode. In this mode TXCLK is aninternally derived 600,1200 or 2400 Hz signal. Serialinput data appearing at TXO must be valid on the risingedge of TXCLK. Receive data is clocked out of RXO onthe falling edge of RXCLK.0 0 1 0External synchronous mode. Operation is identical tointernal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 600, 1200 or 2400 Hz clockmust be supplied externally.0 0 1 1Slave synchronous mode. Same operation as othersynchronous modes. TXCLK is connected internally tothe RXCLK pin in this mode.0 1 0 0Selects asynchronous mode - 8 bits/character (1 startbit, 6 data bits, 1 stop bit).0 1 0 10 1 1 0Selects asynchronous mode - 9 bits/character (1 startbit, 7 data bits, 1 stop bit).--Selects asynchronous mode -10 bits/character (1 startbit, 8 data bits, 1 stop bit).0 1 1 1Selects asynchronous mode -11 bits/character (1 startbit, 8 data bits, Parity and/or 1 or 2 stop bits).1 X 0 0Selects FSK operation.06 0506,05 ModulationType1 00 0QAMOPSK0 1FSK3-125

SSI73K224LV.22bis/V.22/V.21 , Bell 212A/1 03Single-Chip ModemCONTROL REGISTER 0 (Continued)D7 D6 D5 D4CRO MODUL. MODUL. MODUL. TRANSMIT000 OPTION TYPE 1 TYPE 0 MODE2BIT NO. NAME CONDITIOND7 Modulation 0Option1D3 D2 D1 DOTRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 1 MODE 0 ENABLE ORIGINATEDESCRIPTIONQAM selects 2400 bit/so DPSK selects 1200 bit/soFSK selects 103 mode.DPSK selects 600 biVs.FSK selects V.21 mode.CONTROL REGISTER 1D7 D6 05TRANSMIT TRANSMIT ENABLECR1 PATTERN PATTERN DETECT001 1 0 INT.BIT NO. NAME CONDITIOND1 DOD1, DO Test Mode 0 00 11 01 1D2 Reset 0D3 Clock Control 011D4 03 02 01 DOBYPASS ClK TEST TESTSCRAMB CONTROL RESET MODE MODE1 0DESCRIPTIONSelects normal operating mode.Analog loopback mode. loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same carrier frequency as the transmitter. Tosquelch the TXA pin, TRANSMIT ENABLE bit as wellas Tone Reg bit D2 must be low.Selects remote digital loopback. Received data islooped back to transmit data internally, and RXD isforced to a mark. Data on TXD is ignored.--- --------------Selects local digital loopback. Internally loops TXDback to RXD and continues to transmit data camier atTXA pin.Selects normal operation.Resets modem to power down state. All cont rol registerbits (CRO, CR1, CR2, CR3 and Tone) are reset to zeroexcept CR3 bit D2. The output of the clock pin will beset to the crystal frequency.Selects 11.0592 MHz crystal echo output at ClK pin.Selects 16 X the data rate, output at ClK pin in DPSK/QAM modes only.3-126

-~SSI73K224LV.22bis/V.22/V.21 , Bell 212A/1 03Single-Chip ModemCONTROL REGISTER 1 (Continued)D7 D6 D5D4 D3 D2 D1 DOTRANSMIT TRANSMIT ENABLE BYPASS ClK TEST TESTCR1 PATTERN PATTERN DETECT SCRAMB CONTROL RESET MODE MODE001 1 0 I NT. 1 0BIT NO. NAME CONDITION DESCRIPTIOND4 Bypass 0 Selects normal operation. DPSK and QAM data is passedScramblerthrough scrambler.1 Selects Scrambler Bypass. Bypass DPSK and QAMdata is routed around scrambler in the transmit path.D5 Enable Detect 0 Disables interrupt at INT pin. All interrupts are normallyInterruptdisabled in power down mode.1 Enables INT output. An interrupt will be generated witha change in status of DR bits D1-D4 and D6. Theanswer tone and call progress detect interrupts aremasked when the TX enable bit is set. Carrier detect ismasked when TX DTMF is activated. All interrupts willbe disabled if the device is in power down mode.D7 D6D7,D6 Transmit 0 0 Selects normal data transmission as controlled by thePatternstate of the TXD pin.0 1 Selects an alternating mark/space transmit pattern formodem testing and handshaking. Also used for S1pattern generation. See CR2 ~it D4.1 0 Selects a constant mark transmit pattern.1 1 Selects a constant space transmit pattern.IDETECT REGISTERD7 D6 D5 D4 D3 D2 D1 DODR RECEIVE S1 RECEIVE UNSCR. CARR. ANSWER CAll SIGNAL010 lEVEL PATTERN DATA MARK DETECT TONE PROG. QUALITYINDICATOR DETECT DETECT DETECT DETECT INDICATORBIT NO. NAME CONDITION DESCRIPTIONDO Signal Quality 0 Indicates normal received signal.Indicator1 Indicates low received signal quality (above averageerror rate). Interacts with special register bits 02, D1.01 Call Progress 0 No call progress tone detected.Detect1 Indicates presence of call progress tones. The callprogress detection circuitry is activated by energy inthe normal 350 to 620 Hz call progress bandwidth.3-127

SSI73K224LV.22bis/V.22/V.21 , Bell 212A/1 03Single-Chip ModemDETECT REGISTER (Continued)07 06 05 04 03 02 01 DODR RECEIVE S1 RECEIVE UNSCR. CARR. ANSWER CALL SIGNAL010 LEVEL PADERN DATA MARK DETECT TONE PROG. QUALITYINDICATOR DETECT DETECT DETECT INDICATORBIT NO. NAME CONDITION DESCRIPTION02 Answer Tone 0 No answer tone detected.Received 1 In Call Init mode, indicates detection of 2225 Hzanswer tone in Bell mode (TR bit 00=0) or 2100 Hz ifin CCID mode (TR bit 00=1). The device must be inoriginate mode for detection of answer tone. Bothanswer tones are detected in demod mode.03 Carrier 0 No carrier detected in the receive channel.Detect 1 Indicated carrier has been detected in the receivedchannel.04 Unscrambled 0 No unscrambled mark.Mark 1 Indicates detection of unscrambled marks in theDetectreceived data. Should be time qualified by software.05 Receive Continuously outputs the received data stream. ThisDatadata is the same as that output on the RXD pin, but itis not disabled when RXD is tri-stated.06 S1 Pattern 0 No S1 pattern being received.Detect1 S1 pattern detected. Should be time qualified by software.81 pattern isdefined as adoubledi-bit (0011 00 ..)unscrambled 1200 biVs DPSK signal. Pattern must bealigned with baud clock to be detected.07 Receive Level 0 Received signal level below threshold, (typical", -25IndicatordBmO); can use receive gain boost (+18 dB).TONE REGISTER1 Received signal above threshold.07 06 05 04 03 02 01 DORXD TRANSMIT TRANSMIT TRANSMIT DTMF 11 DTMF 01TR OUTPUT GUARD ANSWER DTMF DTMF3 DTMF2 EXTENDED ANSWERI011 CONTR. TONE TONE OVER- GUARDSPEEDBIT NO. NAME CONDITION DESCRIPTION06 05 04 DO DO interacts with bits 06, 05, and 04 as shown.DO DTMF 01 X X 1 X Transmit DTMF tones.Answerl X 1 0 0 Select Bell mode answer tone. Interacts with DR bit 02Guard Tone and TR bit 05.X 1 0 1 Select CCID mode answer tone. Interacts with DR bit(Continued) 02 and TR bit 05.3-128

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemTONE REGISTER (Continued)07 06 05RXO TRANSMIT TRANSMITTR OUTPUT GUARO ANSWER011 CONTR. TONE TONEBIT NO. NAME CONDITION00 OTMF 01 06 05 04 00AnswerlGuard Tone1 0 0 01 0 0 10104 01OTMF 11Extended0 0Overspeed 0 104 0202 OTMF 21 0 04WIREFOX0 104 03 02 01 00TRANSMIT DTMF 11 OTMF 01OTMF OTMF3 OTMF 21 EXTENDED ANSWERI4WIRE OVER- GUAROFOX SPEEDDESCRIPTION00 interacts with bits 06, 05, and 04 as shown.-- ~~Select 1800 Hz guard tone.Select 550 Hz guard tone.01 interacts with 04 as shown.Asynchronous QAM or OPSK +1.0% -2.5%. (normal)Asynchronous QAM or OPSK +2.3% -2.5%. (extendedoverspeed)Selects 2 wire duplex or half duplex02 selects 4 wire full duplex in the modulation modeselected. The receive path corresponds to the ANSIORIG bit CRO 00 in terms of high or low band selection.The transmitter is in the same band as the receiver, butdoes not have magnitude filtering or equalization on itssignal as in the receive path.I3-129

SSI73K224LV.22bi s/V.22/V. 21 , Bell 212A/1 03Single-Chip ModemTONE REGISTER (Continued)D7 D6 D5 D4 D3 D2 D1 DORXD TRANSMIT TRANSMIT TRANSMIT DTMF 11 DTMF 0/TR OUTPUT GUARD ANSWER DTMF DTMF3 DTMF 2/ EXTENDED ANSWER/011 CONTR. TONE TONE 4WIRE OVER- GUARDFDX SPEEDBIT NO. NAME CONDITION DESCRIPTIOND3 D2 D1 DOD3, D2, DTMF 3, 0 0 0 o - Programs 1 of 16 DTMF tone pairs that will beD1,DO 2,1,0 1 1 1 1 transmittedwhenTX DTMF andTXenablebit (CRO, bitD1) is set. Tone encoding is shown below:KEYBOARD DTMF CODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGH1 0 0 0 1 697 12092 0 0 1 0 697 13363 0 0 1 1 697 14774 0 1 0 0 770 12095 0 1 0 1 770 13366 0 1 1 0 770 14777 0 1 1 1 852 12098 1 0 0 0 852 13369 1 0 0 1 852 14770 1 0 1 0 941 1336* 1 0 1 1 941 1209# 1 1 0 0 941 1477---A 1 1 0 1 697 1633B 1 1 1 0 770 1633---- .. -C 1 1 1 1 852 1633D 0 0 0 0 941 1633---------D4 TX DTMF 0 Disable DTMF.(Transmit1 Activate DTMF. The selected DTMF tones are trans-DTMF)mitted continuously when this bit is high. TX DTMFoverrides a" other transmit functions.Note: DTM FO - DTM F2 should be set to an appropriate state after DTM F dialing to avoid unintended operation.3-130

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemTONE REGISTER (Continued)D7 D6 D5 D4RXD TRANSMIT TRANSMITTR OUTPUT GUARD ANSWER011 CONTR. TONE TONEBIT NO. NAME CONDITIOND5 04 DOD5 Transmit 0 0 XAnswer Tone 1 0 01 0 1D6 Transmit 0Guard Tone 1D7 RXD Output 0Control 1CONTROL REGISTER 2D3 D2 D1 DOTRANSMIT DTMF 1/ DTMF 01DTMF DTMF3 DTMF 21 EXTENDED ANSWERI4WIRE OVER- GUARDFDX SPEEDDESCRIPTIOND5 interacts with bits D4 and DO as shown. Alsointeracts with DR bit D2 in originate mode. See DetectRegister description.Disables answer tone generator.In answer mode, a Bell 2225 Hz tone is transmittedcontinuously when the Trans~~. Enable bit is set.Likewise, a CCID 21 00 Hz answer tone is transmitted.Disables guard tone generator:.Enables guard tone generator. (See DO for selection ofguard tones.) Bit D4 must be zero.Enables RXD pin. Receive data will be output on RXD.Disables RXD pin. The RXD pin reverts to a highimpedance with internal weak pull-up resistor.ID7 D6 D5 D4D3 D2 D1 DOCR2 SPEC CALL TRANSMIT RESET TRAIN EQUALIZER100 0 REG INIT S1 16WAY DSP INHIBIT ENABLEACCESSBIT NO. NAME CONDITION DESCRIPTIONDO Equalizer 0 The adaptive equalizer is in.its initialized state.Enable 1 The adaptive equalizer is enabled. This bit is used inhandshakes to control when the equalizer should calculateits coefficients._.-D1 Train 0 The adaptive equalizer is active.Inhibit1 The adaptive equalizer coefficients are frozen.D2 RESET DSP 0 The DSP is inactive and all variables are initialized._.-1 The DSP is running based on the mode set by othercontrol bitsD3 16 Way 0 The receiver and transmitter are using the same decisionplane (based on the Modulator Control Mode).1 The receiver, independent of the transmitter, is forcedinto a 16 point decision plane. Used for QAM handshaking.3-131

SSI73K224LV.22bis/V.22/V.21 , Bell 212A/1 03Single-Chip ModemCONTROL REGISTER 2 (Continued)07 06CR2SPEC100 0 REGACCESSBIT NO.NAME04 TransmitS105 Callinit06 SpecialRegisterAccess07 Not used at this timeCONTROL REGISTER 305 04CALLINITCONDITION0101010TRANSMITS103 02 01 DORESET TRAIN EQUALIZER16WAY OSP INHIBIT ENABLEDESCRIPTIONThe transmitter when placed in alternating mark/space. mode transmits 0101 ...... scrambled or not dependenton the bypass scrambler bit.When this bit is 1 and only when the transmitter is placedin alternating mark/space mode by CR1 bits 07, 06, andin OPSK or QAM, an unscrambled repetitive double dibitpattern of 00 and 11 at 1200 biVs (?1) is sent.The OSP is setup to do demodulation and patterndetection based on the various mode bits. Both answertones are detected in demod mode concurrently; TR-DO is ignored.The OSP decodes unscrambled mark, answer toneand call ~rogress tones.Normal CR3 access.Setting this bit and addressing CR3 allows access tothe SPECIAL REGISTER. See the SPECIAL REGIS-TER for details.----Only write zero to this bit.CR310103,02,01,0004TransmitAttenuatorReceiveGain Boosto 0 0 0-Sets the attenuation level of the transmitted Signalin 1dB steps. The default (03-00=0100) is for a transmitlevel of -10 dBmO on the line with the recommendedhybrid transmit gain. The total range is 16 dB.Boost is in the path. This boost does not changereference levels. It is used to extend dynamic range bycompensating for internally generated noise whenreceiving weak signals. The receive level detect signaland knowledge of the hybrid and transmit attenuatorwill determine when boost should be enabled.3-132

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemSPECIAL REGISTERSR10106 05 03 02 01RXUN- TXO SIGNAL SIGNALOSCR SOURCE QUALITY QUALITYDATA LEVEL LEVELSELECT1 SELECTO0605TXBAUO ClKRXUNOSCRDATATXBAUO clock is the transmit baud-synchronous clock that can be used tosynchronize the input of arbitrary quad/di-bit patterns. The rising edge ofTXBAUO signals the latching of a baud-worth of data internally. Synchronousdata to be entered via the TXOAl T bit, CR3 bit D7, should have datatransitions that start 1/2 bit period delayed from the TXBAUO clock edges.This bit outputs the data received before going to the descrambler. This isuseful for sending special unscrambled patterns that can be used forsignaling.I03TXO SOURCEThis bit selects the transmit data source; either the TXO pin if ZERO or theTXOAlT ifthis bit isa ONE. The TRANSMIT PATTERN bits D7 and D6 in CR1override either of these sources.02,01SIGNALOUALITYlEVELSELECTThe signal quality indicator is a logical ZERO when the signal received isacceptable for low error rate reception. It is determined by the value of theMean Squared Error (MSE) calculated in the decisioning process whencompared to a given threshold. This threshold can be set to four levels of errorrate. The SOl bit will be lowforgood or average connections. As the error ratecrosses the threshold setting, the SOl bit will toggle at a 1.66 ms rate. Togglingwill continue until the error rate indicates that the data pump has lostconvergence and a retrain is required. At that point the SOl bit will be a ONEconstantly. The SOl bit and threshold selection are valid for OAM andOPSK only and indicates typical error rate.NOTE: This register is "mapped" and is accessed by setting CR2 bit 06 to a ONE and addressing CR3. Thisregister provides functions to the 73K224l user that are not necessary in normal communications.Bits 07-04 are read only, while 03-DO are read/write. To return to normal CR3 access, CR2 bit D6must be returned to a ZERO.3-133

SSI73K224LV.22bis/V.22/V.21 , Bell 212A/1 03Single-Chip ModemID REGISTER07 06 0510 10 10 10110 3 2 104100BIT NO. NAME CONDITIONDESCRIPTION07,06, Oevice05, 04 IdentificationSignatureELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETERVOO Supply VoltageStorage TemperatureSoldering Temperature (10 sec.)Applied VoltageRATING7V-65 to 150°C260°C-0.3 to VDD+0.3VNote: A" inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and a" outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITSVDD Supply voltage 4.5 5- -5.5 VExternal Components (Refer to Application section for placement.)VREF Bypass capacitor (VREF to GNO) 0.22 j.!FBias setting resistor (Placed between VDO and ISET pins) 1.8 2 2.2 MQISET Bypass capacitor (ISET pin to GNO) 0.22 j.!FVOO Bypass capacitor 1 (VOOto GNO) 0.22 j.!FVOO Bypass capacitor 2 (VOOto GNO) 22 j.!FXTL 1 Load Capacitance Depends on crystal requirements 18 39 pFXTL2 Load Capacitance Depends on crystal requirements 18 27 pFClock Variation (11.0592 MHz) Crystal or external clock -0.01 +0.01 %TA, Operating Free-Air -40 85 °CTemperature3-134

~- -_.-~-SSI73K224LV.22bis/V.22/V.21 , Bell 212A/1 03Single-Chip ModemDC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VOO = recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN NOM MAX UNITS100, Supply Current ClK = 11.0592 MHzISET Resistor = 2 MQ-----1001, Active Operating with crystal oscillator, 18 25 rnAID02, Idle < 5 pF capacitive load on ClK pin 3 5 rnADigital InputsVll, Input low Voltage 0.8 VVIH, Input High VoltageAll Inputs except Reset 2.0 VOO VXTl1,XTl2-----Reset, XTl1 , XTl2 3.0 VDD V--- -IIH, Input High Current VI = VDD 100 J.lAIll, Input low Current VI =OV -200 J.lAReset Pull-down Current Reset = VDD 2 50~---~---.-J.lADigital OutputsVOH, Output High Voltage 10= 10H Min 2.4 VDD VlOUT = -0.4 rnAVOL, Output low Voltage 10 = lOUT = 1.6 mA 0.4 VRXD Tri-State Pull-up Curr. RXD = GND -2 -50 J.lA-------.-~---.-CapacitanceMaximum Capacitive loadClK Maximum permitted load---- _..25 pFI nput Capacitance All Digital Inputs 10 pF~-~- --- ----I3-135

------~~.-SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)PARAMETERS CONDITIONS MINQAM/DPSK ModulatorCarrier Suppression Measured at TXA 35Output Amplitude TX scrambled marks -11.5ATI=0100 (default)FSK Modulator/DemodulatorOutput Freq. Error ClK = 11.0592 MHz -.31Transmit level A TI = 0100 (Default) -11.5Transmit Dotting PatternTXA Output DistortionAll products through BPFOutput Bias Distortion Dotting Pattern measured at RXD -10at RXDReceive level -20 dBm, SNR 20 dBOutput Jitter at RXD Integrated for 5 seconds £15Sum of Bias Distortion and Integrated for 5 secondsOutput Jitter -17Answer Tone Generator (2100 or 2225 Hz)Output Amplitude ATI = 0100 (Default level) -11.5Not in V.21Output Distortion Distortion pro

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERS CONDITIONS MIN NOM MAX UNITSCarrier DetectReceive Gain = On for lower input level measl!r~mentsThreshold All Modes -48 -43 dBmOHysteresis All Modes 2-- ---Delay Time FSK 70 dBmO to -6 dBmO 25 ._-_ ..37 ms70 dBmO to -40 dBmO 25 37 msDPSK -70 dBmO to -6 dBmO 7--17 ms-70 dBmO to -40 dBmO 7_. ---17 msOAM -70 dBmO to -6 dBmO 25-_.-37 ms-70 dBmO to -40 dBmO 25 37 msHold Time FSK -6 dBmO to -70 dBmO 25------37 ms-40 dBmO to -70 dBmO 15 30 ms- -DPSK -6 dBmO to -70 dBmO 20 29 ms-40 dBmO to -70 dBmO 14- -._. -_.-21 msOAM -6 dBmO to -70 dBmO 25----32 ms-40 dBmO to -70 dBmO 18-- ---------28 msAnswer Tone Detectors DPSK ModeDetect Level -48 -43 dBmODetect Time Call Init Mode, 2100 or 2225 Hz 6 50 msHold Time 6 50 msPattern DetectorsDPSK ModeS1 Pattern-"--Delay Time For signals from -6 to -40 dBmO, 10 55 msHold Time -6 to -40 dBmO, Demod Mode 10 45 ms.. _----Unscrambled MarkDelay Time For signals from -6 to -40 10 45 msHold Time caliinit Mode 10 45 ms- --Receive level Indicator---Detect On -22 -28 dBmOValid after Carrier Detect DPSK Mode 1 4- ---_.._-7 msOutput Smoothing Filter--Output Impedance TXA pin 200- ---300 QOutput load TXA pin; FSK Single 10 KQTone out for THD = -50 dB-----50 pFin .3 to 3.4 kHz rangeMaximum Transmitted 4 kHz, Guard Tones off -35 dBmOEnergy 10kHz, Guard Tones off -55 dBmO---,----12 kHz, Guard Tones off -65 dBmOI3-137

551 73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSAnti Alias Low Pass FilterOut of Band Signal Energy(Defines Hybrid Trans-Hybrid loss requirements)Transmit AttenuatorCONDITIONSLevel at RXA pin with receiveBoost EnabledScrambled data at 2400 bit/sin opposite bandSinusoids out of bandRange of Transmit Level Default A TT =0100 (-10 dBmO) 1111-0000Step AccuracyOutput ImpedanceClock Noisecarrier OffsetCapture RangeRecovered ClockCapture RangeGuard Tone GeneratorTone AccuracyTone Level(Below QAM/DPSKOutput)Harmonic DistortionTXA pin; 153.6 kHzOriginate or Answer% of frequency (originate oranswer)550 Hz1800 Hz550 Hz1800 Hz550 Hz(700 to 2900 Hz) 1800 HzTiming (Refer to Timing Diagrams)Parallel ModeTALTLATLCTCLTRDTLLTRDFTRWCSI Addr. setup before ALE LowCSI Addr. hold after ALE LowALE Low to RDIWR LowRD/WR Control to ALE HighData out from RD LowALE widthData float after RD HighRDwidthMIN NOM MAX UNITS-14 dBm-9 dBm-21 -6 dBmO---0.15 +0.15 dB200 300 zJ 1.5_L __ ±_? ... J ±7mVrmsHz-0.02 ]+002 %+1.2 0/0--f----- ~---0.8-4.5 -3.0 -1.5 dB-7.5 -6.1 -4.5 dB------ ---50 dB---_.-50 dB_.30 ns6 ns40 ns10 ns-90 ns25 ns40 ns--70 ns3-138

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERS CONDITIONS MIN NOM MAX UNITSParallel Mode (Continued)TWW WRwidth 70 ns-----TDW Data setup before WR High 70 nsTWD Data hold after WR High 20 ns--Serial Mode----~-TRCK Clock High after RD Low 250 T1 ns--------f--------TAR Address setup before RD Low 0 nsTRA Address hold after RD Low 350 ns- --TRD RD to Data valid 300 nsTRDF Data float after RD High 40 ns-- --------TCKDR Read Data out after Falling 300 nsTWWEdge of EXCLK-WRwidth 350---_ ..._-nsTAW Address setup before WR Low 50 ns-~ -------TWA Address hold after Rising 50 nsEdge of WRTCKDW Write Data hold after Falling 200 nsEdge of EXCLKTCKW WR High after Falling 330 T1 + T2 nsEdge of EXCLKTDCK Data setup before Falling 50 nsEdge of EXCLKT1, T2 Minimum Period 500 nsINOTE: T1 and T2 are the low/high periods, respectively, of EXCLK in serial mode.3-139

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE~TlC TRW 1RD --+--+ADO-AD7TCl~JTlC 1 TWW JWR---~TlA TRD TRDF ~DL TAL.. ~ J.!.I ~ TOW '"--K ADDRESS >!--K READ DATA >!--K ADDRESS ~A~cs -=-1- -4--~- -4-READ TIMING DIAGRAM (SERIAL VERSION)EXCLKAO-A2DATAWRITE TIMING DIAGRAM (SERIAL VERSION)--+1 T2 1--EXCLK--+1 T1AO-A2 ---/-----------------~-_tf;:,DATA3-140

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemAPPLICATIONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK -Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a OAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes. Two typical OMarrangements are shown: one for a split ±5 or ±12 Vdesign and one for a single 5 V design. These diagramsare for reference only and do not represent productionreadymodem designs.K-Series devices are available with two control interfaceversions: one for a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039148 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontrollers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the serial mode, as explained in the datasheet pin description.In most applications the control/erwill monitor the serial 3data for commands from the DTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent over the sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.RS232LEVELCONVERTERSC9.1 nF+ C822nFCI390 pFCACB L...-'"l...t...="-­CC L...-'"l-,-=,,----,CDCFWRALEasSSIK·SERIESLOWPOWERFAMILYBABBDADODB

SSI73K224LV.22b is/V. 22/V. 21 , Bell 212A/1 03Single-Chip ModemDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing at the transformer, making the transmitsignal common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This Circuit(Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a single 5 volt supply. BecauseDTMF tones utilize a higher amplitude than data, thesesignals will clip if a single-ended drive approach isused. The bridged driver uses an extra op-amp (U1 A)to invert the signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-amp then supplies half the drive signalto the transformer. The receive amplifier (U1 C) picksoff its signal at the junction of the impedance matchingresistor and the transformer. Because the bottom leg ofthe transformer is being driven in one direction by U1 Aand the resistor is driven in the opposite direction at thesame time by U1 B, the junction of the transformer andresistor remains relatively constant and the receivesignal is unaffected.DESIGN CONSIDERATIONSSilicon Systems' 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.C1390pFR437.4K 1%. C30.1""~ f---------_____ ---1RING ~----------------~FIGURE 2: Single 5V Hybrid Version3-142

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemUnlike digital logic circuitry, modem designs mustproperly contend with precise frequency tolerancesand very low level analog signals, to ensure acceptableperformance. Using good analog circuit design practiceswill generally result in a sound design. Followingare additional recommendations which should betaken into consideration when starting new designs.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01% accuracy.In order for a parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capaCitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LA YOUT CONSIDERATIONSGood analogldigital design rules must be used to controlsystem noise in order to obtain highest performance inmodem designs. The more digital circuitry present onthe PC board, the more this attention to noise control isneeded. The modem should be treated as a high impedanceanalog device. A 22 mF electrolytic capacitor inparallel with a 0.22 mF ceramic capacitor between VDDand GND is recommended. Liberal use of groundplanes and larger traces on power and ground are alsohighly favored. The ISET resistor and capacitor shouldbe mounted near the ISET pin, away from digital signals.High speed digital circuits tend to generate a significantamount of EMI (Electro-Magnetic Interference) whichmust be minimized in order to meet regulatory agencylimitations. To accomplish this, high speed digital devicesshould be locally bypassed, and the telephone lineinterface and K-Series device should be located close toeach other near the area of the board where the phoneline connection is accessed. To avoid problems, powersupply and ground traces should be routed separately tothe analog and digital functions on the board, and digitalsignals should not be routed near low level or highimpedance analog traces. The analog and digitalgrounds should only connect at one pOint near the K­Series device ground pin to avoid ground loops. The K­Series modem IC's should have both high frequencyand low frequency bypassing as close to the package aspossible.3-143MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line simulator, operatingunder computer control. All tests were run fullduplex,using a Hayes SmartModem 2400 as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and all signal-to-noise (SIN) ratios reflect 3total power measurements similar to the CCITT V.56measurement specification. The individual tests aredefined as follows.SER vs. SINThis test measures the ability of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a modem will exhibit betterBER-performance test curves receiving in the lowband than in the high band.SER vs. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamiCrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels. The width of the "bowl" ofthese curves, taken at the BER point, is the measure ofdynamic range.

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip Modem551 73K224L BER vs 5/N-DP5K LOW BANDW~a:5 10-4a:a:wI::CD10- 2 "'"10- 3 1\\tI LOW BAND RECEIVEJ -30dBmDPSK OPERATION\~1200 BITtS\\\ ~\~... .,...., '>--'1\ \~/"\H Cl, C2, FLAT,\10- 5 \1110- 6 \ \4 6 8 10 12 14 16SIGNAL TO NOISE (dB)SSI73K224LBER vs S/N-QAM-LOW BAND10- 2 LOW BAND RECEIVE-30dBmII OAM OPERATION2400 BITtS10- 3 ,w~a:a:0 10'"a:a:wI::III~~'~~ ~~I~ ./ ~0 I--I--~,'c2)~10- 5 ~l IT1\10- 6 1\\8 10 12 14 16 18 20SIGNAL TO NOISE (dB)\\~551 73K224L BER vs S/N-DPSK HIGH BAND10- 2 "t1\,\ J HIGH BAND RECEIVE\~\I -30dBmDPSK OPERATION1200 BITtS1\'1\ 10- 3 \\I Cl_ 3002, FLAT\1\ ,..,vw~a:a:0 10'"\"a:a: \wI::\ \III~\I\10- 5 /v \1 \r--- 1.--"---,I~~ 1\ \\ \10- 6 \4 6 8 10 12 14 16SIGNAL TO NOISE (dB)SSI73K224LBER vs S/N-QAM-HIGH BAND10- 2 ~\II HIGH BAND RECEIVE I-30dBmII OAM OPERATION2400 BITtS~ ~.~ ~~J10- 3~\Ir;-~ ~\\w 1L....:r-' ...........~~~a:a:0a: 10'"a: 3002 t-.... ,\' 1/wt::l' ~.1CD\~r"c2l.(\10- 5 l\ ~~1\'\\1\ \10- 6 \'8 10 12 14 16 18 20SIGNAL TO NOISE (dB)3-144

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemSSI 73K224L BER vs CARRIER OFFSET10- 3HIGH BAND RECEIVEI -30 dBmOAM OPERATION2400 BITtStLJ.J~a:a:0 10-4a:a:LJ.JI-D510-5H C217dBSiN\,I 300217 dB SIN'-.. ,..-"':;1-"-"'II-12 -8 -4 4 12CARRIER OFFSET (HZ)3-145

",·.I:,SSI73K224LV. 22bis/V. 22/V.21 , Bell 212A/1 03Single-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)44-Lead PLCCI~!i'4'· .~.",.·.·::.:.·,•.•.~':::~t ,.6iRXAVREFRESETISETRXCLKRXDTXDEXCLKTXCLKINTTXACLKXTL1XTL2ADOAD1AD2AD3AD4AD5AD6AD7ALEWRADGNDRXAVREFRESETISETRXCLKRXDTXDcsEXCLKTXCLKjNfTXAVDD.. ~:,,:::::::::':.:::~~~r?41 4032 31 302928272632-Lead PLCC 252423222115 16 17 18 19 20N/C: jJw¢.:\::r::::: ,: :,tMlWt?:",:\@$.tt):': :,'t~~#.8::::;:):5*f}?::,\~I\:)

SSI73K224LV.22bis/V.22/V.21, Bell 212A/1 03Single-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)ADONrcNrcNrcNrc1e64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 492 U464544gNrcISETNrCRXCLKN/CAD1Nrc4342RXDN/CAD241N/CAD3AD4AD5AD6NrcAD7NrcNrc4010391138123713361435153416 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33TXDNrccsEXCLKNrcNrcNrcN/CI64-Lead TQFPCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTION ORDER NO. PKG.MARKSSI 73K224L with Serial Bus Interface22-Pin Plastic Dual-In-Line 73K224LS-1 P 73K224LS-1 PSSI 73K224L with Parallel Bus Interface28-Pin Plastic Dual-In-Line 73K224L-IP 73K224L-IP28-Pin Plastic Leaded Chip Carrier 73K224L-281H 73K224L-281H----32-Pin Plastic Leaded Chip Carrier 73K224L-321H 73K224L-321H44-Pin Plastic Leaded Chip Carrier 73K224L-IH 73K224L-IH52-Lead Quad Flat Pack Package 73K224L-IG 73K224L-IG64-Lead Thin Quad Flat Pack Package 73K224L-IGT 73K224L-IGTNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheetis current before placing orders.Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-69140194- rev.Protected by the following patents:(4,777,453), (4,789,995), (4,870,370), (4,847,868), (4,866,739)3-147 ©1989 Silicon Systems, Inc.

Notes:3-148

DESCRIPTIONThe 551 73K302L is a highly integrated single-chipmodem Ie which provides the functions needed toconstruct a Bell 202, 212A and 103 compatiblemodem. The 551 73K302L is an enhancement of the551 73K212L single-chip modem with Bell 202 modefeatures added. The 73K302L is capable of 1200 or0-300 biVs full-duplex operation over dial-up lines.4-wire full-duplex capability and a low speed backchannel are also provided in Bell 202 mode. The551 73K302L recognizes and generates a 900 Hz softcarrier turn-off tone, and allows 103 for 300 bit/s F5Koperation. The SSI73K302L integrates analog, digital,and switched-capacitor array functions on a singlesubstrate, offering excellent performance and a highlevel of functional integration in a single 28 or 22-pin DIP configuration. The 551 73K302L operatesfrom a single +5V supply with very low powerconsumption.The 551 73K302L includes the DP5K and F5K modulator/demodulatorfunctions, call progress and handshaketone monitors, test modes, and a tone generatorcapable of producing DTMF, answer, and 900 Hz softcarrier turn-off tone. This device supports Bell202, 212A and 103 modes of operation, allowing both(Continued)FEATURESSSI73K302LBell 212A, 103, 202Single-Chip Modem'#""h"'61&-"1January 1994One-ch ip Bell 212A, 103 and 202S/T standardcompatible modem data pumpFull-duplex operation at 0-300 bitls (FSK), 1200 bitls(DPSK) or 0-1200 bitls (FSK) forward channel with orwithout 0-150 bitls back channelFull-duplex 4-wire operation in Bell 202 modePin and software compatible with other551 K-Series 1-chip modemsInterfaces directly with standard microprocessors(8048, 80C51 typical)Serial (22-pin DIP) or parallel microprocessor busfor controlSerial port for data transferBoth synchronous and asynchronous modes ofoperationCall progress, carrier, precise answer tone(2225 Hz), soft carrier turn-off (SCT), and FSK markdetectorsDTMF, answer, and SCT tone generatorsTest modes available: ALB, DL, RDL, Mark, Space,Alternating bit patternsCMOS technology for low power consumptionusing 35 mW @ 5V from a single power supplyIBLOCK DIAGRAMPIN DIAGRAMAOO-AD7elKXTL1RD 0----+1WR o---~ALE o---~CS o---~RESET o---~TXARXAXTl2ADOAD1AD2AD3INT o-------lTXD 0------......RXD o--------~SMARTDIALING&F~~~SJ4.------..JAD4AD5ADSAD?ALEWRRD0194 - rev. 3-149

SSI73K302LBell 212A, 103, 202Single-Chip ModemDESCRIPTION (Continued)synchronous and asynchronous communications.The SSI73K302L is designed to appearto the systemsdesigner as a microprocessor peripheral, and will easilyinterlace with popular one-chip microprocessors(80C51 typical) for control of modem functions throughits8-bit multiplexed address/data bus orvia an optionalserial command bus. An ALE control line simplifiesaddress demultiplexing. Data communications occursthrough a separate serial port only.The SSI73K302L is ideal for use in either free standingor integral system modem products where multi-standarddata communications is desired. Its high functionality,low power consumption and efficient packagingsimplify design requirements and increase systemreliability. A complete modem requires only the additionof the phone line interlace, a modem controller,and RS232 level converter for a typical system.Tri-mode capability in one-chip allows full-duplex Bell212 and 103 operation or assymetrical Bell 202Soperation overthe 2-wire switched telephone network.202T mode full-duplex operation at 1200 bit/s is alsopossible when operating on 4-wire leased lines.A soft carrier turn-off feature facilitates fast line turnaround when using the 202S mode for half-duplexapplications.Th.e SSI 73K302L is part of Silicon Systems K-Seriesfamily of pin and function compatible single-chipmodem products. These devices allow systems to beconfigured for higher speeds and Bell or CCITT operationwith only a single component change.OPERATIONASYNCHRONOUS MODEData transmission for the DPSK mode requires thatdata ultimately be transmitted in a synchronous fashion.The SSI 73K302L includes ASYNC/SYNC andSYNC/ASYNC converters which delete or insert stopbits in order to transmit data at a regular rate. Inasynchronous mode the serial data comes from theTXD pin into the ASYNC/SYNC converter. TheASYNC/SYNC converter accepts the data provided onthe TXD pin which normally must be 1200 biVs + 1.0%,2.5%. The rate converter will then insert or delete stopbits in orderto output a signal which is 1200 biVs ± .01 %(±.01% is the required synchronous data rateaccuracy).The SYNC/ASYNC converter also has an extendedoverspeed mode which allows selection of an outputoverspeed range of either +1% or +2.3%. In the extendedoverspeed mode, stop bits are output at 7/8 thenormal width.The serial data stream from the transmit buffer or therate converter is passed through the data scramblerand onto the analog modulator. The data scramblercan be bypassed under processor control whenunscrambled data must be transmitted. If serial inputdata contains a break Signal through one character(including start and stop bits) the break will beextended to at least 2 • N + 3 bits long (where N is thenumber of transmitted bits/character).Serial data from the demodulator is passed firstthrough the data descrambler and then through theSYNC/ASYNC converter. The ASYNC/ASYNC converterwillreinsert any deleted stop bits and output dataat an intra-character rate (bit-to-bit timing) of no greaterthan 1219 bit/so An incoming break signal (low throughtwo characters) will be passed through without incorrectlyinserting a stop bit.SYNCHRONOUS MODEThe Bell 212A standard defines synchronous operationat 1200 biVs. Operation is similar to that of theasynchronous mode except that data must be synchronizedto a provided clock and no variation in datatransfer rate is allowable. Serial input data appearing atTXD must be valid on the rising edge of TXCLK.TXCLK is an internally derived signal in internal modeand is connected internally to the RXCLK pin in slavemode. Receive data at the RXD pin is clocked out onthe falling edge of RXCLK. The ASYNCH/SYNCHconverter is bypassed when synchronous mode isselected and data is transmitted out at the same rate asit is input.DPSK MODULATOR/DEMODULATORIn DPSK mode the SSI 73K302L modulates a serial bitstream into di-bit pairs that are represented by fourpossible phase shifts as prescribed by the Bell 212Astandards. The base-band signal is then filtered toreduce intersymbol interference on the bandlimited2-wire telephone line. Transmission occurs using ei-3-150

SSI73K302LBell 212A, 103,202Single-Chip Modemther a 1200 Hz (originate mode) or 2400 Hz (answermode) carrier. Demodulation is the reverse of themodulation process, with the incoming analog signaleventually decoded into di-bits and converted back toa serial bit stream. The demodulator also recovers theclock which was encoded into the analog signal duringmodulation. Demodulation occurs using either a1200 Hz carrier (answer mode or ALB originate mode)or a 2400 Hz carrier (originate mode or ALB answermode). The SSI 73K302L uses a phase locked loopcoherent demodulation technique for optimumreceiver performance.FSK MODULATOR/DEMODULATORThe FSK modulator produces a frequency modulatedanalog output signal using two discrete frequencies torepresent the binary data. Bell 103 mode uses 1270and 1070 Hz (originate, mark and space) or 2225 and2025 Hz (answer, mark and space). Bell 202 modeuses 1200 and 2200 Hz for the main channel and 387and 487 Hz for the back channel. The modulation rateof the back channel is up to 150 baud. Demodulationinvolves detecting the received frequencies anddecoding them into the appropriate binary value. Therate converter and scrambler/descrambler are automaticallybypassed in the 103 or 202 modes.PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and provide compromise delay equalizationand rejection of out-of-band signals in thereceive channel. Amplitude and phase equalizationare necessary to compensate for distortion of thetransmission line and to reduce intersymbol interferencein the bandlimited receive signal. The transmitsignal filtering approximates a 75% square root ofraised Cosine frequency response characteristic.AGCThe automatic gain control maintains a signal level atthe input to the demodulators which is constant towithin 1 dB. It corrects quickly for increases in signalwhich would cause clipping and provides a totalreceiver dynamic range of >45 dB.PARALLEL BUS INTERFACEFour 8-bit registers are provided for control,optionselect and status monitoring. These registers are ad-dressed with the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as four consecutive memory locations.Two control registers and the tone register areread/write memory. The detect register is read onlyand cannot be modified except by modem response tomonitored parameters. The parallel bus interface is notavailable in the 22-pin package.SERIAL COMMAND INTERFACEThe serial command interface allows access to theSSI 73K302L control and status registers via a serialcommand port. In this mode the AO , A1 and A2 linesprovide register addresses for data passed through the 3data pin under control of the RD and WR lines. A readoperation is initiated when the RD line is taken low. Thefirst bit is available after RD is brough low and the nextseven cycles of EXCLK will then transfer out seven bitsof the selected address location LSB first. A write takesplace by shifting in eight bits of data LSB first for eightconsecutive cycles of EXCLK. WR is then pulsed lowand data transfer into the selected register occurs onthe rising edge of WR.SPECIAL DETECT CIRCUITRYThe special detect circuitry monitors the received analogsignal to determine status or presence of carrier,answer tone and weak received signal (long loopcondition), special tones such as FSK marking and the900 Hz soft carrier turn-off tone are also detected. Ahighly frequency selective call progress detector providesadequate discrimination to accurately detectlower quality call progress signals.DTMF GENERATORThe DTMF generator will output one of 16 standardtone pairs determined by a 4-bit binary value and TXDTMF mode bit previously loaded into the tone register.Tone generation is initiated when the DTMF modeis selected using the tone register and the transmitenable (CRO bit D1) is changed from 0 to 1.SOFT CARRIER TURN-OFF TONE GENERATORThe soft carrier turn-off tone generator will output a900 Hztone. When activated in Bell 202 main channeltransmit mode, the output signal will shift to 900 Hz,maintaining phase continuity during the transition.3-151

SSI73K302LBell 212A, 103, 202Single-Chip ModemPIN DESCRIPTIONPOWERNAME 28·PIN 22·PINGND 28 1VDD 15 11VREF 26 21ISET 24 19TYPEII0IDESCRIPTIONSystem Ground.Power supply input, 5V ±10%. Bypass with .1 and 22 JlFcapacitors to GN D.An internally generated reference voltage. Bypass with.1 JlF capacitor to GND.Chip current reference. Sets bias current for op-amps. Thechip current is set by connecting this pin to VDD through a2 Mn resistor. ISET should be bypassed to GND with a.1 JlF capacitor.PARALLEL MICROPROCESSOR INTERFACEALE 12 - IADO-AD7 4-11 - I/OCS 20 - IClK 1 2 0INT 17 13 0RD 14 - IRESET 25 20 IAddress latch enable. The falling edge of ALE latches theaddress on ADO-AD2 and the chip select on CS.Address/data bus. These bidirectional tri-state multiplexedlines carry information to and from the internalregisters.Chip select. A low on this pin during the falling edge of ALEallows a read cycle or a write cycle to occur. ADO-AD7 willnot be driven and no registers will be written if CS (latched)is not active. The state of CS is latched 0 n the falling edgeof ALE.Output clock. This pin is selectable under processor controlto be either the crystal frequency (for use as a processorclock) or 16 x the data rate for use as a baud rate clock inDPSK mode only. The pin defaults to the crystal frequencyon reset.I nterrupt. This open drain output signal isused to inform theprocessor that a detect flag has occurred. The processormust then read the detect register to determine whichdetect triggered the interrupt. INT will stay low until theprocessor reads the detect register or does a full reset.Read. A low requests a read of the SSI73K302l internalregisters. Data cannot be output unless both RD and thelatched CS are active or low.Reset. An active high signal on this pin will put the chip intoan inactive state. All control register bits (CRO, CR1, Tone)will be reset. The output of the ClK pin will be set to thecrystal frequency. An internal pull down resistor permitspower on reset using a capacitor to VDD.3-152

SSI73K302LBell 212A, 103,202Single-Chip ModemPIN DESCRIPTION (Continued)PARALLEL MICROPROCESSOR INTERFACE (Continued)NAME 2S-PIN 22-PIN TYPE DESCRIPTIONWR 13 - I Write. A low on this informs the SSI 73K302L that data isavailable on ADO-AD7 for writing into an internal register.Data is latched on the rising edge of WR. No data is writtenunless both WR and the latched CS are active low.SERIAL MICROPROCESSOR INTERFACEAO-A2DATARDWRNote:- 5-7 I Register Address Selection. These lines carry registeraddresses and should be valid during any read or writeoperation.- 8 I/O Serial Control Data. Data for a read/write operation isclocked in or out on the falling edge of the EXCLK pin. Thedirection of data flow is controlled by the RD pin. RD lowoutputs data. RD high inputs data.- 10 I Read. A low on this input informs the SSI 73K302L thatdata or status information is being read by the processor.The falling edge of the RD signal will initiate a read from theaddressed register. The RD signal must continue for eightfalling edges of EXCLK in order to read all eight bits of thereferenced register. Read data is provided LSB first. Datawill not be output unless the RD signal is active.----- -------- 9 I Write. A low on this input informs the SSI73K302L that dataor status information has been shifted in through the DATApin and is available for writing to an internal register. Thenormal procedure for a write is to shift in data LSB first onthe DATA pin for eight consecutive falling edges of EXCLKand then to pulse WR low. Data is written on the rising edgeofWR.-In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with thepins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.-The serial control mode is provided in the parallel control versions by tying ALE high and CS low.In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,respectively.I3-153

SSI73K302LBell 212A, 103, 202Single-Chip ModemPIN DESCRIPTION (Continued)DTE USER INTERFACENAME 28-PIN 22-PINEXCLK 19 15RXCLK 23 18RXD 22 17TXCLK 18 14TXD 21 16TYPEI000IDESCRIPTIONExternal Clock. This signal is used only in synchronousDPSK transmission when the external timing option hasbeen selected. In the external timing mode the rising edgeof EXCLK is used to strobe synchronous DPSK transmitdata available on the TXD pin. Also used for serial controlinterface.Receive Clock. The falling edge of this clock output iscoincident with the transitions in the serial received DPSKdata output. The rising edge of RXCLK can be used to latchthe valid output data. RXCLK will be valid as long as acarrier is present. In Bell 202 mode a clock which is 16 x1200 or 16 x 150 baud data rate is output.Received Data Output. Serial receive data is available onthis pin. The data is always valid on the rising edge ofRXCLK when in synchronous mode. RXD will output constantmarks if no carrier is detected.Transmit Clock.This signal is used only in synchronousDPSK transmission to latch serial input data on the TXDpin. Data must be provided so that valid data is availableon the rising edge of the TXCLK. The transmit clock isderived from different sources depending upon the synchronizationmode selection. In Internal Mode the clock is1200 Hz generated internally. In External Mode TXCLK isphase locked to the EXCLK pin. In Slave Mode TXCLK isphase locked to the RXCLK pin. TXCLK is always active. InBell 202 mode the output is a 16 x 1200 baud clock or 16x 150 baud to drive a UART.Transmit Data Input. Serial data for transmission is appliedon this pin. In synchronous modes, the data must be validon the rising edge of the TXCLK clock. In asynchronousmodes (1200 or300 baud) no clocking is necessary. DPSKmust be 1200 biVs +1%, -2.5% or +2.3%, -2.5 % inextended overspeed mode.ANALOG INTERFACE AND OSCILLATORRXA 27 22 ITXA 16 12 0XTL1 2 3 IXTL2 3 4 IReceived modulated analog signal input from the telephoneline interface.Transmit analog output to the telephone line interface.These pins are for the internal crystal oscillator requiringa 11.0592 MHz parallel mode crystal and two load capacitorsto Ground. XTL2 can also be driven from an externalclock.3-154

SSI73K302LBell 212A, 103,202Single-Chip ModemREGISTER DESCRIPTIONSFour a-bit internal registers are accessible for controland status monitoring. The registers are accessed inread or write operations by addressing the AO and A 1address lines in serial mode, orthe ADO and AD11inesin parallel mode. The ADO and AD1lines are latched byALE. Register CRO controls the method by which datais transferred over the phone line. CR1 controls theinterface between the microprocessor and the551 73K302L internal state. DR is a detect registerwhich provides an indication of monitored modemstatus conditions. TR, the tone control register, controlsthe DTMF generator, answer and guard tones andRXD output gate used in the modem initial connectsequence. All registers are read/write except for DRwhich is read only. Register control and status bits areidentified below:REGISTER BIT SUMMARYNOTE:When a register containing reservedcontrol bits is written into, the reserved bitsmust be programmed as O's.3-155

SSI73K302LBell 212A, 103, 202Single-Chip ModemREGISTER ADDRESS TABLE0~103 FSK1=202 FSKOOOO=PWR DOWNll00=FSK0010-EXT SYNCH0011 =SLA VE SYNCH01 OO=ASYNCH 8 BITs/CHAR0101.ASYNCH 9 BITs/CHAR0110.ASYNCH 10 BITSICHAR0111=ASYNCH 11 BITSICHARll00.FSK BELL 103 OR 202O=DISABLE IN 212, 103 MODES:TXA OUTPUT O=ANSWERl=ENABLE l=ORIGINATETXAOUTPUTIN 202 MODE:O.RECEIVE @ 1200 BIT/S,TRANSMIT @ 150 BIT/S1.RECEIVE@ 150 BIT/S,TRANSMIT @ 1200 BIT/SO=ENABLEl=DISABLEO=NORMAL1=BYPASSSCRAMBLERl=ADD EXTRAPHASE Ea.IN 202 ONLYO=XTAL O=NORMAL1-16 X DATA l=RESETRATE OUTPUTATCLK PIN INDPSK MODE ONLYO=NORMAL OPERATIONl=FULL DUPLEX IN 202 MODE0=1%1=2.5%0=900 HZ SCT TONE IFIN ANSWER MODE.2225 HZ ANSWER TONEIN 103 OR 212 ORIGINATEMODESl=FSK MARKOOXX.73K212L, 322L, 321 L01 XX-73K221 L, 302L10XX.73K222Lll00-73K224L1110.73K324L1101.73K312L3-156

SSI73K302LBell 212A, 103,202Single-Chip ModemIICONTROL REGISTER 004 03 0201 DO07 05CRO MOOUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/000 OPTION MODE 3 MOOE2 MODE 1 MODE 0 ENABLE ORIGINATEBIT NO. NAME CONDITION DESCRIPTIONDO Answer/ 0 Selects answer mode in 103 and 212A modes (trans-Originate mit in high band, receive in low band) or in Bell 202mode, receive at 1200 bit/s and transmit at 150 biVs.1 Selects originate mode in 103 and 212A modes (transmitin low band, receive in high band) or in Bell 202mode, receive at 150 bit/s and transmit at 1200 bit/soNote: This bit works with TR bit DO to program specialtones detected in Tone Register. See detect and toneregisters.01 Transmit 0 IIs~nIRS transmit output at TXAEnable1 Enables transmit output at TXA.Note: Answer tone and OTMF TX control require TXenable.I05,04,03, Transmit 0 0 0 0 Selects power down mode. All functions disabled02 Mode except digital interface.0 0 0 1 Internal synchronous mode. In this mode TXCLK is aninternally derived 1200 Hz Signal. Serial input dataappearing at TXO must be valid on the rising edge ofTXCLK. Receive data is clocked out of RXO on thefalling edge of RXCLK.0 0 1 0 External synchronous mode. Operation is identical tointernal synchronous, but TXCLK is connected internallytoEXCLK pin, and a 1200 Hz ± 0.01% clock mustbe supplied externally.0 0 1 1 Slave synchronous mode. Same operation as othersynchronous modes. TXCLK is connected internally tothe RXCLK pin in this mode.0 1 0 0 Selects OPSK asynchronous mode - 8 bits/character(1 start bit, 6 data bits, 1 stop bit).0 1 0 1 Selects OPSK asynChronous mode - 9 bits/character(1 start bit, 7 data bits, 1 stop bit).0 1 1 0 Selects OPSK asynchronous mode - 10 bits/character(1 start bit, 8 data bits, 1 stop bit).0 1 1 1 Selects OPSK asynchronous mode - 11 bits/character(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).3-157II.

SSI73K302LBell 212A, 103, 202Single-Chip ModemCONTROL REGISTER 0 (Continued)CRO MODUL.000 OPTIOND7 D5 D4 D3 D2 D1 DOTRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 3 MODE 2 MODE 1 MODE 0 ENABLE ORIGINATEBIT NO. NAME CONDITION DESCRIPTION~-------+--------~------------~-------~-------------D7ModulationOptionD7 D5 D4Selects:~c:vn('''lrnrlnl"0."S mode at 1200 biVs.CONTROL REGISTER 1D7D6TRANSMIT TRANSMITCR1 PATTERN PATTERN001 1 0D5ENABLEDETECTINTER.D4 D3 D2 D1 DOBYPASS ClK TEST TESTSCRAMB/ CONTROL RESET MODE MODEADD 1 aPH. EO.BIT NO. NAME CONDITIOND1 DOD1,DO Test Mode 0 00 11 01 1D2 Reset 01DESCRIPTIONSelects normal operating mode.Analog loopback mode. loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same center frequency as the transmitter. Tosquelch the TXA pin, transmit enable must be forcedlow. Not supported in FDX202 mode.Selects remote digital loopback. Received data islooped back to transmit data internally, and RXD isforced to a mark. Data on TXD is }gnored.Selects local digital loopback. Internally loops TXDback to RXD and continues to transmit carrier fromTXA pin.-Selects normal operation.Resets modem to power down state. All controlregister bits (CRO, CR1, Tone) are reset to zero. Theoutput of the ClK pin will be set to the crystalfrequency.3-158

SSI73K302LBell 212A, 103,202Single-Chip ModemCONTROL REGISTER 1 (Continued)07 06 05TRANSMIT TRANSMIT ENABLECR1 PATTERN PAITERN DETECT001 1 0 INTER.BIT NO. NAME CONDITION03 ClK Control 004* Bypass 0Scrambler/Add PhaseEqualization105 Enable Detect 0Interrupt1104 03 02 01 DOBYPASS ClK TEST TESTSCRAMB/ CONTROL RESET MODE MODEADD 1 0PH. Ea.DESCRIPTIONSelects 11.0592 MHz crystal echo output at ClKpin.Selects 16 X the data rate, output at ClK pin in OPSKmodes only.Selects normal operation. OPSK data is passedthrough scrambler.Selects Scrambler Bypass. OPSK data is routedaround scrambler in the transmit path. In Bell 202mode, additional phase equalization is added to themain channel filters when 04 is set to 1.Disables interrupt at INT pin.Enables INT output. An interrupt will be generated witha change in status of DR bits 01-04. The special toneand call progress detect interrupts are masked whenthe TX enable bit is set. Carrier detect is masked whenTX OTMF is activated. All interrupts will be disabled ifthe device is in power down mode.I07 0607,06 Transmit 0 0Pattern0 11 01 1Selects normal data transmission as controlledby the state of the TXO pin.Selects an alternating mark/space transmit pattern formodem testing.Selects a constant mark transmit pattern.Selects a constant space transmit pattern.* 04 should always be set to 1 when receiving 1200 bitls data and to 0 when transmitting 1200 bitls data in202 mode.3-159

SSI73K302LBell 212A, 103, 202Single-Chip ModemDETECT REGISTERDR010BIT NO.DONAME CONDITION DESCRIPTIONLong Loop o Indicates normal received signal.0102Call Progress 0 No call progress tone detected.Detect I--------+--In-d-ic-a-te-s-p-r-es-e-n-c-e-o-f -c-al-I-p-ro-g-re-s-s-to-n-e-s-.-T-h-e-c-a-II~Special ToneDetectoprogress detection circuitry is activated by energy inthe normal 350 to 620 Hz call progress band.No special tone detected as programmed byCRO bit DO and Tone Register bit DO.(1) 2225 Hz answer tone if DO of TR=O and the deviceis in Bell 103 or 212A originate mod/3.(2) Soft carrier turn-off tone if DO of TR=O and thedevice is in Bell 202 answer mode.(3) an FSK mark in the mode the device is set toreceive if DO of TR is set to 1 .03 Carrier Detect l---~---L-~~~~~~~~~~~~~~~---IIndicated carrier has been detected in the receivedchannel.040506,07UnscrambledMarkI--------+--(D-P-S-K-o-nl-y)-In-d-ic-a-te-s-d-e-te-c-tio-n-o-f-u-n-sc-r-am--bl-ed--~DetectReceiveDatamarks in the received data. A valid indication requiresthat unscrambled marks be received for> 165.5 ±6.5 ms.Continuously outputs the received data stream.This data is the same as that output on the RXD pin, butit is not disabled when RXD is tri-stated.3-160

SSI73K302LBell 212A, 103,202Single-Chip ModemTONE REGISTER07 06 05RXO TRANSMIT TRANSMITTR OUTPUT SOFT ANSWERCARRIER011 CONTR. TURN-OFF TONETONE04 03TRANSMITOTMFOTMF302 D1 DOOTMF 21 OTMF 11 OTMF 01202 OVER- SPECIALFOX SPEED TONE SELBIT NO. NAME CONDITION05 04 DODO OTMF 01 0 1 XSpecial Tone0 0 0Detect/SelectX 0 11 0 01 0 104 0101 OTMF 11 0 0Overspeed0 102 OTMF2/202T 0FOX 103 02 01 DO03,02, OTMF 3, 0 0 0 0-01,00 2,1,0 1 1 1 13-161DESCRIPTIONDO interacts with bits 06, D4, and CRO as shown.Transmit OTMF tones.2225 Hz answer tone will be detected in 02 of DR iforiginate mode is selected in CRO.900 Hz SCT tone will be detected in 02 of DR if Bell 202answer mode is selected in CRO.Mark of an FSK mode selected in CRO is to be detectedin 02 of DR.2225 Hz answer tone will be generated when inanswer mode and transmit enable is selected in CRO.2100 Hz answer tone will be generated when inanswer mode and transmit enable is selected in CRO.01 interacts with 04 as shown.Asynchronous DPSK 1200 bitls _+1.0% -2.5%.Asynchronous OPSK 1200 bitls +2.3% -2.5%.Enables 202 half-duplex operation if 04=0Enables 202 full-duplex operation if 04=0Programs 1 of 16 DTMF tone pairs that will betransmitted when TX OTM F and TX enable bit (CRO, bitD1) are set. Tone encoding is shown below:KEYBOARD DTMF CODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGH1 0 0 0 1 697 12092 0 0 1 0 697 13363 0 0 1 1 697 14774 0 1 0 0 770 12095_..0 1 0 1 770 13366 0 1 1 0 770 14777 0 1 1 1 852 12098 1 0 0 0 852 13369 1 0 0 1 852 14770 1 0 1 0 941 1336I

SSI73K302LBell 212A, 103, 202Single-Chip ModemTONE REGISTER (Continued)07 06TRANSMITRXOSOFTTR OUTPUT CARRIER011 CONTR. TURN-OFFTONE05TRANSMITANSWERTONE04 03 02 01 DOTRANSMIT DTMF 21 DTMF 11 OTMF 01DTMF DTMF3 202T OVER- SPECIALFOX SPEED TONE SELBIT NO.03,02,01,00(cont.)NAME04 TransmitDTMF05 TransmitAnswer Tone06 TransmitSCT Tone07 RXD OutputControl, " Notes for Tone Register use:CONDITION01010101DESCRIPTIONKEYBOARD DTMF CODE TONESEQUIVALENT 03 02 01 DO LOW HIGH* 1 0 1 1 941 1209# 1 1 0 Q 941 1477A 1 1 0 1 697 1633B 1 1 1 0 770 1633-----_.-C 1 1 1 1 852 16330 0 0 0 0 941 1633Disable DTMF.Activate OTMF. The selected DTMF tones aretransmitted continuously when this bit is high.TX DTMF overrides all other transmit functions.Disables answer tone generator.Enables answer tone generator. A 2225 Hzanswer tone will be transmitted continuously when thetransmit enable bit is set. To transmit answer tone, thedevice must be in answer mode.Disables SCT tone generator.Transmit SCT tone in Bell 202 mode.Enables RXD pin. Receive data will be output onRXD.Disables RXD pin. The RXD pin reverts to a highimpedance with internal weak pul_~~up resistor.1. To detect SCT tone, 202 answer mode must be selected. To transmit SCT tone, 202 originate mode mustbe selected.2. For answer tone detection, 103 or 212 originate mode must be active. To transmit answer tone, the73K302 must be in 103 or 212 answer mode.3. After completion of DTMF dialing, bit 02 should be reset unless 202 full-duplex mode is selected.3-162

__ 0-SSI73K302LBell 212A, 103,202Single-Chip Modem10 REGISTER101100710061005100410BIT NO.NAMECONDITIONDESCRIPTION07 06 05 04Indicates Device:07,06DeviceIdentificationSignatureIELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETERVOO Supply VoltageRATINGStorage Temperature -65 to 150°C---_.-Soldering Temperature (10 sec.) 260°CApplied Voltage14V--_ ..-0.3 to VDD+0.3VNote: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITSVDO Supply voltage 4.5 5 5.5 VTA, Operating Free-Air Temp. -40 +85 °CClock Variation (11.0592 MHz) Crystal or external clock -0.01 +0.01 %External Components (Refer to Application section for placement.)VREF Bypass Capacitor (External to GNO) 0.1 J.1F- --~-Bias setting resistor (Placed between VDD and ISET pins) 1.8 2 2.2 MQ--ISET Bypass Capacitor (ISET pin to GNO) 0.1 J.1FVDO Bypass Capacitor 1 (External to GNO) 0.1-------J.1FVDO Bypass Capacitor 2 (External to GND) 22,---J.1FXTL 1 Load Capacitor Depends on crystal characteristics; 40 pFXTL2 Load Capacitor from pin to GND 203-163--

SSI73K302LBell 212A, 103, 202Single-Chip ModemDC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN100, Supply Current ISET Resistor = 2 MQIDDA, ActiveClK = 11.0592 MHzIDD1, Power-down ClK = 11 .0592 MHzIDD2, Power-down ClK = 19.200 kHzDigital InputsVIH, Input High VoltageReset, XTl1 , XTl2 3.0All other inputs 2.0Vll, Input low Voltage 0IIH, Input High Current VI = VIH MaxIll, Input low Current VI = Vil Min -200Reset Pull-down Current Reset = VDD 1Input CapacitanceAll Digital Input PinsDigital OutputsVOH, Output High Voltage 10H MIN = -0.4 rnA 2.4VOL, Output low Voltage 10 MAX = 1.6 mAVOL, ClK Output10 = 3.6 mARXD Tri-State Pull-up Curro RXD = GND -1CMAX, ClK Output Maximum Capacitive loadCapacitanceInputsCapacitance, all Digital Input pinsXTl1, 2 load Capacitors Depends on crystal 15ClKMaximum Capacitive loadNOM MAX UNITS8 12 rnA4 mA3 mAVDD VVDD V0.8 V100 ~~50 ~10 pFVDD V0.4 V0.6 V-50 ~15 pF10 pF60 pF15 pF3-164

--.-~----SSI73K302LBell 212A, 103,202Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING(TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.)PARAMETERS CONDITIONS MIN NOM MAX UNITSDPSK ModulatorCarrier Suppression Measured at TXA 45 -T~- --TdB~-'-.~Output Amplitude TX scrambled marks -11 -10 -9 dBmO---FSK ModulatorOutput Freq. Error elK = 11.0592 MHz -0.35 +0.35 %--Transmit level Transmit Do~ Pattern -11 -10 -9 dBmOSoft Carrier Turnoff Tone -11.9 -10.9----9.9 dBmOHarmonic Distortion THO in the alternate band -60 -50 dBin 700-2900 Hz band DPSK or FSK---~----Output Bias Distortion Transmit Dotting Pattern ±3 %In AlB@ RXDTotal Output Jitter Random Input in ALB @ RXD -10 +10 %DTMF GeneratorMust not be in 202 modeFreq. Accuracy -0.25 +0.25%Output Amplitude, Low group DPSK mode -10 -9 -8 dBmO--Output Amplitude, High group DPSK mode -8 -7 -6 dBmOTwist High-Band to low-Band 1.0 2.0 3.0 dBLong Loop Detect With Sinusoid -38 -28 dBmO---Dynamic Range Refer to Performance Curves 45 dB-------Note: Parameters expressed in dBmO refer to the following definition:5V Version:o dB loss in the Transmit path to the line.2 dB gain in the Receive path from the line.Refer to the Basic Box Modem diagram in the Applications section for the DAA design.--I3-165

SSI73K302LBell 212A, 103, 202Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCall Prog ress DetectorDetect LevelReject LevelDelay TimeHold TimeHysteresisCarrier DetectThresholdDelay TimeBell 103Bell 212ABell 202 Forward ChannelBell 202 Back ChannelHold TimeBell 103Bell 212ABell 202 Forward ChannelBell 202 Back ChannelHysteresisSpecial Tone DetectorsDetect LevelDelay TimeAnswer toneCONDITIONS-3 dB points in 285 and 675 HzTest signal is a 460 Hz sinusoid-70 dBmO to -30 dBmO STEP-30 dBmO to -70 dBmO STEPDPSK or FSK receive dataSee definitions forTR bit DO mode900 Hz SCT tone Preceded by valid carrier*202 Main Channel Mark202 Back Channel Mark1270 or 2225 Hz marks* If SCT duration >4ms, it is guaranteed to detect.MIN NOM MAX UNITS-38 dBmO-45 dBmO20 40 ms20 40 ms2 dB-49 -42 dBmO8 20 ms15 32 ms6 12 ms25 40 ms6 20 ms10 24 ms3 8 ms10 25 ms2 dB-49 -42 dBmO10 25 ms4 10 ms10 25 ms20 65 ms10 25 ms3-166

----.~.---~-.------.--SSI73K302LBell 212A, 103,202Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMINNOM MAX UNITSSpecial Tone Detectors (Continued)Hold TimeAnswer tone900 Hz SCT tone202 Main Channel Mark202 Back Channel Mark1270 or 2225 Hz marksHysteresisDetect Freq. RangeOutput Smoothing FilterOutput loadOut of Band EnergyOutput ImpedanceClock NoiseCarrierVCOCapture RangeCapture TimeDPSK Recovered ClockCapture RangeData Delay TimeTone GeneratorTone AccuracyTone LevelAny Special ToneTXA pin; FSK SingleTone out for THO = -50 dBin 0.3 to 3.4 kHzFrequency> 12 kHz in all modesSee Transmit Energy SpectrumTXA pinTXA pin; 76.8 kHz or 122.88 kHzin 202 main channelOriginate or Answer-10Hz to +10 Hz CarrierFrequency Change% of data rate(center at 1200 Hz)Analog data in at RXA pin toreceive data valid at RXD pinDTMF or FSK tonesFor DTMF, must not be in 202 mode4131052-3-~-~-~----.-----15 ms10 ms10 ms25 ms15 msdB+3 %10 kQ50 pF-60 dBmO20 50 Q------0.1 0.4 mVrms-10 +10 Hz~~---.-~~-40 100 ms-------------r--~-~--~~-625 +625 ppm30 50 ms-5 +5 Hz-1 +1 dBI3-167

SSI73K302LBell 212A, 103, 202Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSTiming (Refer to Timing Diagrams)TALTLATLCTCLTRDTLLTRDFTRWTWWTDWTWDTCKDTCKWTDCKTACTCATWHCONDITIONSCS/Addr. setup before ALE LowCS/Addr. hold after ALE LowALE Low to RDIWR LowRD/WR Control to ALE HighData out from RD LowALE widthData float after RD HighRDwidthWRwidthData setup before WR HighData hold after WR HighData out after EXCLK LowWR after EXCLK LowData setup before EXCLK LowAddress setup before control*Address hold after control*Data Hold after EXCLK* Control for setup is the falling edge of RD or WR.Control for hold is the falling edge of RD or the rising edge of WR.MIN NOM MAX UNITS25 ns20---ns30-----ns-5--ns0 140-- _._---ns30 ns0 5 ns200 25000 ns140 25000 ns40 ns- 1--10' ns200 ns150 ns150--ns50 ns----50 ns20--- ----3-168

SSI73K302LBell 212A, 103,202Single-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE ~ ________TLCTLCADO-AD7I T~DTAL ~-{ ADDRESS >l-------K READ DATA>l-------K ADDRESS >l-------K WRITE DATA}---Cs~~-__ -~~______-~~ __ ~i-____ __IREAD TIMING DIAGRAM (SERIAL VERSION)EXCLKRDI~--~----------~AO-A2DATA --+WRITE TIMING DIAGRAM (SERIAL VERSION)EXCLKHTWW-----+--------------------------------------~--,iAO-A2 ----+------------------- -----------1+.TCKW I ~I ~ TCADATA3-169

SSI73K302LBell 212A, 103, 202Single-Chip ModemAPPLICATIONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK-Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a OAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes.Two typical OAA arrangementsare shown: one for a split ±5 or ±12volt design and one for a single 5V design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one for a para"el multiplexed address/data interface, and one for a serial interface. Thepara"el version is intended for use with 8039/48 or8031/51 microcontro"ers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontro"ers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The para"el versions may alsobe used in the serial mode, as explained in the datasheet pin description.In most applications the contro"erwill monitorthe serialdata for commands from the OTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent overthe sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.C9.1 nF+ C822nFC1390pFCACB ' ./1, .......... ---.JCCCD I-I>'~':"""""CFwriALE~SSIK-SERIESLOWPOWERFAMILYRXA I-.--H-----~kCMBA f'::>-I~+--I---+--lf---t--!BBDADODBUS.U6MC145406RESETfVRIMOVV250L20R910K.5~ 22KFIGURE 1: Basic Box Modem with Dual-Supply Hybrid3-170

SSI73K302LBell 212A, 103,202Single-Chip ModemDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing at the transformer, making the transmitsignal common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This circuit(Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a single 5V supply. BecauseDTMF tones utilize a higher amplitude than data, thesesignals will clip if a single-ended drive approach isused. The bridged driver uses an extra op-amp (U1 A)to invert the signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-amp then supplies half the drive signalto the transformer. The receive amplifier (U1C) picksoff its signal at the junction of the impedance matchingresistor and the transformer. Because the bottom legof the transformer is being driven in one direction byU1A and the resistor is driven in the opposite directionat the same time by U 1 B, the junction of the transformerand resistor remains relatively constant and the receivesignal is unaffected.DESIGN CONSIDERATIONSSilicon Systems' 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.ICI390pFR437.4K 1%C30.1nf'

SSI73K302LBell 212A, 103, 202Single-Chip ModemUnlike digital logic circuitry, modem designs mustproperly contend with precise frequency tolerancesand very low level analog signals, to ensure acceptableperformance. Using good analog circuit design practiceswill generally result in a sound design. Followingare additional recommendations which should betaken into consideration when starting new designs.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±O.01% accuracy.In orderfor a parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LAYOUT CONSIDERATIONSGood analog/digital design rules must be used tocontrol system noise in orderto.obtain highest performancein modem designs. The more digital circuitrypresent on the PC board, the more this attention tonoise control is needed. The modem should be treatedas a high impedance analog device. A 22 mF electrolyticcapacitor in parallel with a 0.1 mF ceramic capacitorbetween VDD and GND is recommended. Liberaluse of ground planes and larger traces on power andground are also highly favored. High speed digitalcircuits tend to generate a significant amount of EMI(Electro-Magnetic Interference) which must be minimizedin order to meet regulatory agency limitations.To accomplish this, high speed digital devices shouldbe locally bypassed, and the telephone line interfaceand K-Series device should be located close to eachother near the area of the board where the phone lineconnection is accessed. To avoid problems, powersupply and ground traces should be routed separatelyto the analog and digital functions on the board, anddigital signals should not be routed near low level orhigh impedance analog traces. The analog and digitalgrounds should only connect at one point near theK-Series device ground pin to avoid ground loops. TheK-Series modem IC's should have both high frequencyand low frequency bypassing as close to thepackage as possible.MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line Simulator, operatingunder computer control. All tests were run fullduplex,using a Concord Data Systems 224 as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and all signal-to-noise (SIN) ratios reflecttotal power measurements simifar to the CCITT V.56measurement specification. The individual tests aredefined as follows.SER vs. SINThis test measures the abifity of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a DPSK modem will exhibitbetter BER-performance test curves receiving in thelow band than in the high band.SER vs. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamicrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels . The width of the "bowl" ofthese curves, taken at the BER pOint, is the measure ofdynamic range.3-172

SSI73K302LBell 212A, 103,202Single-Chip ModemSSI73K302LBERvsS/NSSI73K302LBER vs SIN10- 3W~a:a:0 10-4a:a:wt::III10-510-6\ \~ \\'\~ \ \\\ 1\I\~ \ \\~ 1\ i~ ~ 3002W/O EO.]\\1\\ \1 \FLAT W/EO.1\\' I :\~ '\\[FLATWiO}EO.~ ~ 11 \\~ Kc~~rol\ \.1\ \ \~ RECEIVE LEVEL I \~ ~f2WiEOI ~ ~.-30 dBmBELL 202 MODE I\ \ \\ \4 10 12 14 1610-3W~a:a:0 10-4a:a:wt::III10- 5I HIGH BAND RECEIVE}=:-30 dBm\ I DPS~2~6~1~~iION\\\\\~ ~I--C2~'¥ H'\ ~~'c1;3002-,--,r"--'-; FLAT-~\'\\\\\\ \\ \, \ \,\ \\ \ \10 12 14ISIGNAL TO NOISE (dB)SIGNAL TO NOISE (dB)SSI73K302LBER vs RECEIVE LEVEL.1 HIGH BAND RECEIVE ~DPSK OPERATIONI C2 LINESSI73K302LBER vs PHASE JITTERI HIGH BAND RECEIVE I-DPSK OPERATION10- 310-4\SIN -10.8 dB1I10-5- j 3002 11 .5 dB SIN- ./Il/'",rr./'~b:::::: ::::: .--.--1C210.8 dB SIN ~ I--I--r-r-SIN = 15dB"-10 -10 -20 -30 -40 -50RECEIVE LEVEL (dBm)12 16 20 24PHASE JITTER (DEG.)3-173

SSI73K302LBell 212A, 103, 202Single-Chip ModemSSI73K302LBER vs CARRIER OFFSETI HIGH BAND RECEIVE ~I DPSKOPERATION10- 3 12I 300211.8dBS/N II C211.3dBSAII I\\I-- V:..- :..-~ -----~--~r--4-8 -12CARRIER OFFSET (HZ)3-174

SSI73K302LBell 212A, 103,202Single-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.GNDA1RXAVREFRESETISETRXClKRXDTXDEXClKClKXTl1XTL2ADOAD1AD2AD3AD4AD5ADSAD7GNDRXAVREFRESETISETRXClKRXDTXDcsEXClKTXClK4 3 2 12827262524PLCC PINOUTS 238 ARE THE SAME AS 22THE 28-PIN DIP 21ITXCLKALEINT20INTWRTXA19TXARDVDD12 13 14 15 16 17 18400-MII22-Pin DIPSOO-Mil28-Pln DIP28-PinPLCCORDERING INFORMATIONPART DESCRIPTIONORDER NO.PKG.MARKSSI 73K302L with Parallel Bus Interface28-Pin Dip28-Lead PLCCSSI 73K302L with Serial Interface22-pin Dip73K302L-IP73K302L-IH73K302SL-IP73K302L-IP73K302L-IH73K302SL-IPPreliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations andare not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69140194 - rev.3-175Protected by the following Patents (4,691,172) (4,777,453)©1989 Silicon Systems, Inc.

Notes:3-176

SSI73K321LCCITT V.23, V.21Single-Chip ModemDESCRIPTIONThe SSI 73K321 L is a highly integrated single-chipmodem IC which provides the functions needed toconstruct a CCITT V.23 and V.21 compatible modem,capable of 0-300 bitls full-duplex or 0-1200 bitls ha.lfduplexoperation over dial-up telephone lines. The73K321 L provides 1200 bit/s operation in V.23 modeand300biVsinV.21 mode. TheSSI73K321Laisocanboth detect and generate the 2100 Hz answer toneneeded for call initiation. The SSI 73K321 L integratesanalog, digital, and switched-capacitor array functionson a single substrate,offering excellent performanceand a high level of functional integration in a single 28-or 22-pin DIP configuration. The SSI 73K321 L operatesfrom a single +5V supply with very low powerconsumption.The SSI 73K321 L includes the FSK modulator/demodulatorfunctions, call progress and handshaketone monitortest modes, and a tone generator capableof producing DTMF, answer, calling tones. TheSSI 73K321 L is designed to appear to the systemsdesigner as a microprocessor peripheral, and will easilyinterface with popular one-chip microprocessors(80C51 typical) for control of modem functions throughits 8-bit multiplexed address/data bus orvia an optionalserial control bus. An ALE control line simplifies addressdemultiplexing. Data communications occursthrough a separate serial port only.(Continued)•••January 1994FEATURES• One-Chip CCITT V.23 and V.21 standardcompatible modem data pump• Full-duplex operation at 0-300 bitls (V.21) or0-1200 bitls (V.23) forward channel with orwithout 0-75 bitsls back channelFull Duplex 0-1200 bitls (V.23) in 4-wire modePin and software compatible with otherSSI K-Series 1-chip modemsInterfaces directly with standard microprocessors(8048, 80C51 typical)• Serial or parallel microprocessor bus forcontrol• Serial port for data transfer• Call progress, carrier, precise answer tone(2100 Hz), calling tone (1300 Hz) and FSK markdetectors• DTMF generator• Test modes available: ALB, DL, RDL, Mark,Space, Alternating bit patterns• Precise automatic gain control allows 45 dBdynamic range• Space efficient 28-pin PLCC package available• CMOS technology for low power consumptionusing 30 mW @ 5V from a single power supplyIBLOCK DIAGRAMPIN DIAGRAMeLKXTL1RD~WR~ALE~cs~RESET~INT 0------4TXDO--------I~RXDD---------!SMARTDIALING&DETECTFUNCTIONSTXARXAXTL2ADOAD1AD2AD3AD4AD5ADSAD7ALEWRRD0194 - rev.3-177

SSI73K321LCCITT V.23, V.21Single-Chip ModemDESCRIPTION (Continued)The SSI 73K321 L is ideal for either free standing orintegral system modem applications where multi-standarddata communications over the 2-wire switchedtelephone network is desired. Typical uses includevideotex terminals, low-cost integral modems andbuilt-in diagnostics for office automation or industrialcontrol systems. The 73K321 L's high functionality, lowpower consumption and efficient packaging simplifydesign requirements and increase system reliability inthese applications. A complete modem requires onlythe addition of the phone line interface, a controlmicroprocessor, and RS-232 level converter for atypical system. The SSI 73K321 L is part of SiliconSystems K-Series family of pin and function compatiblesingle-chip modem products. These devices allowsystems to be configured for higher speeds and Bell orCCITT operation with only a single component change.OPERATIONFSK MODULATOR/DEMODULATORThe FSK modulator produces a frequency modulatedanalog output signal using two discrete frequencies torepresent the binary data. V.21 mode uses 980 and1180 Hz (0 riginate, mark and space) or 1650 and1850 Hz (answer, mark and space). V.23 mode uses1300 and 2100 Hz for the main channel and 390 and450 Hzforthebackchannel. The modulation rate of theback channel is up to 75 baud. Demodulation involvesdetecting the received frequencies and decoding theminto the appropriate binary value.PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and provide compromise delay equalizationand rejection of out-of-band signals in thereceive channel. Amplitude and phase equalizationare necessary to compensate for distortion of thetransmission line and to reduce intersymbol interferencein the bandlimited receive Signal.AGCThe automatic gain control maintains a signal level atthe input to the demodulators which is constant towithin 1 dB. It corrects quickly for increases in signalwhich would cause clipping and provides a totalreceiver dynamic range of >45 dB.PARALLEL BUS INTERFACEFour 8-bit registers are provided for control, optionselect and status monitoring. These registers are addressedwith the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as four consecutive memory locations.Two control registers and the tone register areread/write memory. The detect register is read only andcannot be modified except by modem response tomonitored parameters. The parallel bus interface is notavailable with the 22-pin package.SERIAL COMMAND INTERFACEThe Serial Command mode allows access to the SSI73K321 L control ~nd status registers via a serialcommand port. In this mode the AO , A 1 and A2 linesprovide register addresses for data passed through thedata pin under control of the RD and WR lines. A readoperation is initiated when the RD line is taken low. Thefirst bit is available after RD is brought low and the nextseven cycles of EXCLK will then transfer out seven bitsof the selected address location LSB first. A write takesplace by shifting in eight bits of data LSB first for eightconsecutive cycles of EXCLK. WR is then pulsed lowand data transferred into the selected register occurson the rising edge of WR.SPECIAL DETECT CIRCUITRYThe special detect Circuitry monitors the receivedanalog Signal to determine status or presence of carrier,answer tone and weak received signal (long loopcondition), special tones such as FSK marking and the1300 Hz calling tone are also detected. A highly frequencyselective call progress detector provides adequatediscrimination to accurately detect Europeancall progress Signals.DTMF GENERATORThe DTMF generator will output one of 16 standardtone-pairs determined by a 4-bit binary value and TXDTMF mode bit previously loaded illto the tone register.Dialing is initiated when the DTMF mode is selectedusing the tone register and the transmit enable(CRO bit D1) is changed from 0 to 1.3-178

SSI73K321LCCITT V.23, V.21Single-Chip ModemPIN DESCRIPTIONPOWERNAME 28-PIN 22-PIN TYPEGND 28 1 IVDD 15 11 IVREF 26 21 0ISET 24 19 IPARALLEL MICROPROCESSOR INTERFACEDESCRIPTIONSystem Ground.Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 IJ-Fcapacitors to GND.An internally generated reference voltage. Bypass with0.1 IJ-F capacitor to GND.Chip current reference. Sets bias current for op-amps. Thechip current is set by connecting this pin to VDD through a2 MQ resistor. ISET should be bypassed to GND with a0.1 IJ-F capacitor.IALE 12 - IADO-AD7 4-11 - I/OCS 20 - IClK 1 2 0INT 17 13 0RD 14 - IRESET 25 20 IAddress latch enable. The falling edge of ALE latches theaddress on ADO-AD2 and the chip_ select on CS.Address/data bus. These bidirectional tri-state multiplexedlines carry information to and from the internalregisters.Chip select. A low during the falling edge of ALE on this pinallows a read cycle or a write cycle to occur. ADO-AD7 willnot be driven and no registers will be written if CS (latched)is not active. The state of CS is latched on the falling edgeof ALE.Output clock. This pin is the output of the crystal oscillatorfrequency only in the SSI 73K321 .Interrupt. This open drain output signal is used to inform theprocessor that a detect flag has occurred. The processormust then read the detect register to determine whichdetect triggered the interrupt. INT will stay low until theprocessor reads the detect register or does a full reset.Read. A low requests a read of the SSI 73K321 l internalregisters. Data cannot be output unless both RD and thelatched CS are active or low.Reset. An active high signal high on this pin will put the chipinto an inactive state. All control register bits (CRO, CR1,Tone) will be reset. The output of the ClK pin will be set tothe crystal frequency. An internal pull down resistor permitspower on reset using a capacitor to VDD.3-179

SSI73K321LCCITT V.23, V.21Single-Chip ModemPIN DESCRIPTION (Continued)PARALLEL MICROPROCESSOR INTERFACE (Continued)NAME 28·PIN 22·PIN TYPE DESCRIPTIONWR 13 - I Write. A low on this informs the SSI 73K321 L that data isavailable on ADO-AD7 for writing into an internal register.Data is latched on the rising edge of WR. No data is writtenunless both WR and the latched CS are low.SERIAL MICROPROCESSOR INTERFACEAO-A2 - 5-7 I Register Address Selection. These lines carry registeraddresses and should be valid during any read or writeoperation.DATA - 8 I/O Serial Control Data. Data for a read/write operation isclocked in or out on the falling edge of the EXCLK pin. Thedirection of data flow is controlled by the RD pin. RD lowoutputs data. RD high inputs data.RD - 10 I Read. A low on this input informs the SSI 73K321 L thatdata or status information is being read by the processor.The falling edge of the RD signal will initiate a read from theaddressed register. The RD signal must continue for eightfalling edges of EXCLK in order to read all eight bits of thereferenced register. Read data is provided LSB first. Datawill not be output unless the RD signal is active.WR - 9 I Write. A low on this input informs the SSI73K321 L that dataor status information has been shifted in through the DATApin and is available for writing to an internal register. Thenormal procedure for a write is to shift in data LSB first onthe DATA pin for eight consecutive falling edges of EXCLKand then to pulse WR low. Data is written on the rising edgeofWR.Note:In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with thepins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.The Serial Control mode is provided in the 28-pin version by tying ALE high and CS low. In thisconfiguration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2, respectively.3-180

SSI73K321LCCITT V.23, V.21Single-Chip ModemDTE USER INTERFACENAME 28·PIN 22·PIN TYPEEXCLK 19 15 IRXCLK 23 18 0RXD 22 17 0TXCLK 18 14 0TXD 21 16 IDESCRIPTIONExternal Clock. Used for serial control interface to clockcontrol data in or out of the 73K321 L.Receive Clock. Aclockwhich is 16x1200,or16x 75 in V.23mode, or 16 x 300 baud data rate is output in V.21.Received Digital Data Output. Serial receive data is availableon this pin. The data is always valid on the rising edgeof RXCLK when in Synchronous mode. RXD will outputconstant marks if no carrier is detected.Transmit Clock. TXCLK is always active. In V.23 mode theoutput is either a 16 x 1200 baud clock or 16 x 75 baud, inV.21 mode the clock is 16 x 300 baud.Transmit Digital Data Input. Serial data for transmission isinput on this pin. In Asynchronous modes (1200 or 300baud) no clocking is necessary.IANALOG INTERFACE AND OSCILLATORRXA 27 22 ITXA 16 12 0XTL1 2 3 IXTL2 3 4 IReceived modulated analog signal input from the phoneline.Transmit analog output to the phone line.These pins are for the internal crystal oscillator requiringa 11.0592 MHz Parallel mode crystal and two load capacitorsto Ground. XTL2 can also be driven from an externalclock.3-181

SSI73K321LCCITT V.23, V.21Single-Chip ModemREGISTER DESCRIPTIONSFour 8-bH internal registers are accessible for controland status monitoring. The registers are accessed inread or wrHe operations by addressing the AO and A 1address lines in Serial mode, orthe ADO and AD1 linesin Parallel mode. The ADO and AD1 lines are latched byALE. Register CRO controls the method by which datais transferred over the phone line. CR1 controls theinterface between the microprocessor and theSSI73K321L internal state. DR is a detect registerwhich provides an indication of Monitored modemstatus conditions. TR, the tone control register, controlsthe DTM F generator, answer and guard tones andRXD output gate used in the modem initial connectsequence. All registers are read/write except for DRwhich is read only. Register control and status bits areidentified below:REGISTER BIT SUMMARYCROCQIITROLREGISTER CR1 0011DETECTREGISTER DR 010CLK TEST TESTCQIITROLRESET MODE MODE1 0CARRIER SPECIAL CALL LONGDETECT TQIIE PROGRESS LOOPTQIIECQIITROL TR 011REGISTERDTMF3DTMF2!V.23 FOXDTMF1CQIITROLREGISTER CR2 1002CQIITROLREGISTER CR3 1013IDREGISTER ID 110NOTE:When a register containing reservedcontrol bits is written into, the reserved bitsmust be programmed as O's.3-182

SSI73K321LCCITT V.23, V.21Single-Chip ModemREGISTER ADDRESS TABLE0.V.23 FSK1.V.21 FSKOOOO.PWR DOWN ________---'lloo=FSK0ool.TRANSMIT DTMF, CALL PROGRESS DETECTIONO=DISABLE IN V.21 MODE:TXA OUTPUT O.ANSWERl=ENABLE 1.0RIGINATETXA OUTPUT IN V.23 MODEO.RECEIVE @ 1200 BITIS,TRANSM IT @ 75 BITISl=RECEIVE @ 75 BITIS,TRANSMIT @ 1200 BITISIO.HALF DUPLEX V.231 .ALLOWS V.23 FULLDUPLEX OPERATIONO.ANSWER TONE FREO .• 2225 HzFSK MARK WILL BE INDICATEDBY SPECIAL TONE BIT IN DR1.ANSWER TONE FREO .• 2100 HzEITHER 2100 Hz (IN ORIG.) OR1300 Hz (IN ANS.) WILL BEINDICATED BY SPECIAL TONEBIT IN DROOXX.73K212L. 322L. 321L01XX.73K221L.302L10XX.73K222Lll00.73K224L1110.73K324L1101.73K312L3-183

SSI73K321LCCITT V.23, V.21Single-Chip ModemCONTROL REGISTER 0CRO00005TRANSMITMOOE3BIT NO. NAME CONDITIONDOAnswer/ oOriginate01TransmitEnableDESCRIPTIONSelects Answer mode in V.21 (transmit in high band,receive in low band) or in V.23 mode, receive at1200 biVs and transmit at 75 bit/s.Selects Originate mode in V.21 (transmit in low band,receive in high band) or in V.23 mode, receive at 75 biVsand transmit at 1200 bit/s. If in V.23 and 02 of TR=1,selects V .23 full duplex operation in 4-wire configuration.Note: This bit works with TR bit DO to program specialtones detected in Tone Register. See detect and toneregisters.05,04,03,0202TransmitModeects Power Down mode. All functions disabled exceptital interface.0607FSK CCITT V.23 mode.FSK CCITT V.21 mode.3-184

--.-----~.--.--SSI73K321LcelTT V.23, V.21Single-Chip ModemCONTROL REGISTER 107 06 05TRANSMIT TRANSMIT ENABLECR1 PATTERN PATTERN DETECT001 1 0 INTER.BIT NO. NAME CONDITION01, DO Test Mode 01 DO0 00 11 01 102 Reset 003 ClK Control Program as(Clock Control) 004 Add Ph. Eq. 005 Enable Detect 0Interrupt07, 06 07 06Transmit 0 0Pattern1110 11 01 104 03 02 01 DOADD ClK TEST TESTPH. Ea. CONTROL RESET MODE MODE1 0DESCRIPTIONSelects Normal Operating mode.Analog loopback mode. loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same center frequency as the transmitter. Tosquelch the TXA pin, transmit enable must be forced low.Selects remote digitalloopback. Received data is loopedback to transmit data internally, and RXO is forced to amark. Data on TXO is ignored.Selects local digitalloopback. Internally loops TXO backto RXO and continues to transmit.data from TXA pin.Selects normal operation.Resets modem to power down state. All control registerbits (CRO, CR1, Tone) are reset to zero. The output of theclock pin will be set to the crystal frequency.Not supported in the SSI 73K321.See the TXClK andRXClK pin descriptions for 16x t~e data rate clocks.Selects normal equalization.In V.23 mode, additional phase equalization is added tothe main channel filters when 04 is set to 1.Disables interrupt at INT pin. All interrupts arenormally disabled in Power Down modes.Enables INT output. An interrupt will be generated witha change in status of DR bits 01-03. The special tone andcall progress detect interrupts are masked when the TXenable bit is set. Carrier detect is masked when TX OTM Fis activated. All interrupts will be disabled if the device isin Power Down mode.Selects normal data transmission as controlled by thestate of the TXO pin.Selects an alternating mark/space transmit pattern formodem testing.Selects a constant mark transmit pattern.Selects a constant space transmit pattern.I3-185

SSI73K321LCCITT V.23, V.21Single-Chip ModemDETECT REGISTERD2D1DODR010SPECIALTONECALLPROG.LONGLOOPDOLong LoopD1Call ProgressDetectD2Special ToneDetect0(1 )(2)(3)2100 Hz answertorie if DO of TR=1 and the device isin V.21 Originate mode.1300 Hz calling tone if DO of TR=1 and the device isin V.21 or V.23 Answer mode.an FSK markforthe mode the device is setto receivein if DO of TR = O.D3Carrier DetectD5D6,D7ReceiveDataContinuously outputs the received data stream. Thisdata is the same as that output on the RXD pin, but it isnot disabled when RXD is tri-stated.Not used.3-186

~-SSI73K321Lcelll V.23, V.21Single-Chip ModemTONE REGISTER07 06 05RXO TRANSMIT TRANSMITTR OUTPUT CALLING ANSWER011 CONTR. TONE TONEBIT NO. NAME CONDITION00 OTMF 01 06 05 04 00Answer TonelX X 1 XSpecial Tonel X X a aOetectiSe lectX X a 1X 1 a aX 1 a 1D3 D2 D1 DOD3, D2, DTMF 3, a a a 0-01,00 2,1,0 1 1 1 104 0302 01 00TRANSMITOTMF 01OTMF OTMF3 OTMF2 OTMF 1 ANS. TONEISPECIALTONEI SELDESCRIPTION00 interacts with bits 06, OS, 04, and CRO as shown.Transmit OTMF tones.Mark of an FSK mode selected in CRO is to be detectedin D2 of DR.--~---2100 Hz answer tone will be detected in D2 of DR if V.21Originate mode is selected in CRO.1300 Hz calling tone will be detected in D2 of DR if V.21or V.23 Answer mode is selected in CRO.Transmit 2225 Hz answer tone in Answer mode.Transmit 2100 Hz answer tone in Answer mode.Programs 1 of 16 DTMF tone pairs that will betransmitted when TX DTMF and TX enable bit (CRO, bitD1) is set. Tone encoding is shown below:KEYBOARD DTMF CODE TONESEQUIVALENT 03 02 01 DO LOW HIGH----t-------1 0 a a 1 697 1209--1---- ---2 a a 1 a 697 1336-_.-e----3 a a 1 1 697 1477--~ ~-.- ----~i----4 a 1 a a 770 1209--r-- -5 a 1 0 1 770 1336--r-- -- --"-- --6 a 1 1 a 770 1477--~1-----7 a 1 1 1 852 1209-----1------- -8 1 0 0 a 852 1336--r------ ----9 1 a a 1 852 1477---1------a 1 a 1 a 941 1336---I3-187

SSI73K321LCCITT V.23, V.21Single-Chip ModemTONE REGISTER (Continued)BIT NO.D3, D2,D1, DO(Cont.)D4NAMETransmitDTMF05 TransmitAnswer Tone06 TransmitCalling ToneCONDITION010101DESCRIPTIONKEYBOARD DTMFCODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGH--* 1 0 1 1-941 1209# 1 1 0 0 941 1477A 1 1 0 1 697 1633B 1 1 1 0---770 1633C 1 1 1 1 852 1633D 0 0 0 0--941 1633Disabled DTMF.Activates DTMF. The selected DTMF tones are transmittedcontinuously when this bit is high. TX DTMFoverrides all other transmit functions.Disables answer tone generator.Enables answer tone generator. A 21 00 Hz answer tonewill be transmitted continuously when the transmit enablebit is set. The device must be in-_Answer mode...-Disables calling tone generator.Transmit calling tone in either mode.07 RXD OutputControl01Enables RXD pin. Receive data will be output on RXD.Disables RXD pin. The RXD pin reverts to a high impedancewith internal weak pull-up resistor.10 REGISTER0706D5D4ID110IDIDIDIDBIT NO.NAMECONDITIONDESCRIPTIOND7 D6 D5 04Indicates Device:07, 06, 05 Device04 IdentificationSignature3-188

-~SSI73K321LCCITT V.23, V.21Single-Chip ModemELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETERVDD Supply VoltageStorage TemperatureSoldering Temperature (10 sec.)Applied VoltageRATING14V-65 to 150°C-260°C-0.3 to VDD+0.3VNote: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITSVDD Supply voltage 4.5 5 5.5 V-~TA, Operating Free-Air -40 +85 °CTemperature- -----Clock Variation (11.0592 MHz) Crystal or -0.01 +0.01 %external clock-- -External Components (Refer to Application section for placement.)VREF Bypass Capacitor (External to GND) 0.1 JlFBias setting resistor (Placed between VDD 1.8 2 2.2 MOand ISET pins)ISET Bypass Capacitor (ISET pin to GND) 0.1 JlF-------VDD Bypass Capacitor 1 (External to GND) 0.1 JlFVDD Bypass Capacitor 2 (External to GND) 22 JlFXTL 1 Load Capacitor Depends on crystal characteristics; 40 pF~~----.1-----------XTL2 Load Capacitor from pin to GND 20I3-189

____ 0"SSI73K321LCCITT V.23, V.21Single-Chip ModemDC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN100, Supply Current ISET Resistor = 2 MQIDOA, ActiveCLK = 11 .0592 MHz1001, Power-down CLK = 11.0592 MHz1002, Power-down CLK = 19.200 kHzDigital InputsVIH, Input High VoltageReset, XTL 1, XTL2 3.0All other inputs 2.0VIL, Input Low Voltage 0IIH, Input High Current VI = VIH MaxilL, Input Low Current VI = VIL Min -200Reset Pull-down Current Reset = VOO 1Input CapacitanceAll Oigitallnput PinsDigital OutputsVOH, Output High Voltage 10H MIN = -0.4 rnA 2.4VOL, Output Low Voltage 10 MAX = 1.6 rnAVOL, CLK Output10 = 3.6 rnARXO Tri-State Pull-up Curr. RXO = GNO -1CMAX, CLK OutputMaximum Capacitive LoadNOM MAX UNITS8 12 rnA-------- -----------4 rnA3 rnAVOOVVOO-- .-_..-V--0.8 V-~----100- ~-----~50 ~10 pFVOOV0.4 V0.6 V-50 ~15 pF--3-190

---~-----SSI73K321LCCITT V.23, V.21Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING{TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.}PARAMETERS CONDITIONS MIN NOM MAX UNITSFSK Modulator_.. _--Output Freq. Error ClK = 11.0592 MHz -0.35 +0.35 %Transmit level Transmit Dotting Pattern -11 -10 -9 dBmO.- -Harmonic Distortion TH 0 in the alternate band FSK -60 -50 dBin 700-2900 Hz bandOutput Bias Distortion Transmit Dotting Pattern in ALB @ RXD ±3%Total Output Jitter Random Input in ALB @ RXD -10 +10%NOTE: Parameters expressed in dBmO refer to the following definition:o dB loss in the Transmit path to the line.2 dB gain in the Receive path from the line.Refer to the Basic Box Modem diagram in the Applications section for the DAA design.DTMF GeneratorFreq. Accuracy -0.25 +0.25 %- ---Output Amplitude low Band, CRO bit 02=1 -10 -9 -8 dBmOOutput Amplitude High Band, CRO bit 02=1 -8 -7 -6 dBmOTwist High-Band to low-Band, as above 1.0 2.0 3.0 dBLong Loop Detect Not valid for V.23 back channel -38 -28 dBmODynamic Range Refer to Performance Curves 43 dBt--------.Call Progress DetectorDetect level -3 dB points in 285 and 675 Hz -38--1-----dBmOReject level Test signal i~a 460 Hz sinusoid- ----45 dBmODelay Time -70 dBmO to -30 dBmO STEP---- _.40 msHold Time -30 dBmO to -70 dBmO STEP-_._--40 msHysteresis 2 dB-- ----t----Carrier DetectThreshold Single Tone -48 -43 dBmODelay Time.._._------V.21 10- -----"_.._-20 msV.23 Forward Channe I---6 12 msV.23 Back Channel 25 40 msHold Time1------V.21 6 20 msV.23 Forward Channel---3 8 msV.23 Back Channel 10 25 ms-----Hysteresis 2 dB-I3-191

~-SSI73K321LCCITT V.23, V.21Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMINNOM MAX UNITSSpecial Tone DetectorsDetect LevelDelay TimeSee definitions forTR bit DO mode-70 dBmO to -30 dBmO Step-48- ~--..------- ----43 dBmO2100 Hz answer tone1300 Hz calling tone390 HzV.23 back channel mark101020--25 ms. __.. -25 ms65 ms980 or 1650 HzV.21 marksHold Time-30 dBmO to -79 dBmO Step10-- -"----25 ms2100 Hz answer tone415 ms1300 Hz calling tone310 ms390 HzV.23 back channel mark980 or 1650 HzV.21 marksHysteresisDetect Freq. RangeOutput Smoothing FilterOutput loadOut of Band EnergyOutput ImpedanceAny Special ToneTXA pin; FSK SingleTone out for THO = -50 dBin .3 to 3.4 kHzFrequency> 12 kHz in all modesTXA pin, TXA Enabled1052-310-------- -----25 ms15 msdB--------+3 %--_.- -----kQ50 pF-60 dBmO20 50 nClock NoiseTXA pin; 76.8 kHz or122.88 kHz in V.23 main channel0.1 0.4 mVrms3-192

SSI73K321LCCITT V.23, V.21Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSTiming (Refer to Timing Diagrams)TALTLATLCTCLTRDTLLTRDFTRWTWWTOWTWOTCKDTCKWTDCKTACTCATWHCONDITIONS---CS/Addr. setup before ALE LowCSI Addr. hold after ALE LowALE Low to RDIWR LowRD/WR Control to ALE HighData out from RD LowALE widthData float after RD HighRD width-WRwidthData setup before WR HighData hold af!er WR HighData out after EXCLK LowWR after EXCLK LowData setup before EXCLK LowAddress setup before control*Address hold after control*Data Hold after EXCLK* Control for setup is the falling edge of RD or WR.Control for hold is the falling edge of RD or the rising edge of WR.MIN252030-503002001404010150150505020NOM MAX UNITSnsns- --- ---------.-- -------------""---_._.-------_.- ..- --nsns140 nsns5 ns25000 ns25000 nsnsns200 nsnsnsnsnsI3-193

SSI73K321LCCITT V.23, V.21Single-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE ~RDWRL TAL l...L 'JTlC .LTRWJ TCl r-------TLC J TWW I~ ~ I ... TOW ~ .. ,t~1-'r-..,1--~-TlA TAD TRDF I TWDADO-AD7 ---K ADDRESS )f-----K READ DATA)f-----K ADDRESS ~~CS ~- -J- -~- -J-READ TIMING DIAGRAM (SERIAL VERSION)EXClKRDAO-A2DATA --+WRITE TIMING DIAGRAM (SERIAL VERSION)EXClKHTWW-----+--------------------------------------~--"AO-A2 ---1-----------------------1+,DATA3-194

SSI73K321LCCITT V.23, V.21Single-Chip ModemAPPLICATIONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK-Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a DAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes.Two typical DAAarrangements are shown: one for a split ±5 or ±12volt design and one for a single 5 volt design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one for a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039/48 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontrollers or in applicationswhere only a limited number of port.lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the Serial mode, as explained in the datasheet pin description.In most applications the controllerwill monitor the serialdata for commands from the DTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent over the sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.IRS232LEVELCONVERTERSCl390 pFCACBCCCOCFRTSCTSOSROTROCOWRALE/:SSSIK-SERIESLOWPOWERFAMILYC2300pFBABBOADODBTXORXORXCLKTXCLKus. U6MC145406VRlMOVV250L20+5o~22KFIGURE 1: BaSic Box Modem with Dual-Supply Hybrid3-195

SSI73K321LCCITT V.23, V.21Single-Chip ModemDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the Signalappearing at the transformer, making the transmitsignal Common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This circuit(Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a single 5V supply. BecauseDTMF tones utilize a higher amplitude than data, thesesignals will clip if a single-ended drive approach isused. The bridged driver uses an extra op-amp (U1 A)to invert the Signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-amp then supplies half the drive signalto the transformer. The receive amplifier (U1 C) picksoff its signal at the junction of the impedance matchingresistor and the transformer. Because the bottom leg ofthe transformer is being driven in one direction by U1 Aand the resistor is driven in the opposite direction at thesame time by U1 B, the junction of the transformer andresistor remains relatively constant and the receivesignal is unaffected.DESIGN CONSIDERATIONSSilicon Systems' 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.Cl390pFR437.41< 1%C30.1 of'@)---l f----------

SSI73K321LCCITT V.23, V.21Single-Chip ModemUnlike digital logic circuitry, modem designs mustproperly contend with precise frequency tolerancesand very low level analog signals, to ensure acceptableperformance. Using good analog circuit design practiceswill generally result in a sound design. Followingare additional recommendations which should betaken into consideration when starting new designs.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a Parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01% accuracy.In order for a Parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LA YOUT CONSIDERATIONSGood analog/digital design rules must be used tocontrol system noise in orderto obtain highest performancein modem deSigns. The more digital circuitrypresent on the PC board, the more this attention tonoise control is needed. The modem should be treatedas a high impedance analog device. A 22 mF electrolyticcapacitor in parallel with a 0.1 mF ceramic capacitorbetween VDD and GND is recommended. Liberaluse of ground planes and larger traces on power andground are also highly favored. High speed digitalcircuits tend to generate a significant amount of EMI(Electro-Magnetic Interference) which must be minimizedin order to meet regulatory agency limitations.To accomplish this, high speed digital devices shouldbe locally bypassed, and the telephone line interfaceand K-Series device should be located close to eachother near the area of the board where the phone lineconnection is accessed. To avoid problems, powersupply and ground traces should be routed separatelyto the analog and digital functions on the board, anddigital signals should not be routed near low level orhigh impedance analog traces. The analog and digitalgrounds should only connect at one pOint near the K­Series device ground pin to avoid ground loops. The K­Series modem IC's should have both high frequencyand low frequency bypassing as close to the packageas possible.MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line simulator, operatingunder computer control. All tests were run fullduplex,using a Concord Data Systems 224 as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and all signal-to-noise (SIN) ratios reflect 3total power measurements similar to the CCITT V.56measurement specification. The individual tests aredefined as follows.BER vs. SINThis test measures the ability of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a DPSK modem will exhibitbetter BER-performance test curves receiving in thelow band than in the high band.BER VS. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamicrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels. The width of the "bowl" ofthese curves, taken at the BER point, is the measure ofdynamic range.3-197

10- 6 0 1 2 3 4 5 6 7 8 9 10 11 1210. 6 10 0 -10 -20 -30 -40 -50SSI73K321LCClll V.23, V.21Single-Chip ModemSSI73K321LBER vs SIGNAL TO NOISE10- 2 I V.21 OPERATION I-40 dBM\FLAT HIGH BAND10-3 1\ \~,\1\\1\ \~10.4\ ~~\ ~\\C2 HIGH BAND ~ ~ I--~3002 HIGH BAND ~~I\. \ l7\10-5 1\ f\. V'\ \\\ r\ \\ I LOW BAND RECEIVE ~FLAT, 3002, AND C2 LINES*SSI 73K321 LBER vs RECEIVE LEVEL (V.23)10- 2 r V.23 MAIN CHANNEL t10.3I RECEIVE OPERATIONC2 LINE, SIN = 9.5 dBw~a:~ 10-4a:a:wt= JOJ1_10-5 II\ /\v/_vt--SIGNAL TO NOISE (dB)RECEIVE LEVEL (dS)*SSI 73K321 LBER vs SIN (V.23 ONLY)**10- 2 ~ \ \./I\f\ , \3 1\ l...-1"""10-10-4I V.23 OPERATION r--40dBMH C2 EO. OFF I \ 3002 EO. OFF ~H FLAT EO. OFF...... t"-..\\ \3002 EO. ON f-I'vVl\ 1'( \* = "EO On" Indicates bit CR1 04 is set foradditional phase equalization.** 73K302L performance is similar to that=of the 73K322L V.23 operationcorresponds to Bell 202.10·5\ \ \ \I-- BACK CHANNEL I t-- FLAT EO. ON 1-I--j \ v ~II~ \~1 \ 1 1\C2EO.ON ~ I--\ '1 V \ \10. 6 .\ \-2 0 2 4 6 8 10 12 14 16 18 20 22SIGNAL TO NOISE (dB)3-198

SSI73K321LCCITT V.23, V.21Single-Chip ModemPACKAGE PIN DESIGNATIONS(TOP VIEW)CAUTION: Use handling procedures necessaryfor a static sensitive component.GNDXTLlAlRXAVREFRESETISETRXCLKRXDTXDEXCLKTXCLKINTClKXTllXTL2ADOADlAD2AD3AD4ADSAD6AD7ALEWRGNDRXAVREFRESETISETRXClKRXDTXDCSEXClKTXClKINTTXA, i255~6 ' 24Plee4 3 2 1 28 27 26PINOUTS8 ARE THE SAME AS 229 THE 28-PIN DIP 21lOLi 2011 q 1923ITXARDVDD12 13 14 15 16 17 18400-Mil22-Pin DIP600-Mil28-Pin DIP28-PinPLCCORDERING INFORMATIONPART DESCRIPTIONORDER NO.PKG.MARKSSI 73K321 L with Parallel Bus Interface28-Pin 5V SupplyPlastic Dual-In-LinePlastic Leaded Chip CarrierSSI 73K321 L with Serial Interface22-Pin 5V SupplyPlastic Dual-In-Line73K321 L-IP73K321L-IH73K321 SL-IP73K321 L-IP73K321 L-IH73K321 SL-IPNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680, (714) 573-6000, FAX: (714) 573-69141292 - rev.3-199Protected by the following patents: (4,691,172) (4,777,453)©1989 Silicon Systems, Inc.

Notes:3-200

551 73K322LCCITT V.23, V.22, V.21Single-Chip ModemJanuary 1994DESCRIPTIONThe SSI 73K322L is a highly integrated single-chipmodem IC which provides the functions needed toconstruct a CCITT V.23, V.22 and V.21 compatiblemodem, capable of 1200 or 0-300 bit/s full-duplexoperation or 0-1200 biVs half-duplex operation with orwithout the back channel over dial-up lines. TheSSI 73K322L is an enhancement of the SSI 73K221 Lsingle-chip modem with performance characteristicssuitable for European and Asian telephone systems.The SSI 73K322L produces either 550 or 1800 Hzguard tone, recognizes and generates a 2100 Hzanswer tone, and supports V.21 for 300 Hz FSKoperation. It also operates in V.23, 1200 biVs FSKmode. The SSI73K322L integrates analog, digital, andswitched-capacitor array functions on a singlesubstrate,offering excellent performance and a highlevel of functional integration in a single 28- or 22-pinDIP configuration. The SSI73K322L operates from asingle +5V supply with very low power consumption.The SSI 73K322L includes the DPSK and FSKmodulator/demodulator functions, call progress andhandshake tone monitor test modes, and a tonegenerator capable of producing DTM F, answer, callingand 550 or 1800 Hz guard tone. This device supportsV.23, V.22 (except mode v) and V. 21 modes ofoperation, allowing both synchronous and(Continued)BLOCK DIAGRAMFEATURESOne-chip CCITT V.23, V.22 and V.21 standardcompatible modem data pumpFull-duplex operation at 0-300 bitls (FSK) or 600 and1200 bitls (DPSK) or 0-1200 bitls (FSK) forwardchannel with or without 0-75 bitls back channelInterfaces directly with standard microprocessors(8048, 80C51 typical)Serial or parallel microprocessor bus for controlSerial port for data transferBoth synchronous and asynchronous modes ofoperationCall progress, carrier, preCise answer tone(2100 Hz), calling tone (1300 Hz) and FSK markdetectorsDTMF and 550 or 1800 Hz guard tone generatorsTest modes available: ALB, DL, RDL, Mark, Space,Alternating bit patternsPrecise automatic gain control allows 45 dBdynamic rangeCMOS technology for low power consumptionusing 30 mW @ 5V from a single power supplySurface mount PLCC package availablePIN DIAGRAMIADO-A0728 ~ GND27 P RXA26 VREFRDWRALECSRESETINTTXD 0--------+-1RXD o-------L-_..JTXARXAAD2AD3AD4ADSAD6AD7WRRDCAUTION: Use handling procedures necessaryfor a static sensitive component.0194 - rev.3-201

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemDESCRIPTION (continued)asynchronous communications. The SSI 73K322L isdesigned to appear to the systems designer as amicroprocessor peripheral, and will easily interfacewith popular one-chip microprocessors (80C51 typical)for control of modem functions through its 8-bitmultiplexed address/data bus or via an optional serialcontrol bus. An ALE control line simplifies addressdemultiplexing. Data communications occurs througha separate serial port only.The SSI73K322L is ideal for use in either free standingor integral system modem products where multi-standarddata communications over the 2-wire switchedtelephone network is desired. Its high functionality, lowpower consumption and efficient packaging simplifydesign requirements and increase system reliability. Acomplete modem requires only the addition of thephone line interface, a control microprocessor, andRS-232 level converter for a typical system. TheSSI 73K322L is part of Silicon Systems K-Series familyof pin and function compatible single-chip modemproducts. These devices allow systems to be configuredfor higher speeds and Bell or CCITT operationwith only a single component change.OPERATIONASYNCHRONOUS MODEData transmission for the DPSK mode requires thatdata ultimately be transmitted in a synchronous fashion.The SSI 73K322L includes ASYNC/SYNC andSYNC/ASYNC converters which delete or insert stopbits in order to transmit data at a regular rate. InAsynchronous mode the serial data comes from theTXD pin into the ASYNC/SYNC converter. TheASYNC/SYNC converter accepts the data provided onthe TXD pin which normally must be 1200 or 600 bit/s+ 1.0%, -2.5%. The rate converter will then insert ordelete stop bits in order to output a signal which is 1200or 600 biVs± 0.01% (± 0.01% is the crystal tolerance).The SYNC/ASYNC converter also has an extendedoverspeed mode which allows selection of an outputoverspeed range of either +1% or +2.3%. In the extendedoverspeed mode, stop bits are output at 7/8 thenormal width.The serial data stream from the transmit buffer or therate converter is passed through the data scramblerand onto the analog modulator. The data scramblercan be bypassed under processor control whenunscrambled data must be transmitted. If serial inputdata contains a break signal through one character(including sJart and stop bits) the break will beextended to at least 2 • N + 3 bits long (where N is thenumber of transmitted bits/character).Serial data from the demodulator is passed firstthrough the data descrambler and then through theSYNC/ASYNC converter. The ASYNC/ASYNC converterwillreinsert any deleted stop bits and output dataat an intra-character rate (bit-to-bit timing) of no greaterthan 1219 biVs. An incoming break signal (low throughtwo characters) will be passed through without incorrectlyinserting a stop bit.SYNCHRONOUS MODEThe CCITTV.22 standard defines synchronous operationat 600 and 1200 bit/so Operation is similar to that ofthe Asynchronous mode except that data must besynchronized to a provided clock and no variation indata transfer rate is allowable. Serial input data appearingat TXD must be valid on the rising edge ofTXCLK.TXCLK is an internally derived signal in Internal modeand is connected internally to the RXCLK pin in Slavemode. Receive data at the RXD pin is clocked out onthe falling edge of RXCLK. The ASYNCH/SYNCHconverter is bypassed when Synchronous mode isselected and data is transmitted out at the same rate asit is input.DPSK MODULATOR/DEMODULATORIn DP5K mode the 551 73K322L modulates a serial bitstream into di-bit pairs that are represented by fourpossible phase shifts as prescribed by the V.22 standards.The base-band signal is then filtered to reduceintersymbol interference on the bandlimited 2-wiretelephone line. Transmission occurs using either a1200 Hz (Originate mode) or 2400 Hz carrier (Answermode). Demodulation is the reverse of the modulationprocess, with the incoming analog signal eventuallydecoded into di-bits and converted back to a serial bitstream. The demodulator also recovers the clockwhich was encoded into the analog signal duringmodulation. Demodulation occurs using either a1200 Hz carrier (Answer mode or ALB Originate mode)or a 2400 Hz carrier (Originate mode or ALB Answermode). The SSI 73K322L uses a phase locked loop. coherent demodulation technique for optimumreceiver performance.3-202

SSI73K322LCClll V.23, V.22, V.21Single-Chip ModemFSK MODULATOR/DEMODULATORThe F5K modulator produces a frequency modulatedanalog output signal using two discrete frequencies torepresent the binary data. V.21 mode uses 980 and1180 Hz (originate, mark and space) or 1650 and1850 Hz (answer, mark and space). V.23 mode uses1300 and 2100 Hz for the main channel and 390 and450 Hz for the back channel. The modulation rate ofthe back channel is up to 75 baud. Demodulationinvolves detecting the received frequencies anddecoding them into the appropriate binary value. Therate converter and scrambler/descrambler are automaticallybypassed in the V.21 or V.23 modes.PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and provide compromise delay equalizationand rejection of out-of-band Signals in thereceive channel. Amplitude and phase equalizationare necessary to compensate for distortion of thetransmission line and to reduce intersymbol interferencein the bandlimited receive signal. The transmitsignal filtering approximates a 75% square root ofraised Cosine frequency response characteristic.AGCThe automatic gain control maintains a signal level atthe input to the demodulators which is constant towithin 1 dB. It corrects quickly for increases in signalwhich would cause clipping and provides a totalreceiver dynamic range of >45 dB.PARALLEL BUS INTERFACEFour 8-bit registers are provided for control, optionselect and status monitoring. These registers are addressedwith the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as four consecutive memory locations.Two control registers and the tone register areread/write memory. The detect register is read only andcannot be modified except by modem response tomonitored parameters.SERIAL COMMAND INTERFACEThe serial command interface allows access to the551 73K322L control and status registers via a serialcommand port (22-pin version only). In this mode theAO , A 1 and A2lines provide register addresses for datapassed through the data pin under control of the RDand WR lines. A read operation is initiated when the RDline is taken low. The first bit is available after RD isbrought low and the next seven cycles of EXCLK willthen transfer out seven bits of the selected addresslocation L5B first. A write takes place by shifting in eightbits of data L5B first for eight consecutive cycles ofEXCLK. WR is then pulsed low and data transferredint~e selected register occurs on the rising edgeofWR.SPECIAL DETECT CIRCUITRYThe special detect circuitry monitors the receivedanalog Signal to determine status or presence of carrier,answer tone and weak received signal (long loopcondition), special tones such as F5K marking and the1300 Hz calling tone are also detected. A highly frequencyselective call progress detector provides adequatediscrimination to accurately detect Europeancall progress Signals.DTMF GENERATORThe DTMF generator will output one of 16 standardtone pairs determined by a 4-bit binary value and TXDTMF mode bit previously loaded into the tone register.Tone generation is initiated when the DTMF modeis selected using the tone register and the transmitenable (CRO bit 01) is changed from 0 to 1.I3-203

SSI73K322LCCllT V.23, V.22, V.21Single-Chip ModemPIN DESCRIPTIONPOWERNAME 28-PIN 22-PINGND 28 1VDD 15 11VREF 26 21ISET 24 19TYPEII0IDESCRIPTIONSystem Ground.Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 J..lFcapacitors to GND.An internally generated reference voltage. Bypass with0.1 J..lF capacitor to GND.Chip current reference. Sets bias current for op-amps. Thechip current is set by connecting this pin to VDD through a2 MQ resistor. ISET should be bypassed to GND with a0.1 J..lF capacitor.PARALLEL MICROPROCESSOR INTERFACEALE 12 - IADO-AD7 4-11 - 1/0CS 20 - IClK 1 2 0INT 17 13 0RD 14 - IRESET 25 20 IAddress latch enable. The falling edge of ALE latches theaddress on ADO-AD2 and the chip select on CS.Addressldata bus. These bidirectional tri-state multiplexedlines carry information to and from the internalregisters.--Chip select. A low on this pin during the falling edge of ALEallows a read cycle or a write cycle to occur. ADO-AD7 willnot be driven and no registers will be written if CS (latched)is not active. The state of CS is latched on the falling edgeof ALE.Output clock. This pin is selectable under processor controlto be either the crystal frequency (for use as a processorclock) or 16 x the data rate for use as a baud rate clock inDPSK modes only. The pin defaults to the crystal frequencyon reset.I nterrupt. This open drain output Signal is used to inform theprocessor that a detect flag has occurred. The processormust then read the detect register to determine whichdetect triggered the interrupt. INT will stay low until theprocessor reads the detect register or does a full reset.Read. A low requests a read of the SSI 73K322l internalregisters. Data cannot be output unless both RD and thelatched CS are active or low.Reset. An active high signal on this pin will put the chip intoan inactive state. All control register bits (CRO, CR1, Tone)will be reset. The output of the elK pin will be set to thecrystal frequency. An internal pull down resistor permitspower on reset using a capacitor to VDD.3-204

SSI73K322LCClll V.23, V.22, V.21Single-Chip ModemPARALLEL MICROPROCESSOR INTERFACE (Continued)NAME 28·PIN 22·PIN TYPE DESCRIPTIONWR 13 - I Write. A low on this informs the SSI73K322L that data isavailable on ADO-AD7 for writing into an internal register.Data is latched on the rising edge of WR. No data is writtenunless both WR and the latched CS are low.SERIAL MICROPROCESSOR INTERFACEAO-A2 - 5-7 I Register Address Selection. These lines carry registeraddresses and should be valid during any read or writeoperation.DATA - 8 I/O Serial Control Data. Data for a read/write operation isclocked in or out on the falling edge of the EXCLK pin. Thedirection of data flow is controlled by the RD pin. RD lowoutputs data. RD high inputs d~ta.RD - 10 I Read. A low on this input informs the SSI73K322L that dataor status information is being read by the processor. Thefalling edge of the RD signal will initiate a read from theaddressed register. The RD signal must continue for eightfalling edges of EXCLK in order to read all eight bits of thereferenced register. Read data is provided LSB first. Datawill not be output unless the RD si~~al is active.WR - 9 I Write. A low on th is input informs the SS I 73K322 L that dataor status information has been shifted in through the DATApin and is available for writing to an internal register. Thenormal procedure for a write is to shift in data LSB first onthe DATA pin for eight consecutive falling edges of EXCLKand then to pulse WR low. Data is written on the rising edgeofWR.- ...--~------Note: In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with thepins;AO,A1, A2, DATA, and an unconnected pin. Also, the RDandWR controls are used differently.The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,respectively.IDTE USER INTERFACENAME 28·PIN 22·PIN TYPE DESCRIPTIONEXCLK 19 15 I External Clock. This signal is used only in synchronousDPSK transmission when the external timing option hasbeen selected. In the External Timing mode the riSing edgeof EXCLK is used to strobe synchronous DPSK transmitdata available on the TXD pin. Also used for serial controlinterface.3-205

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemRS·232 INTERFACE (Continued)NAME 28-PIN 22·PINRXCLK 23 18RXD 22 17TXCLK 18 14TXD 21 16TYPE000IDESCRIPTIONReceive Clock. The falling edge of this clock output iscoincident with the transitions in the serial received DPSKdata output. The rising edge of RXCLK can be used to latchthe valid output data. RXCLK will be valid as long as acarrier is present. In V.23 or V.21 mode a clock which is16 x1200 (or 16 x 75) or 16 x 300 Hz baud data rate isoutput, respectively, for driving a UART.Received Data Output. Serial receive data is available onthis pin. The data is always valid on the rising edge ofRXCLK when in Synchronous mode. RXD will outputconstant marks if no carrier is detected.Transmit Clock. This signal is used only in synchronousDPSK transmission to latch serial input data on the TXDpin. Data must be provided so that valid data is availableon the rising edge of the TXCLK. The transmit clock isderived from different sources depending upon the Synchronizationmode selection. In Internal Mode the clock is1200 Hz generated internally. In External Mode TXCLK isphase locked to the EXCLK pin. In Slave Mode TXCLK isphase locked to the RXCLK pin. TXCLK is always active. InV.23 or V.21 mode the output is a 16 x 1200 (or 16 x 75) or16 x 300 Hz baud clock, respectively for driving a UART.Transmit Data Input. Serial data fortransmission is appliedon this pin. In Synchronous modes, the data must be validon the rising edge of the TXCLK clock. In Asynchronousmodes (1200 or 300 baud) no clocking is necessary. DPSKmust be 1200/600 bitls +1%, -2.5% or +2.3%, -2.5 % inExtended Overs peed mode.ANALOG INTERFACE AND OSCILLATORRXA 27 22 ITXA 16 12 0XTL1 2 3 IXTL2 3 4 IReceived modulated analog signal input from the telephoneline interface.Transmit analog output to the telephone line interface.These pins are for the internal crystal oscillator requiringa 11.0592 MHz Parallel mode crystal and two load capacitorsto Ground. XTL2 can also be driven from an externalclock.3-206

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemREGISTER DESCRIPTIONSFour 8-bit internal registers are accessible for controland status monitoring. The registers are accessed inread or write operations by addressing the AO and A 1address lines in Serial mode, orthe ADO and AD1 linesin Parallel mode. The ADO and AD11ines are latched byALE. Register C RO controls the method by which datais transferred over the phone line. CR1 controls theinterface between the microprocessor and theSSI73K322L internal state. DR is a detect registerwhich provides an indication of monitored modemstatus conditions. TR, the tone control register, controlsthe DTM F generator, answer and guard tones andRXD output gate used in the modem initial connectsequence. All registers are read/write except for DRwhich is read only. Register control and status bits areidentified below:REGISTER BIT SUMMARYCRO 000COOTROLENABLEREGISTER CR1 001 DETECT1 INTERRUPTDETECTRECEIVEREGISTER DR 010 DATABYPASSSCRAMBLER!CLK TEST TESTADDPH.EQ.COOTROL RESET MODE MODE(V.23) 1 0UNSCR. CARRIER SPECIAL CALL LONGMARKS DETECT TONE PROGRESS LOOPITOOECOOTROL m 011REGISTERTRANSMITDTMFDTMF3DTMF21V.23 FOXCOOTROLREGISTER CR2 1002COOTROLREGISTER CR3 101310REGISTER 10 110NOTE:When a register containing reservedcontrol bits is written into, the reserved bitsmust be programmed as O's.3-207

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemREGISTER ADDRESS TABLE0=1200 BITtS DPSK1 =600 81TtS DPSKO=V.23 FSK1=V.21 FSKOOOO=PWR DOWN0001=INT SYNCH001 O.EXT SYNCH0011 =SLAVE SYNCH0100=ASYNCH 8 BITSiCHAR010hASYNCH 9 BITSiCHAR0110=ASYNCH 10 BITSICHAR011hASYNCH 11 BITS/CHAR1100.FSKO=DISABLETXA OUTPUT1=ENABLETXA OUTPUTIN V.21 OR V.22 MODE'O=ANSWER1.0RIGINATEIN V.23 MODE:O.RECEIVE @ 1200 BITtS,TRANSMIT @ 75 BITtS1=RECEIVE @ 75 BITtS,TRANSMIT @ 1200 81TtSO=XTAL1=16 X DATARATE OUTPUTAT CLK PIN INDPSKMODEONLYO=NORMAL1=ALLOWS V.23 FULLDUPLEX OPERATION0=1800 Hz G.T. (V.22).2225 Hz ANS TONEGENERATED, FSKMARK DETECTSELECTED1 =550 Hz G.T. (V.22)2100 Hz ANS TONEGENERATED &DETECTED (V.21 , V.22)1300 Hz DETECTED (V.23)00XX.73K212L, 322L, 321L01XX.73K221L,302L1 OXX.73K222L1100_73K224L11 10.73K324L1101 =73K312L3-208

SSI73K322LCCITT V.23, V.22, V.21Single-Chip Modem)ICONTROL REGISTER 004D7D5CRO MOOUL. TRANSMIT TRANSMIT000 OPTION MODE 3 MOOE2BIT NO. NAME CONDITIONDO Answer/ 0highOriginate01 Transmit 0Enable1105 04 03 0205,04,03, Transmit 0 0 0 002 Mode0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 1 o 003 02 01 DOTRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 1 MOOEO ENABLE ORIGINATEDESCRIPTIONSelects Answer mode in V.21 and V.22 (transmit inband), receive in low band or in V.23 HOX mode,receive at 1200 bit/s and transmit at 75 bit/soSelects Originate mode in V.21 and V.22 (transmit inlow band) ,receive in high band or in V.23 HOX mode,receive at 75 bitls and transmit at 1200 bit/soNote: This bit works with TR bit DO to program specialtones detected in Tone Register. See detect and tone"'~":H"";:).')I~;mlp.~ transmit output atEnables transmit output atNote: Answer tone and OTMF TX control require TXenable.Selects Power Down mode. All functions disabledexcept digital interface.Internal Synchronous mode. In this mode TXCLK is aninternally derived 1200 Hz signal. Serial input dataappearing at TXO must be valid on the rising edge ofTXCLK. Receive data is clocked out of RXO on thefalling edge of RXCLK.External Synchronous mode. Operation is identical tointernal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 1200 Hz ± 0.01 % clock mustbe supplied externally.Slave Synchronous mode. Same operation as otherSynchronous modes. TXCLK is connected internally tothe RXCLK pin in this mode.Selects OPSK Asynchronous mode - 8 bits/character(1 start bit, 6 data bits, 1 stop bit).Selects OPSK Asynchronous mode - 9 bits/character(1 start bit, 7 data bits, 1 stop bit).Selects OPSK Asynchronous mode - 10 bits/character(1 start bit, 8 data bits, 1 stop bit).Selects OPSK Asynchronous mode - 11 bits/character(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).3-209Selects FSK VI-'''' I ClUV II

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemCONTROL REGISTER 0 (Continued)07050403 02 01 DOCRO MOOUL.000 OPTIONTRANSMITMODE 2TRANSMIT TRANSMIT ANSWER/MODE 0 ENABLE ORIGINATE07 05 04Selects:07 ModulationOptionFSK CCITT V.21 mode.CONTROL REGISTER 107 06TRANSMIT TRANSMITCR1 PATTERN PATTERN001 1 005ENABLEDETECTINTER.04 03 02 01 DOBYPASS ClK TEST TESTSCRAMB/ CONTROL RESET MODE MODEADD 1 0PH. Ea.BIT NO. NAME CONDITION01 DO01,00 Test Mode 0 a0 11 01 102 Reset 01DESCRIPTIONSelects normal operating mode.Analog loopback mode. Loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same center frequency as the transmitter. Tosquelch the TXA pin, transmit enable must beforced low.Selects remote digital loopback. Received data islooped back to transmit data internally, and RXO isforced to a mark. Data on TXD is ignored.Selects local digital loopback. Internally loops TXDback to RXO and continues to transmit carrier fromTXA pin.Selects normal operation.Resets modem to power down state. All control registerbits (CRO, CR1 , Tone) are resetto zero. The outputof the ClK pin will be set to the crystal frequency.3-210

-~ --SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemCONTROL REGISTER 1 (Continued)07 06 05TRANSMIT TRANSMIT ENABLECR1 PATTERN PATTERN DETECT001 1 0 INTER.BIT NO. NAME CONDITION03 ClK Control 004 Bypass 0Scrambler/Add Phase 1Equalization05 Enable Oetect 01107 0607,06 Transmit 0 0Pattern0 11 01 104 03 02 01 DOBYPASS ClK TEST TESTSCRAMB/ CONTROL RESET MODE MODEADD 1 0PH. Ea.DESCRIPTIONSelects 11.0592 MHz crystal echo output at ClKpin.Selects 16 X the data rate, output at ClK pin in DPSKmodes only.Selects normal operation. DPSK data is passedthrough scrambler.Selects Scrambler Bypass. DPSK data is routedaround scrambler in the transmit path. In V.23 mode,additional phase equalization is added to the mainchannel filters when 04 is set to 1.Disables interrupt at INT pin.Enables INT output. An interrupts will be generatedwith a change in status of DR bits 01-04. The specialtone and call progress detect interrupts are maskedwhen the TX enable bit is set. Carrier detect is maskedwhen TX DTMF is activated. All interrupts will bedisabled if the device is in power down mode.-Selects normal data transmission as controlled by thestate of the TXD pin.Selects an alternating mark/space transmit pattern formodem testing.Selects a constant mark transmit pattern.Selects a constant space transmit pattern.I3-211

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemDETECT REGISTERD5D4 D3 D2 D1DODR010RECEIVEDATAUNSCR. CARR. SPECIAL CALLMARK DETECT TONE PROG.LONGLOOPBIT NO.NAMECONDITIONDESCRIPTIONDOLong LoopD1D2Call ProgressDetectSpecial ToneDetect1----------+--,-nd-i-ca-t-es-p-re-s-en-c-e-o-f-c-a-lI-p-rO-g-re-s-s-t-on-e-s-. -T-h-e-c-a-II-Ioprogress detection circuitry is activated by energy inthe normal 350 to 620 Hz call progress band.No special tone detected as programmed by CRO bit DOand Tone Register bit DO.(1) 2100 Hz answer tone if DO of TR= 1 and the deviceis in V.21 or V.22 originate mode.(2) 1300 Hz calling tone if DO of TR=1 and the deviceis in V.21, or V.22 answer mode.(3) an FSK mark in the mode the device is set toreceive.D3D4D5D7Carrier Detect I---~---L~~~~~~~~~~~~~~~-----JIndicated carrier has been detected in the receivedchannel.UnscrambledMa~ I----------+--,-nd-i-ca-t-es-d-e-te-c-ti-o-n-of-u-n-s-cr-a-m-b-,e-d-m-a-r-ks-i-n----IReceiveDatathe received data. A valid indication requires thatunscrambled marks be received for> 165.5 ± 6.5 ms.Continuously outputs the received data stream. Thisdata is the same as that output on the RXD pin, but itis not disabled when RXD is tri-stated.3-212

SSI73K322LCClll V.23, V.22, V.21Single-Chip ModemTONE REGISTER07 06 D5RXD TRANSMIT TRANSMITTR OUTPUT GUARD/ ANSWER011 CONTR. CALLING TONETONE04 D3TRANSMITDTMFDTMF3D2 D1 DODTMF 21 DTMF 11 DTMF 01V.23 FDX OVER- G.T./ANSW./SPEED SP. TONE!SELECTBIT NO. NAME CONDITIOND6 D5 D4 DODO DTMFO X X 1 XGuard Tone/ 1 X 0 0Answer ToneSpecial T onel 1 X 0 1DetecVSelectX X 0 0X X 0 1X 1 0 0X 1 0 1D4 D1D1 DTMF 1/ 0 0Overspeed0 1D2 DTMF 2/ 0V.23 FDX1D3 D2 D1 DOD3, D2, DTMF 3, 0 0 0 0-D1,DO 2,1,0 1 1 1 1DESCRIPTIONDO interacts with bits D6, D4, and CRO as shown.Transmit DTMF tones.Select 1800 Hz guard tone if in V.22 and Answer modeinCRO.Select 550 Hz guard tone if in V.22 and Answer modeinCRO.Mark of an FSK mode selected in CRO is to be detectedin D2 of DR.2100 Hz answer tone will be detected in D2 of DR ifV.21 or V.22 Originate mode is selected in CRO.1300 Hz calling tone will be detected in D20f DR ifV.21,or V.22 Answer mode is selected in CRO.Transmit 2225 Hz Answer ToneTransmit 2100 Hz Answer ToneD1 interacts with D4 as shown.Asynchronous DPSK 1200 or 600 bitls +1.0% -2.5%.Asynchronous DPSK 1200 or 600 bitls +2.3% -2.5%.Half-duplex asymetric operati_on in V.23 mode.Full-duplex (4-wire) operation in\(23 mode.Programs 1 of 16 DTMF tone pairs that will betransmitted when TX DTM F and TX enable bit (CRO, bitD1) are set. Tone encoding is shown below:KEYBOARD DTMFCODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGH3-2131 0 0 0 1 697 12092 0 0 1 0 697 13363 0 0 1 1 697 14774 0 1 0 0 770 12095 0 1 0 1 770 13366 0 1 1 0 770 14777 0 1 1 1 852 1209I

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemTONE REGISTER (Continued)D7 D6 D5RXD TRANSMIT TRANSMITTR OUTPUT GUARD/ ANSWER011 CONTR. CALLING TONETONESIT NO. NAME CONDITIOND3, D2,D1, DO(Cont.)D4 Transmit 0DTMF1D5 Transmit 0Answer Tone1D6 TX Guard or 0Calling ToneD7 RXD Output 0Control11D4 D3 D2 D1 DOTRANSMIT DTMF 2/ DTMF 1/ DTMF 0/DTMF DTMF3 V.23 FDX OVER- GUARD/SPEED SPECIALTONE SELDESCRIPTIONKEYBOARD DTMFCODE TONESEQUIVALENT D3 D2 D1 DO LOW HIGH8 1 0 0 0 852 13369 1 0 0 1 852 14770 1 0 1 0 941 1336* 1 0 1 1 941 1209# 1 1 0 0 941 1477A 1 1 0 1 697 1633B 1 1 1 0 770 1633C 1 1 1 1 852 1633D 0 0 0 0 941 1633Disable DTMF.Activate DTMF.The selected DTMF tones aretransmitted continuously when this bit is high.TX DTMF overrides all other transmit functions.----_ ..Disables answer tone generator.Enables answer tone generator. A 2100 Hz answertone will be transmitted continuously when the transmitenable bit is set. The device must be in Answer mode.To transmit answer tone, the device must be in DPSKAnswer mode.Disables guard/calling tone generator.Transmit guard tone if in V.22 and answering;otherwise transmit calling tone, in any other modeincluding V.23 mode.Enables RXD pin. Receive data will be output onRXD.Disables RXD pin. The RXD pin reverts to a highimpedance with internal weak pull-up resistor.3-214

----~~--~---SSI73K322LCClll V.23, V.22, V.21Single-Chip Modem10 REGISTERD7D6D5D4ID110IDIDIDIDBIT NO.NAMECONDITIONDESCRIPTIOND7 D6 D5 D4Indicates Device:D7, D6, D5 DeviceD4IdentificationSignatureIELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETER RATING UNITVDD Supply Voltage 14 V1----Storage Temperature -65 to 150 °cSoldering Temperature (10 sec.) 260f----------°cApplied Voltage -0.3 to VDD+0.3 VNote: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITS~----VDD Supply voltage 4.5 5 5.5 VTA, Operating Free-Air Temp. -40-+85 °cClock Variation (11.0592 MHz) Crystal or external clock -0.01 +0.01%External Components (Refer to Application section for placement.)VREF Bypass Capacitor (External to GND) 0.1 IJ.FBias setting resistor (Placed between VDD and ISET pins) 1.8-.. -.-2-_.• -2.2 MnISET Bypass Capacitor (ISET pin to GND) 0.1 J.lFVDD Bypass Capacitor 1 (External to GND) 0.1 IJ.F--_._-VDD Bypass Capacitor 2 (External to GND) 22 J.lFXTL 1 Load Capacitor Depends on crystal characteristics; 40 pFXTL2 Load Capacitor from pin to GND 203-215

-.-~SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemDC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN100, Supply Current ISET Resistor = 2 MQI DDA, ActiveIDD1, Power-downIDD2, Power-downDigital InputsVIH, Input High VoltageClK = 11.0592 MHzClK = 11.0592 MHzClK = 19.200 KHzReset, XTl1 , XTl2 3.0All other inputs 2.0Vll, Input low Voltage 0IIH, Input High CurrentVI = VIH MaxIll, Input low Current VI = Vil Min -200Reset Pull-down Current Reset = VDD 1I nput CapacitanceDigital OutputsAll Digital Input PinsVOH, Output High Voltage 10H MIN = -0.4 rnA 2.4VOL, Output low VoltageVOL, ClK Output10 MAX = 1.6 rnA10 = 3.6 rnARXD Tri-State Pull-up Curro RXD = GND -1CMAX, ClK OutputCapacitanceInputsMaximum Capacitive loadCapacitance, all Digital Input pinsXTAl1, 2 load Capacitors Depends on crystal characteristics 15ClKMaximum Capacitive load--f---------NOM MAX UNITS---8 12 rnA--------- ----------- --~---- - .._..'.-----_._. -_._---4 rnA3 rnAVDDVDDVV0.8 V100 IJAIJA50 IJA10 pFVDDV0.4 V0.6 V-50 IJA15 pF10 pF60 pF15 pF3-216

-------~~~ ..SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING(TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.)PARAMETERS CONDITIONS MIN NOM MAX UNITSDPSK ModulatorCarrier Suppression Measured at TXA 45]dBOutput Amplitude TX scrambled marks -11 -10 -9 dBmOFSK ModulatorOutput Freq. Error ClK = 11.0592 MHz -0.35 +0.35%Transmit level Transmit Dotting Pattern -11 -10 -9 dBmO~--------.~-~c------~---Harmonic Distortion TH D in the alternate band -60 -50 dBin 700-2900 Hz band DPSK or FSK-- .~-Output Bias Distortion Transmit Dotting Pattern ±3%In AlB@ RXD---Total Output Jitter Random Inpu_t in ALB @ RXD -10---+10 0/0DTMF GeneratorFreq. Accuracy Must be in V.22 mode -.25 +.25 %Output Amplitude low Band, V.22 mode -10 -9 -8 dBmO1----------Output Amplitude High Band, '(22 mode -8 -7 -6 dBmOTwist High-Band to low-Band, V.22 mode 1.0 2.0 3.0 dBLong Loop Detect With Sinusoid -38 -28 dBmO-.-Dynamic Range Refer to Performance Curves 45 dBNote:Parameters expressed in dBmO refer to the following definition:o dB loss in the Transmit path to the line.2 dB gain in the Receive path from the line.Refer to the Basic Box Modem diagram in the Applications section for the DAA design.- ---- .. --.I3-217

SSI73K322LCCllT V.23, V.22, V.21Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMINNOM MAX UNITSCall Prog ress DetectorDetect Level-3 dB points in 285 and 675 Hz-38-------.-dBmOReject LevelDelay TimeHold TimeHysteresisCarrier DetectTest signal is a 460 Hz sinusoid-70 dBmO to -30 dBmO STEP-30 dBmO to -70 dBmO STEP2-- -~--.~-~-------------45 dBmO40 ms40 msdBThresholdDelay TimeDPSK or FSK receive data-48---43 dBmOV.211020 msV.22V.23 Forward ChannelV.23 Back ChannelHold TimeV.21156256--_.- .---------- ,-----32 ms12 ms40 ms20 msV.221024 msV.23 Forward ChannelV.23 Back Channel310f---8 ms25 msHysteresisSpecial Tone DetectorsDetect LevelSee definitions forTR bit DO mode2-48.--,--dB-43 dBmODelay Time2100 Hz answer tone1300 Hz calling tone1010-- -25 ms25 ms390 HzV.23 back channel mark2065 ms3·218

SSI73K322LCClll V.23, V.22, V.21Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMIN NOM MAX UNITSSpecial Tone Detectors (Continued)980 or 1650 HzV.21 marksHold Time2100 Hz answer tone1300 Hz calling tone390 HzV.23 back channel mark980 or 1650 HzV.21 marksHysteresisDetect Freq. RangeOutput Smoothing FilterOutput loadOut of Band EnergyOutput ImpedanceClock NoiseCarrierVCOCapture RangeCapture TimeRecovered ClockCapture RangeData Delay TimeAny Special ToneTXA pin; FSK SingleTone out for THD = -50 dBin 0.3 to 3.4 kHzFrequency> 12 kHz in all modesTXA pin, TXA enabledTXA pin; 76.8 kHz or122.88 kHz in V.23 main channelOriginate or Answer-10Hz to +10 Hz CarrierFreq. Change Assum.% of frequencycenter frequency(center at 1200 Hz)Analog data in at RXA pin toreceive data valid at RXD pin_ .. _._-------.10 25 ms~~~~--------4--_..•.._-_ ...15 ms3-_._------10 ms10 25 ms._----5 15 ms-------2 dB--.-- ~--3 +3 %--------_._._-_ ..10 kQ---50 pF-60 dBmO~~---------20 50 Q0.1 0.4 mVrms-- ----10 +10 Hz40 l100 ms_____ L-__ ~_-------625 +625 ppm--~--- -~-30 50 msI3-219

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMIN NOM MAX UNITSGuard Tone GeneratorTone AccuracyTone Level(Below DPSK Output)Harmonic Distortion700 to 2900 HzTiming (Refer to Timing Diagrams)TALTLATLCTCLTRDTLLTRDFTRWTWWTOWTWOTCKDTCKWTDCKTACTCATWH550 or 1800 Hz550 Hz1800 Hz550 HzCS/Addr. setup before ALE Low-CSI Addr. hold after ALE LowALE Low to RDIWR LowRD/WR Control to ALE HighData out from RD LowALE widthData float after B[) HighRDwidthWRwidth-Data setup before WR HighData hold afterWR HighData out after EXCLK LowWR after EXCLK LowData setup before EXCLK LowAddress setup before control*Address hold after control*Data Hold after EXCLK* Control for setup is the falling edge of RD or WR.Control for hold is the falling edge of RD or the rising edge of WR.-20 +20 Hz-4.0 -3.0 -2.0 dB-7.0 -6.0----5.0 dB-50 dB--- -------25 -_._._-_ ... _---ns--20 ns30 ns-5 ns0 140 ns30 ns---.--0 5 ns200 25000 ns140 25000 ns40--- --ns10 ns200---_.ns150 ns--150.._-_.._-ns50 ns50 ns----_ ...20~---------3-220

------~--SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE~ ~TlC ---..L TRW J TClAD-+ +TlC 1 TWW JWA--~TlA TRD TRDF ~DL TAL , .I!.i ~ TDW '"ADO-AD7 -1( ADDRESS }-----K READ DATA}-----K ADDRESS ~~~as -=1- -~- -~--~- ~~--IREAD TIMING DIAGRAM (SERIAL VERSION)EXClKADI'------+--------~----------rAO-A2DATA --+WRITE TIMING DIAGRAM (SERIAL VERSION)EXClK --1 r=_--+--_________ --+------,rI TWWTCKW I ~I ~ TCAAO-A2 ----f------------------~··-----·-tfDATA3-221

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemAPPLICATIONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK-Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a DAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes.Two typical DAA arrangementsare shown: one for a split ±5 or ±12volt design and one for a single 5 volt design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one for a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039/48 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontrollers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the Serial mode, as explained in the datasheet pin description.In most applications the controller will monitorthe serialdata for commands from the DTE and the receiveddata for break signals from the far end modem. I n thisway, commands to the modem are sent over the sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.C9.1 m=+ C622 m= C1390 pFCA >-D-4-='----1CB K.f+=',....--iCC K.f~--Ico >-D-~.!.-.4CF K.f-+-"-'-'----tViRALEcsSSIK-SERIESLOWPOWERFAMILYRXABABBOA00DBU5, U6MC145406RESETTXA L..L-lI-...J\AlI/'----

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing at the transformer, making the transmitsignal Common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This circuit(Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a Single 5 volt supply. BecauseDTMF tones utilize a higher amplitude than data, thesesignals will clip if a single-ended drive approach isused. The bridged driver uses an extra op-amp (U1 A)to invert the signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-amp then supplies half the drivesignal to the transformer. The receive amplifier (U1 C)picks off its signal at the junction of the impedancematching resistor and the transformer. Because thebottom leg of the transformer is being driven in onedirection by U1A and the resistor is driven in theopposite direction at the same time by U1 B, the junctionof the transformer and resistor remains relativelyconstant and the receive signal is unaffected.DESIGN CONSIDERATIONSSilicon Systems' 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.ICl390pFR437.4K 1%C30.1 rtF~t-----+--_____ ---1RING ~------------------------~FIGURE 2: Single 5V Hybrid Version3-223

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemUnlike digital logic circuitry, modem designs mustproperly contend with precise frequency tolerancesand very low level analog signals, to ensure acceptableperformance. Using good analog circuit design practiceswill generally result in a sound design. Followingare additional recommendations which should betaken into consideration when starting new designs.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a Parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01 % accuracy.In order for a Parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LAYOUT CONSIDERATIONSGood analogldigital design rules must be used tocontrol system noise in orderto obtain highest performancein modem deSigns. The more digital circuitrypresent on the PC board, the more this attention tonoise control is needed. The modem should be treatedas a high impedance analog device. A 22 mF electrolytiCcapacitor in parallel with a 0.1 mF ceramic capaCitorbetween VDD and GND is recommended.Liberal use of ground planes and larger traces onpower and ground are also highly favored. High speeddigital circuits tend to generate a significant amount ofEMI (Electro-Magnetic Interference) which must beminimized in order to meet regulatory agency limitations.To accomplish this, high speed digital devicesshould be locally bypassed, and the telephone lineinterface and K-Series device should be located closeto each other near the area of the board where thephone line connection is accessed. To avoid problems,power supply and ground traces should berouted separately to the analog and digital functions onthe board, and digital signals should not be routed nearlow level or high impedance analog traces. The analogand digital grounds should only connect at one pointnear the K-Series device ground pin to avoid groundloops. The K-Series modem IC's should have bothhigh frequency and low frequency bypassing as closeto the package as possible.MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line Simulator, operatingunder computer control. All tests were run fullduplex,using a Concord Data Systems 224 as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and all signal-to-noise (SIN) ratios reflecttotal power measurements similar to the CCITT V.56measurement specification. The individual tests aredefined as follows.BER vs. SINThis test measures the ability of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a DPSK modem will exhibitbetter BER-performance test curves receiving in thelow band than in the high band.BER vs. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamicrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels. The width of the "bowl"ofthese curves, taken atthe BER point, is the measureof dynamic range.3-224

SSI73K322LCCITT V.23, V.22, V.21Single-Chip Modem*SSI 73K322LBER vs PHASE JITTER10- 2 r-HIGH BAND RECEIVEI DPSK OPERATION10- 2SSI73K322LBER vs CARRIER OFFSETI HIGH BAND RECEIVE ~L DPSK OPERATION10-310- 310-4 I-- t:! 3002".SdBSlNI--I\.. V)-' Ie---'V~ ~ v 10-\ ~ SII C210.8dB SIN r t---I--/'10- 410-5I C211.3cBSfN I300211.8dB SINl-I-- tr I---"l-I-- pc-1\\ V --~.....-- l- vI10- 6 0 4 8 12 16 20 2410- 6 128 4 0 -4 -8 -12PHASE JITTER (0 PEAK)CARRIER OFFSET (HZ)*SS173K322LBER vs SIN (V.23 ONLY)10- 2 \1 V.23 OPERATION IJ. \ \-40dBM.A'\1\M-~o~;1\~\ \L.--1'3002 Ea. OFF t--10- 3 IW \ \I3002 EO. ON l-10-4H FLAT Ea. OFF~y~r-..... '( \\ 1\\ \I--H BACK CHANNEL I I--H FLATEO ON l-I--10-5 I ~It IK" I C21EO J~ ~ I--\1- V 1 110- 6 .\ \-2 0 2 4 6 8 10 12 14 16 18 20 22SIGNAL TO NOISE (dB)10- 210-310- 410- 510.60SSI73K322LBER vs SIGNAL TO NOISE1 V.21 OPERATION-t--40dBM\'" FLAT HIGH BAND r - -1\ \~\ C2 HIGH BANDj-- -\\ f"'"i\ \~\ ~~\ \ 3002 '" HIGH BAN 0 ~~\. '\ 1/\~ 1/\\\ 1\,\ J LOW BAND RECEIVE ~FLAT, 3002, AND C2 LINES1 2 3 4 5 6 7 8 9 10 11 12SIGNAL TO NOISE (dB)I*"EO On" Indicates bit CR1 D4 is set for additional phase equalization.3-225

SSI73K322LCCITT V.23, V.22, V.21Single-Chip Modem10-2*SS173K322BER vs RECEVE LEVEL (V.23)10-2*SS173K322LBER vs SIGNAL TO NOISE10.310-4J V.23 MAIN CHANNELI r-RECEIVE OPERATION f--C2 LINE, SiN = 9.5 dBII10-5 /\ 1'{./\...-10- 6 10 0 -10 -20 -30 -40 -5010.310-410.510-62I HIGH BAND RECEIVE ~·40dBm\ I DPSK OPERATION\ .L.\ \\\ BPS600 .\\\L BPS~~.--- I--' C2~ c\-\ \\ \'¥ H~ r C2 \' ~'t'--~Clor3002..........~r--i FLAT- r--\ \ \\\-0\ rf C1 or 3002] \'l\Sr e \l\\\ ,\ ~\I\\\ '1\ \1\ \ \ 1\ \ \\ \ \ \4 6 8 10 12 14RECEIVE LEVEL (dB)SIGNAL TO NOISE (dB)10.2*SS173K322BER vs RECEVE LEVELJ HIGH BAND RECEIVE ~DPSK OPERATIONI C2 LINE10-310-4\SIN -11.3dB10-5IS/N-15dB10-610 0 -10 -20 -30 -40 -50RECEIVE LEVEL (dBm)* "EQ On" Indicates bit CR1 D4 is set for additional phase equalization_3-226

SSI73K322LCCITT V.23, V.22, V.21Single-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)GNDXTL1A1RDRXAVREFRESETISETRXCLKRXDTXDEXCLKTXCLKINTCLKXTL1XTL2ADOAD1AD2AD3AD4ADSADSAD7ALEWRGNDRXAVREFRESETISETRXCLKRXDTXDCSEXCLKTXCLKINTTXA,! PlCC PINOUTS238 ARE THE SAME AS 224 3 2 1 28 27 265('256 n 249 J THE 28-PIN DIP 21100 2011 rl 19IVDDTXARDVDD12 13 14 15 16 17 18400-Mil22-Pin DIP600-Mil28-Pin DIP28-PinPLCCCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONORDER NO.PKG.MARKSSI 73K322L with Parallel Bus Interface28-Pin 5V SupplyPlastic Dual-In-LinePlastic Leaded Chip CarrierSSI 73K322L with Serial Interface22-Pin 5V SupplyPlastic Dual-In-Line73K322L-IP73K322L-IH73K322SL -I P73K322L-IP73K322L-IH73K322SL-IPNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69140194 - rev.3-227Protected by the following Patents (4,691,172) (4,777.453)©1989 Silicon Systems, Inc.

Notes:3-228

SSI73K324LCCITT V.22bis, V.22, V.21, V.23, Bell 212ASingle-Chip ModemApril 1994DESCRIPTIONThe 881 73K324L is a highly integrated single-chipmodem IC which provides the functions needed todesign a Quad-mode CCITT and Bell 212A compatiblemodem capable of operation over dial-up lines. The881 73K324L adds V.23 capability to the CCITTmodes of Silicon Systems' 73K224 one-chip modem,allowing a one-chip implementation in designs intendedfor European marKets which require this addedModulation mode. The 881 73K324L offers excellentperformance and a high level of functional integrationin a single IC. The device supports V.22bis, V.22, Bell212A, V.21, and V.23 operating modes, allowing bothsynchronous and asynchronous operation as definedby the appropriate standard.The 881 73K324L is designed to appear to theSystems Engineer as a microprocessor peripheral,and will easily interface with popular one-chipmicrocontrollers (80C51 typical) for control of modemfunctions through its 8-bit multiplexed address/databus. A serial control bus is available for applications notrequiring a parallel interface. An optional package withonly the serial control bus is also available. Datacommunications occurs through a separate serial port.(Continued)FEATURESOne chip Multi-mode CCITT V.22bis, V.22, V.21,V.23 and Bell 212A compatible modem data pumpFSK (75, 300, 1200 bit/s), DPSK (600, 1200 bitls),or QAM (2400 bitls) encodingPin and software compatible with otherSSI K-Series family one-chip modemsInterfaces directly with standard microprocessors(8048, 80C51 typical)Serial and parallel microprocessor bus for controlSelectable asynch/synch with internal bufferldebuffer and scrambler/descrambler functionsAll synchronous (internal, external, slave) andAsynchronous Operating modesAdaptive equalization for optimum performanceover all linesProgrammable transmit attenuation (16 dB, 1 dBsteps), and selectable receive boost (+18 dB)Call progress, carrier, answer tone, unscrambledmark, S1, and signal quality monitorsDTMF, answer, calling, SeT and guard tonegeneratorsTest modes available: ALB, DL, RDL; Mark, Spaceand Alternating bit pattern generatorsCMOS technology for low power consumption4-wire full duplex operation in all modesIBLOCK DIAGRAM8· BITmpBUSVF0494 - rev.3-229CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDESCRIPTION (Continued)The SSI 73K324L offers full hardware and softwarecompatibility with other products in Silicon Systems'K-Series family of single-chip modems, allowing systemupgrades with a single component change. TheSSI 73K324L is ideal for use in free-standing or integralsystem modem products where full-duplex 2400 bit/soperation with Alternate mode capability is required. Itshigh functionality, low power consumption, and efficientpackaging simplify design requirements andincrease system reliability. A complete modemrequires only the addition of the phone line interface, acontrol microprocessor, and RS-232 level convertersfor a typical system.The SSI 73K324L is designed to provide a completeV.22bis, V.22, Bell 212A, V.21, and V.23 compatiblemodem on a chip. Many functions were included tosimplify implementation in typical modem designs. Inaddition to the basic 2400 bitls QAM, 1200/600 bitlsDPSK and 1200/300/75 bitls FSK modulator/demodulatorsections, the device also includes synch/asynchbuffering, DTMF, answer, soft carrier, guard, and callingtone generator capabilities. Handshake patterndetectors simplify control of connect sequences, andprecise tone detectors allow accurate detection of callprogress, answer, calling, and soft carrier turn off tones.All Operating modes defined by the incorporated standardsare included, and Test modes are provided. Mostfunctions are selectable as options, and logical defaultsare provided. The device can be directly interfacedto a microprocessor via its 8-bit multiplexedaddress/data bus for control and status monitoring.Data communications takes place through a separateserial port. Data may also be sent and received throughthe control registers. This simplifies designs requiringspeed buffering, error control and compression.FUNCTIONAL DESCRIPTIONQAM MODULATOR/DEMODULATORThe SSI 73K324L encodes incoming data into quadbitsrepresented by 16 possible signal points withspecific phase and amplitude levels. The basebandsignal is then filtered to reduce intersymbol interferenceon the band limited telephone network. Themodulator transmits this encoded data using either a1200 Hz (Originate mode) or 2400 Hz (Answer mode)carrier. The demodulator, although more complex,essentially reverses this procedure while also recoveringthe data clock from the incoming signal. Adaptiveequalization corrects for varying line conditions byautomatically changing filter parameters to compensatefor line characteristics.DPSK MODULATOR/DEMODULATORThe SSI 73K324L modulates a serial bit stream intodi-bit pairs that are represented by four possible phaseshifts as prescribed by the Bell 212A1V.22 standards.The baseband signal is then filtered to reduce intersymbolinterference on the band limited 2-wire PSTNline. Transmission occurs on either a 1200 Hz (Originatemode) or 2400 Hz carrier (Answer mode).Demodulation is the reverse of the modulation process,with the incoming analog signal eventually decodedinto di-bits and converted back to a serial bitstream. The demodulator also recovers the clockwhich was encoded into the analog signal duringmodulation. Demodulation occurs using either a1200 Hz carrier (Answer mode or ALB Originate mode)or a 2400 Hz carrier (Originate mode or ALB Answermode). The SSI 73K324L use a phase locked loopcoherent demodulation technique that offers excellentperformance. Adaptive equalization is also used inDPSK modes for optimium operation with varyinglines.FSK MODULATOR/DEMODULATORThe FSK modulator/demodulator produces a frequencymodulated analog output signal using twodiscrete freqLJencies to represent the binary data. V.21frequencies of 980 and 1180 Hz (originate mark andspace), or 1650 and 1850 Hz (answer mark and space)are used in V.21 mode. V. 23 mode uses 1300 and2100 Hz forthe main channel or 390 and 450 Hz fortheback channel. Demodulation involves detecting thereceived frequencies and decoding them into theappropriate binary value. The rate converter andscrambler/descrambler are automatically bypassed inthe FSK modes.PASSBAND FILTERS AND EQUALIZERSHigh and low band filters are included to shape theamplitude and phase response of the transmit andreceive signals and to provide compromise delayequalization as well as rejection of out-of-band signals.The transmit signal filtering corresponds to a -v75%raised cosine frequency response characteristic.3-230

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemASYNCHRONOUS MODEThe Asynchronous mode is used for communicationwith asynchronous terminals which may transfer dataat 600, 1200, or 2400 bitls + 1 %, -2.5% even though themodem's output is limited to the nominal bit rate ±.01%in DPSK and QAM modes. When transmitting in thismode the serial data on the TxD input is passedthrough a rate converter which inserts or deletes stopbits in the serial bit stream in order to output a signalthat is the nominal bit rate ±.01%. This signal is thenrouted to a data scrambler and into the analog modulatorwhere di-bit or quad-bit encoding results in theoutput signal. Both the rate converter and scramblercan be bypassed for handshaking and synchronousoperation as selected. Received data is processed ina similar fashion except that the rate converter nowacts to reinsert any deleted stop bits and output data tothe terminal at no greater than the bit rate plus 1 %. Anincoming break signal (low through two characters) willbe recognized and passed through without incorrectlyinserting a stop bit.The SYNC/ASYNC converter has an extendedOverspeed mode which allows selection of an outputspeed range of either +1% or +2.3%. In the extendedOverspeed mode, some stop bits are output at 7/8 thenormal width.Both the SYNC/ASYNC rate converter and the datadescrambler are automatically bypassed in the FSKmodes.SYNCHRONOUS MODESynchronous operation is possible only in the QAM orDPSK modes. Operation is similar to that of the Asynchronousmode except that data must be synchronizedto a clock and no variation in data transfer rate isallowable. Serial input data appearing at TXD must bevalid on the rising edge of TXCLK.TXCLK is an internally derived 1200 or 2400 Hz Signalin Internal mode and is connected internally to theRXCLK pin in Slave mode. Receive data at the RXD pinis clocked out on the falling edge of RXCLK. Theasynchlsynch converter is bypassed when Synchronousmode is selected and data is transmitted out atessentially the same rate as it is input.PARALLEL CONTROL INTERFACEEight 8-bit registers are provided for control, optionselect, and status monitoring. These registers areaddressed with the ADO, AD1, and AD2 multiplexedaddress lines (latched by ALE) and appear to a controlmicroprocessor as seven consecutive memory locations.Six contol registers are read/write. The detectand ID registers are read only and cannot be modifiedexcept by modem response to monitored parameters.SERIAL CONTROL INT,ERFACEThe Serial Command mode allows access to theSSI 73K324L control and status registers via a serial 3control port. In this mode the AO, A 1, and A2 linesprovide register addresses for data passed through theDATA pin under control of the RD and WR lines. A readoperation is initiated when the RD line istaken low. Thenext eight cycles of EXCLK will then transfer out eightbits of the selected addresss location LSB first. A writetakes place by shifting in eight bits of data LSB first foreight consectuive cycles of EXCLK. WR is then pulsedlow and data transfer into the selected register occurson the riSing edge of WR.TONE GENERATORThe DTMF generator controls the sending of the sixteenstandard DTM F tone pairs. The tone pair sent isdetermined by selecting TRANSMIT DTMF (bit D4)and the 4 DTMF bits (DO-D3) of the TONE register.Transmission of DTMF tones from TXA is gated by theTRANSMIT ENABLE bit of eRO (bit D1) as with allother analog signals.FULL DUPLEX OPERATIONFour-wire full duplex operation is allowed in all modes.This feature allows transmission and reception in thesame band for four wire applications only.3-231

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemPIN DESCRIPTIONPOWERNAME TYPE DESCRIPTIONGND I System Ground.VDD I Power supply input, 5V -5% + 10%. Bypass with 0.22 IJ,F and 22 IJ,F capacitorsto GND.VREF 0 An internally generated reference voltage. Bypass with 0.22 IJ,F capacitor toGND.ISET I Chip current reference. Sets bias current for op-amps. The chip current is setby connecting this pin to VDD through a 2 MQ resistor. Iset should be bypass~dto GND with a 0.22 IlF capacitor.PARALLEL MICROPROCESSOR INTERFACEALE I Address latch enable. The falling edge of ALE latches the address on ADO-AD2 and the chip select on CS.ADO- I/O / Address/data bus.These bidirectional tri-state multi-plexed lines carry infor-AD7 Tristate mation to and from the internal registers.CS I Chip select. A low on this pin allows a read cycle or a write cycle to occur. ADO-AD7 will not be driven and no registers will be written if CS (latched) is notactive. CS is latched on the falling edge of ALE.ClK 0 Output clock. This pin is selectable under processor control to be either thecrystal frequency (for use as a processor clock) or 16 x the data rate for useas a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystalfrequency on reset.INT 0 Interrupt. This open drain weak pullup, output signal is used to inform theprocessor that a detect flag has occurred. The processor must then read thedetect register to determine which detect triggered the interrupt. INT will stayactive until the processor reads the detect register or does a full reset.RD I Read. A low requests a read of the SSI 73K324l internal registers. Datacannot be output unless both RD and the latched CS are active or low.RESET I Reset. An active high signal on this pin will put the chip into an inactive state.All control register bits (CRO, CR1, CR2, CR3, Tone) will be reset. The outputof the ClK pin will be set to the crystal frequency. An internal pull down resistorpermits power on reset using a capacitor to VDD.WR I Write. A low on this informs the SSI73K324l that data is available on ADO-AD7for writing into an internal register. Data is latched o..!!1he rising edge of WR.No data is written unless both WR and the latched CS are low.Note: The Serial Control mode is provided in the parallel versions by tying ALE high and CS low. In thisconfiguration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2, respectively.3-232

SSI73K324LCCITI V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemRS-232 INTERFACENAMETYPEEXCLKIRXCLKOfTristateRXD 0TXCLKOfTristateTXDIANALOG INTERFACERXAITXA 0XTL1IXTL2I/ODESCRIPTIONExternal Clock. This signal is used in synchronous transmission when theexternal timing option has been selected. In the External Timing mode therising edge of EXCLK is used to strobe synchronous transmit data availableon the TXD pin. Also used for serial control interface.Receive Clock Tri-statable. The falling edge of this clock output is coincidentwith the transitions in the serial received DPSK/QAM data output. The risingedge of RXCLK can be used to latch the valid output data. RXCLK will be validas long as a carrier is present. In V.23 orV.21 mode a clock which is 16 x 1200/75 or 16 x 300 Hz data rate is output, respectively.Received Data Output. Serial receive data is available on this pin. The data isalways valid on the rising edge of RXCLK when in Synchronous mode. RXDwill output constant marks if no carrier is detected.Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAMtransmission to latch serial input data on the TXD pin. Data must be providedso that valid data is available on the rising edge of the TXCLK. The transmitclock is derived from different sources depending upon the Synchronizationmode selection. In Internal Mode the clock is generated internally (2400 Hz forQAM, 1200 Hz for DPSK or 600 Hz for half-speed DPSK). In External ModeTXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phaselocked to the RXCLK pin. TXCLK is always active. In V.23 or V.21 mode theoutput is a 16 x 1200/75 or 16 x 300 Hz clock, respectively.Transmit Data Input. Serial data for transmission is input on this pin. InSynchronous modes, the data must be valid on the rising edge of the TXCLKclock. In Asynchronous modes (2400/1200/600 bit/s, or 75/300 baud) noclocking is necessary. DPSK/QAM data must be +1%, -2.5% or +2.3%, -2.5% in Extended Overspeed mode.Received modulated analog signal input from the phone line.- . .-Transmit analog output to the phone line.These pins are forthe internal crystal oscillator requiring a 11.0592 MHzParallel mode crystal. Two capacitors from these pins to ground are alsorequired for proper crystal operation. Consult crystal manufacturer for propervalues. XTL2 can also be driven from an external clock.I3-233

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemPIN DESCRIPTION (continued)SERIAL MICROPROCESSOR INTERFACENAME TYPE DESCRIPTIONAO-A2 I Register Address Selection. These lines carry register addresses and shouldbe valid during any read or write operation.DATA 1/0 Serial Control Data. Data for a readlwrite operation is clocked in or out on thefalling edge of the EXCLK pin. The direction of data flow is controlled by theRD pin. RD low outputs data. RD high inputs data.RD I Read. A low on this input informs the SSI 73K324L that data or statusinformation is being read by the processor. The falling edge of the RD signalwill initiate a read from the addressed register. The RD signal must continuefor eight falling edges of EXCLK in order to read all eight bits of the referencedregister. Read data is provided LSB first. Data will not be output unless the RDsignal is active.WR I Wrtte. A low on this input informs the SSI73K324L that data or status informationhas been shifted in through the DATA pin and is available for writing to an internalregister. The normal procedure for a wrtte is to shift in data LSB first on the DATApin for eight consecutive falling edges of EXCLK and then to pulse WR low. Datais wrttten on the rising edge of WR.Note: In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the pins;AO, A1, A2, DATA, and EXCLK. Also, the RD and WR controls are used differently.3-234

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemREGISTER DESCRIPTIONSEight 8-bit internal registers are accessible for controland status monitoring. The registers are accessed inread or write operations by addressing the AO, A1 andA2 address lines in Serial mode, orthe ADO, AD1 andAD2 lines in Parallel mode. The address lines arelatched by ALE. Register CRO controls the method bywhich data is transferred over the phone line. CR1controls the interface between the microprocessor andthe SSI 73K324L internal state. DR is a detect registerwhich provides an indication of monitored modemstatus conditions. TR, the tone control register, controlsthe DTMF generator, answer, guard tones, SCT,calling tone, and RXD output gate used in the modeminitial connect sequence. CR2 is the primary DSPcontrol interface and CR3 controls transmit attenuationand receive gain adjustments. All registers are read/write except for DR and 10 which are read only.Register control and status bits are identified below:REGISTER BIT SUMMARYCONTROL MODULATION MODULATIONREGISTER CRO 000MODULATIONTYPETYPEOPTIONa1 aCONTROL TRANSMIT TRANSMIT ENABLEREGISTER CR1 001 PATTERN PATTERN DETECT1 1 a INTERRUPTDETECT RECEIVE PATTERN RECEIVEREGISTER DR 010LEVEL S1 DET DATATRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER!MODE MODE MODEENABLE ORIGINATE2 1 aBYPASSSCRAMBLER! CLKTESTTESTADD PH. EQ. CONTROLRESET MODE MODE(V.23)1 0UNSCR. SPECIAL CALLCARRIERSIGNALMARKTONE PROGRESSDETECT DETECT QUAUTYDETECTDETECTITRANSMITTONERXDTRANSMITGUARDTONEICONTROL TR all OUTPUT ANSWERSCT/CALUNGREGISTERCONTROLTONETONETRANSMIT DTMF21 DTMFllDTMF3DTMF4WIRE FOX OVERSPEEDDTMFO/GUARDIANSWER!CALUNG/SCTCONTROLSPECIALREGISTER CR2 100 REGISTER2 ACCESSCALLINITlAUZETRANSMIT RESET TRAIN EQUALIZERSl16 WAYDSP INHIBIT ENABLECONTROLREGISTER CR3 101 TXDALT3TRISTATETX/RXCLKRECEIVE TRANSMIT TRANSMIT TRANSMIT TRANSMITGAIN ATTEN. ATTEN. ATTEN. ATTEN.BOOST 3 2 1 0SPECIALREGISTER SR 101 TX BAUD RX UNSCR.CLOCKDATAIDREGISTER 10 110 10 IDNOTE:When a register containing reserved controlbits is written into, the reserved bits must beprogrammed as O's.3-235

SSI73K324LCCllT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemREGISTER ADDRESS TABLEOAM: 0=2400 BmsDPSK: 0=1200 Bmsl:j100BmSFSK: 0=V.23bV.21~~~~::~~HN ----------'0010=EXT SYNCH0011 =SLAVE SYNCH0100=ASYCH 8 BfTSICHAR010bASYCH 9 BfTSICHAR0110=ASYCH 10 BITSICHAR011bASYCH 11 BITSICHARlXOO=FSKO=DISABLE O=ANSWERTXA OUTPUT bORIGINATE1 =ENABLE in V.23TXA OUTPUT O=BC xmilhMCxmitGUARD: 0·1800 HZ1·550 HZANS WER: 0 . 2225 HZ1 ·2100 HZCALLING: 0·1300 HZSCT' 1 ·900 HZO=ACCESS CRa O=DSP IN O=NORMAL O=RX= TX O=DSPbACCESS DEMOD MODE DOTTING 1=RX=16 WAY INACTIVESPECIAL 1 =DSP IN CALL 1=S 1bDSPREGISTER PROGRESSACTIVEMODEO=ADAPTEOACTIVEl=ADAPT EOFROZENO=ADAPTEOIN INiT1=ADAPT EOOK TO ADAPT00XX=73K212L,322L, 321 L01XX=73K221L,302L1 OXX= 73K222L1100=73K224L1110=73K324L1101=73K312L3-236

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemCONTROL REGISTER 0D7D6CRO MODUL. MODUL.000 OPTION TYPE 1D5MODUL.TYPE 0D4 D3 D2 D1 DOTRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/MODE 2 MODE 1 MODEO ENABLE ORIGINATEBIT NO.DOD1NAMEAnswer/OriginateTransmitEnableD5, D4, TransmitD3,D2 ModeCONDITIONDESCRIPTION0 Selects Answer mode (transmit in high band, receive inlow band) or in V.23 HDX mode, receive at 1200 bitlsand transmit at 75 bit/so1 Selects Originate mode (transmit in low band,receivein high band) or in V.23 HDX mode, receive at 75 bitlsand transmit at 1200 bit/soNote: This bit works with Tone Register bits DO and D6to program special tones detected in the Detect Register.See Detect and Tone Registers.0 Disables transmit output at TXA.1 Enables transmit output at TXA.D5 D4 D3 D2Note: Transmit Enable must be set to 1 to allowactivation of Answer Tone, DTMF, or Carrier.0 0 0 0 Selects Power Down mode. All functions disabledexcept digital interface.0 0 0 1 Internal Synchronous mode. In this mode TXCLK is aninternally derived 600, 1200 or 2400 Hz signal. Serialinput data appearing at TXD must be valid on the risingedge of TXCLK. Receive data is clocked out of RXD onthe falling edge of RXCLK.0 0 1 0 External Synchronous mode. Operation is identical tointernal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 600, 1200 or 2400 Hz clockmust be supplied externally.0 0 1 1 Slave Synchronous mode. Same operation as otherSynchronous modes. TXCLK is connected internally tothe RXCLK pin in this mode.0 1 0 0 Selects Asynchronous mode - 8 bits/character (1 startbit, 6 data bits, 1 stop bit).- --0 1 0 1 Selects Asynchronous mode - 9 bits/character (1 start--_ ..-bit, 7 data bits, 1 stop bit).0 1 1 0 Selects Asynchronous mode -1 0 bits/character (1 startbit, 8 data bits, 1 stop bit).-----0 1 1 1 Selects Asynchronous mode - 11 bits/character (1 startbit, 8 data bits, Parity and/or 1 or 2 stop bits).1 X 0 0 Selects FSK operation.3-237I

SSI73K324LCCITI V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemCONTROL REGISTER 0 (Continued)SIT NO. NAME CONDITION DESCRIPTIOND6 D5D6,D5 Modulation 1 0 QAMType 0 0 DPSK0 1 FSKD7 Modulation 0 QAM selects 2400 bit/s. DPSK selects 1200 biVs.Option FSK selects V.23 mode.- -----1 DPSK selects 600 biVs.FSK selects V.21 mode.CONTROL REGISTER 1D7 D6 D5 D4 D3 D2 D1 DOTRANSMIT TRANSMIT ENABLE BYPASS ClK TEST TESTCR1 PATIERN PATIERN DETECT SCRAMBI CONTROL RESET MODE MODE001 1 0 INT. ADD PH.EQ 1 0SIT NO. NAME CONDITION DESCRIPTIOND1 DOD1,DO Test Mode 0 0 Selects Normal Operating mode.0 1 Analog loopback mode. loops the transmitted analogsignal back to the receiver, and causes the receiver touse the same carrier frequency as the transmitter. Tosquelch the TXA pin, transmit enable bit must be low.Tone Register bit D2 must be zero.1 0 Selects remote digitalloopback. Received data is loopedback to transmit data internally, and RXD is forced to amark. Data on TXD is ignored.1 1 Selects local digitalloopback. Internally loops TXD backto RXD and continues to transmit data_carrrier at TXA pin.D2 Reset 0 Selects normal operation.1 Resets modem to power down state. All control registerbits (CRO, CR1, CR2, CR3 and Tone) are reset to zeroexcept CR3 bit D2. The output of the clock pin will be setto the crystal frequency.--D3 ClK Control 0 Selects 11.0592 MHz crystal echo output at ClK pin.(Clock Control) 1 Selects 16 X the data rate output at ClK pin in QAM andDPSK only.3-238

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemCONTROL REGISTER 1 (Continued)07 06TRANSMIT TRANSMITCR1 PATTERN PATTERN001 1 005 04 03 02 01 DOENABLE BYPASS ClK TEST TESTDETECT SCRAMB/ CONTROL RESET MODE MODEINT. ADD PH.EO. 1 0BIT NO. NAME CONDITION DESCRIPTION04 Bypass 0 Selects normal operation. OPSK and OAM data isScrambler/passed through scrambler.Add Ph. Eq. 1 Selects Scrambler Bypass. OPSK and OAM data isrouted around scrambler in the transmit path. In the V.23mode, additional phase equalization is added to the mainchannel filters when 04 is set to 1.05 Enable Detect 0 Disables interrupt at INT pin. All interrupts are normallyInterruptdisabled in Power Down mode.1 Enables INT output. An interrupt will be generated with achange in status of DR bits 01-04 and 06. The answertone and call progress detect interrupts are maskedwhen the TX enable bit is set. Carrier detect is maskedwhen TX OTM F is activated. All interrupts will be disabledif the device is in Power Down mode.07 0607,06 Transmit 0 0 Selects normal data transmission as controlled by thePatternstate of the TXO pin.0 1 Selects an alternating mark/space transmit pattern formodem testing and handshaking. Also used for S1 patterngeneration. See CR2 bit 04.1 0 Selects a constant mark transmit pattern.1 1 Selects a constant space transmit pattern.I3-239

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDETECT REGISTERD7 D6 D5 D4 D3 D2 D1 DODR RECEIVE S1 RECEIVE UNSCR. CARRIER SPECIAL CALL SIGNAL010 LEVEL PATTERN DATA MARK DETECT TONE PROG. QUALITYINDICATOR DETECT DETECT DETECT DETECT INDICATORBIT NO. NAME CONDITION DESCRIPTIONDO Signal Quality 0 Indicates normal received signal.Indicator 1 Indicates low received signal quality (above average errorrate). Interacts with Special Register SQ bits D2, D1.D1 Call Progress 0 No call progress tone detected.Detect 1 Indicates presence of call progress tones. The callprogress detection circuitry is activated by energy in thenormal 350 to 620 Hz call progress band.D2 Special Tone 0 Condition not detectedDetect 1 Condition detectedCRO DO TR DO CR205---------1 0 1 2225 Hz ±10 Hz answer tone detected in V.22bis, V.22,V.21 modes.1 1 1 2100 Hz ±21 Hz answer tone detected in V.22bis, V.22,V.21 modes.0 X 0 900 Hz SCT tone detected in V.23 mode.I X 0 2100 Hz or 2225 Hz answer tone detected in QAM, DPSK,or V.21 Mode.D3 Carrier Detect 0 No carrier detected in the receive channel.1 Indicated carrier has been detected in the receivedchannel. Should be time qualified by software.D4 Unscr. Mark 0 No unscrambled mark being received.Detect1 Indicates detection of unscrambled marks in the receiveddata. Should be time qualified by software.D5 Receive Continuously outputs the received data stream.DataThis data is the same as that output on the RXD pin, but itis not disabled when RXD is tri-stated.-------D6 S1 Pattern 0 No S1 pattern being received.Detect1 S1 pattern detected. Should be time qualified by software.S1 is an unscrambled double dibit (11001100...) sent inDPSK 1200 bitls mode. Generated pattern must be properlyaligned to transmitter qaud clock_!O be detected.D7 Receive Level 0 Received signal level below threshold,Indicator(== -25 dBmO);can use receive gain boost (+18 dB.)1 Received signal above threshold.3-240

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemTONE REGISTER07 06RXD TRANSMITTR OUTPUT GUARDI011 CONTR. CALLING/SCTTONE05 04 03 02 01 DOTRANSMIT TRANSMIT DTMF 21 OTMF 11 OTMF 01ANSWER OTMF OTMF 3 WIRE OVER- G.T.lANSW.ITONE FOX SPEED CALLING/SCTTONE/SELSIT NO.NAME00,04, DTMF 0105,06 Guard TonelAnswer TonelCailing/SCTTonelTransmitSelectD102OTMF 11OverspeedDTMF 214WIREFOXCONDITIONDESCRIPTION06 05 D4 DO DO interacts with bits 06, D5, 04, and CRO as shown.X X 1 X Transmit DTMF tones (overides all other functions).1 0 0 0 Select 1800 Hz guard tone if in V.22bis or V.22 andAnswer mode in CRO.1 0 0 1 Select 550 Hz guard tone if in V.22bis or V.22 andAnswer mode in CRO.Note: Bit DO also selects the answer tone detected in Originate mode, seeDetect Register Special Tone Detect (bit 02) for details.1 0 0 0 1300 Hz calling tone will be transmittted if V.21, V.22,V.22bis or V.23 Originate mode is selected in CRO.X 1 0 0 Transmit 2225 Hz Answer Tone. Must be in OPSKAnswer mode.X 1 0 1 Transmit 2100 Hz Answer Tone. Must be in OPSKAnswer mode.1 0 0 1 900 Hz SCT (soft carrier turnoff) tone transmitted inV.23 75 bitls Receive mode. (CRO bit DO = 1).04 01 01 interacts with 04 as shown.0 0 Asynchronous OAM/OPSK +1% -2.5%. (Normal).0 1 Asynchronous OAM/OPSK, 2400, 1200 or 600 bitls+2.3% -2.5%. (Extended overspeed).04 020 0 Selects 2-wire full-duplex or half-duplex.0 1 02 selects 4 wire full duplex in the Modulation modeselected. The receive path corresponds to the ANSIORIG bit CRO DO in terms of high or low band selection.The transmitter is in the same band as the receiver, butdoes not have magnitude filtering or equalization on itssignal as in the receive path.INote: DTMFO - DTM F2 should be set to an appropriate state after DTM F dialing to avoid unintended operation.3-241

SSI73K324LCCITI V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemTONE REGISTER (Continued)07 06 05 04 03 02 01 DORXO TRANSMIT TRANSMIT TRANSMIT OTMF 21 OTMF 11 DTMF 0/TR OUTPUT GUARD/ ANSWER OTMF DTMF3 WIRE OVER- GUARD/011 CONTR. CALLING/SCT TONE FOX SPEED CALLING/SCTTONETONE SELBIT NO. NAME CONDITION DESCRIPTION03,02, DTMF 3, 04 = 1 Programs 1 of 16 DTMF tone pairs that will be01, DO 2,1,0 transmitted when TX DTM F and TX enable bit (CRO, bit01) is set. Tone encoding is shown below:KEYBOARD DTMF CODE TONESEQUIVALENT 03 02 01 DO LOW HIGH1 0 0 0 1 697 12092 0 0 1 0 697 13363 0 0 1 1 697 14774 0 1 0 0 770 12095 0 1 0 1 770 13366 0 1 1 0 770 1477-----7 0 1 1 1 852 12098 1 0 0 0 852 13369 1 0 0 1 852 1477----0 1 0 1 0 941 1336* 1 0 1 1 941 1209# 1 1 0 0 941 1477A 1 1 0 1 697 1633B 1 1 1 0 770 1633C 1 1 1 1 852 16330 0 0 0 0 941 163307 RXO Output 0 Enables RXD pin. Receive data will be output onControlRXD.1 Disables RXD pin.The RXD pin reverts to a highimpedance with internal weak pull-up resistor.3-242

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemCONTROL REGISTER 207 06CR2SPEC100 0 REGACCESS05CALLINIT04 03 02 D1 DOTRANSMIT TRAIN EQUALIZERS1 16 WAY RESET INHIBIT ENABLEOSPBIT NO.DONAMEEqualizerEnable01 TrainInhibit02 RESET OSP03 16 Way04 TransmitS105 Cailinit06 SpecialRegisterAccess07 N/ACONDITIONDESCRIPTION0 The adaptive equalizer is in its initialized state.1 The adaptive equalizer is enabled. This bit is used inhandshakes to control when the equalizer shouldcalculate its coefficients.0 The adaptive equalizer is active.1 The adaptive equalizer coefficients are frozen.0 The OSP is inactive and all variables are initialized.1 The OSP is running based on the mode set by othercontrol bits0 The receiver and transmitter are using the same decisionplane (based on the Modulator Control Mode).1 The receiver, independent of the transmitter, is forcedinto a 16 point decision plane. Used for QAM handshaking.0 The transmitterwhen placed in alternating Mark/Spacemode transmits 01 01 .... scrambled or not dependenton the bypass scrambler bit and Modulation mode.1 When this bi~ is 1 and only when the transmitter isplaced in alternating Mark/Space mode by CR1 bits07, 06, an unscrambled repetitive double dibit patternof 00 and 11 at 1200 bitls (S1) is sent.0 The OSP is setup to do demodulation and patterndetection based on the Various mode bits. Both answertones are detected in Oemod Mode concurrently; TRDO is ignored.1 The OSP decodes call progress, calling tones, unscrambledmark, and 2100 Hz and 2225 Hz answertones.0 Normal CR3 access.1 Setting this bit and addressing CR3 allows access tothe SPECIAL REGISTER. See the SPECIAL REGIS-TER for details.--0 Must be 0 for normal operation.I3-243

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemCONTROL REGISTER 307 06CR3 TXOALT TRISTATE101 TXlRXCLK05 04RECEIVE0 ENABLEBOOST03 02 01 00TRANSMIT TRANSMIT TRANSMIT TRANSMITADEN. ADEN. ATTEN. ATTEN.3 2 1 0BIT NO.NAME03,02, Transmit01,00 Attenuator04 ReceiveGain Boost(18 dB)05 Not Used06 TristateTXCLKlRXCLK07 TXOALTCONDITION03 02 01 000 0 0 o -1 1 1 101001Spec. Reg. bit 03=1DESCRIPTIONSets the attenuation level of the transmitted signalin 1 dB steps. The default (03-00=0100) is for a transmitlevel of -10 dBmO. The total range is 16 dB.18 dB receive front end boost is not used.Boost is in the path. This boost does not changereference levels. It is used to extend dynamic range bycompensating for internally generated noise whenreceiving weak signals. The receive level detect signaland knowledge of the hybrid and transmit attenuatorsetting wi" determine when boost should be enabled.Not used. Only write zeros this location.TXCLK, RXCLK outputs drivenTXCLK, RXCLK outputs in Tristate modeAlternate TX data source. See Special Register.10 REGISTERSPECIAL REGISTER060503 0201SR101TXOSOURCESIGNALQUALITYLEVELSELECT1SIGNALQUALITYLEVELSELECTO06 TXBAUO CLK TXBAUO clock is the transmit baud-synchronous clock that can be used tosynchronize the input of arbitrary quad/di-bit patterns. The rising edge ofTXBAUO signals the latching of a baud-worth of data internally. Synchronousdata to be entered via the TXOAL T bit, CR3 bit 07, should have datatransitions that start 1/2 bit riod from the TXBAUO clock edges.05 RXUNOSCR This bit outputs the data received before going to the descrambler. This isOAT A useful for sending special unscrambled patterns that can be used for signaling.3-244

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemSPECIAL REGISTER (Continued)BIT NO. NAME DESCRIPTIOND3 TXD SOURCE This bit selects the transmit data source; either the TXD pin if ZERO or theTXDALTifthisbit isaONE. The TRANSMIT PATTERN bits 07 and 06 in CR1override either of these sources.D2, D1 SIGNAL The signal quality indicator is a logical zero when the signal received isOUALITY acceptable for low error rate reception. It is determined by the value of theLEVEL Mean Squared Error (MSE) calculated in the decisioning process whenSELECT compared to a given threshold. This threshold can be set to four levels of errorrate. The SOl bit will be low for good or average connections. Asthe error ratecrosses the threshold setting, the SOl bit will toggle at a 1.66 ms rate. Togglingwill continue until the error rate indicates that the data pump has lostconvergence and a retrain is required. At that point the sal bit will be a ONEconstantly. The SOl bit and threshold selection are valid for OAM and DPSKonly.TYPICALD2 D1 THRESHOLD VALUE UNITS0 0 10- 5 BER (default)0 1 10- 6 BER_.------1 0 10- 4 BER1 1 10- 3 BERNOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a ONE and addressing CR3. Thisregister provides functions to the 73K324L user that are not necessary in normal communications.Bits D7-D4 are read only, while 03-00 are read/write. To return to normal CR3 access, CR2 bit D6must be returned to a ZERO.----ID7 D6 D5 D4 D31 D2 1 D1 IDOIID ID ID ID ID110 3 2 1 0 USER DEFINABLE PERSONALITYBIT NO. NAME CONDITION DESCRIPTIOND7 D6 D5 D4 Indicates Device:D7, D6, D5, Device 0 0 X X SSI73K212Lor73K322Lor73K321LD4 Identification 0 1 X X SSI73K221Lor73K302LSignature 1 0 X X SSI73K222L1 1 0 0 SSI73K224L1 1 1 0 SSI73K324L1 1 0 1 SSI73K312L-------.-I3-245

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSPARAMETERVDD Supply VoltageStorage TemperatureSoldering Temperature (10 sec.)Applied VoltageRATING7V-65 to 150°C260°C-0.3 to VDD+0.3VNote: All inputs and outputs are protected from static charge using built-in, industry standard protectiondevices and all outputs are short-circuit protected.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITSVDD Supply voltage 4.5 5 _L 5.5 VExternal Components (Refer to Application section for placement.)VREF Bypass capacitor (VREF to GND) 0.22 ~F- --Bias setting resistor (Placed between VDDand ISET pins) 1.8 2 2.2 MQf---ISET Bypass capacitor (ISET pin to GND) 0.22 ~FVDD Bypass capacitor 1 (VDDto GND) 0.22 ~FVDD Bypass capacitor 2 (VDDto GND) 22 ~FXTL 1 Load Capacitance Depends on crystal requirements 18 39 pFXTL2 Load Capacitance Depends on crystal requirements 18 27 pFClock Variation (11.0592 MHz) Crystal or -0.01 +0.01 %external clockTA, Operating Free-Air -40 85 °CTemperature",---3-246

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDC ELECTRICAL CHARACTERISTICS(TA = -40°C to 85°C, VDD =recommended range unless otherwise noted.)PARAMETER CONDITIONS MIN NOM MAX UNITS100, Supply Current ClK = 11.0592 MHzISET Resistor = 2 MQIDD1, Active Operating with crystal oscillator. 18 25 rnAIDD2, Idle < 5 pF capacitive load on ClK pin.--_._--5 rnADigital InputsVll, Input low Voltage 0.8 V- -VIH, Input High VoltageAll Inputs except Reset 2.0 VDD VXTl1, XTl2Reset, XTl1 , XTl2 3.0 VDD VIIIH, Input High Current VI = VDD 100 ~Ill, Input low Current VI =OV -200 ~Reset PUll-down Current Reset = VDD -2 -30 -70---'--------~Digital OutputsVOH, Output High Voltage IO=IOH Min 2.4 VDD VlOUT = -0.4 rnAVOL, Output low Voltage 10 = lOUT = 1.6 rnA 0.4 VRXD Tri-State Pull-up Curr. RXD = GND -2 -50 ~CapacitanceMaximum Capacitive loadClK 25 pFI nput Capacitance All Digital Inputs 10 pF3-247

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)PARAMETERS CONDITIONS MINQAM/DPSK ModulatorCarrier Suppression Measured at TXA 35Output Amplitude TX scrambled marks -11.5ATT =0100 (default)FSK Modulator/DemodulatorOutput Freq. Error ClK = 11.0592 MHz -.31Transmit level ATT = 0100 (Default) -11.5Transmit Dotting PatternTXA Output DistortionAll products through BPFOutput Bias Distortion Dotting Pattern measured at RXD -10at RXDReceive level -20 dBm, SNR 20 dBOutput Jitter at RXD Integrated for 5 seconds -1 S.Sum of Bias Distortion and Integrated for 5 seconds -15Output Jitter at RXD2100 Hz Answer Tone GeneratorOutput Amplitude ATT = 0100 (Default level) -11.5Not in V.21 or V.23 ModeOutput DistortionDTMF GeneratorDistortion products in receive bandNot in V.21 or V.23 modeFreQ. Accuracy -0.03Output Amplitude low Band ATT =: 0100 -10OutlLut AmQlitude Hiah Band ATT = 0100 -8Twist Hiah-Band to low-Band 1.0Receiver Dynamic Range Refer to Performance Curves -43Call Prog ress DetectorIn Call Init modeDetect level 460 Hz input sigIlal -34Reject levelDelavTimeHold Time-70 dBmO to -30 dBmO STEP-30 dBmO to -70 dBmO STEPHysteresis @ 460 Hz input signal 2NOM MAX UNITSdB-10.0 f -9 dBmO------+0.20 %-10.0 -9 dBmO------45 dB+10%+15 %+15 %-10 -9 dBmO-40 dB-_._---+0.25 0/0-8 dBmO-6 dBmO2.0 3.0 dB-----3.0 dBmO0 dBmO-40 dBmO25 ms25 msdBNOTE: Parameters expressed in dBmO refer to the following definition:o dB loss in the Transmit path to the line.2 dB gain in the Receive path from the line.Refer to the Basic Box Modem diagram in the Applications section for the DAA design.3-248

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERS CONDITIONS MIN NOM MAX UNITSCarrier Detect Receive Gain Boost "On" for Lower Input Level MeasurementsThreshold OAM/DPSK or FSK receive data -48 -43--1------- -----_.-1-------dBmOHysteresis All Modes 2 dB------ -Delay Time FSK 70 dBmO to -6 dBmO 25 37----- -----1-------ms70 dBmO to -40 dBmO 25 37c----- --1---msDPSK -70 dBmO to -6 dBmO 7 17 ms--70 dBmO to -40 dBmO 7-----_.17 msOAM -70 dBmO to -6 dBmO 25--- - -----37 ms-70 dBmO to -40 dBmO 25_._------37 msHold Time FSK -6 dBmO to -70 dBmO 25 37 msSpecial Tone Detectors-40 dBmO to -70 dBmO 15 30 msDPSK -6 dBmO to -70 dBmO 20 29 ms-40 dBmO to -70 dBmO 14 21 msOAM -6 dBmO to -70 dBmO 25 32 ms-40 dBmO to -70 dBmO 8 28 ms~~-------- ---Detect Level See definitions for DO of Tone Register -48 -43-- _ .._-- - -- -----dBmODelay and Hold Time-- ------CalilNIT mode2225 or 2100 Hz 2225 ± 10 Hz 6 50 msanswer tone2100±21 Hz-----900 Hz SCT Tone Accuracy ±9 Hz 10 45 msReceive V.23 main channelr----~~~-------- --.~----Hysteresis 2----- - -- -dBPattern DetectorsDPSK ModeS1 PatternDelay Time For signals from -6 to -40 dBmO, 10 55 ms-------Hold Time Demod Mode 10 45 ms-----Unscrambled Mark-_.".-_._ .. -Delay Time For signals from -6 to -40 10 45 ms~--- -"-Hold Time Demod or call Init Mode 10-- -----_...45 msReceive Level Indicator---Detect On -22 -28 dBmOValid after Carrier Detect DPSK Mode 1 4 7 ms----I3-249

----~----~---SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERSCONDITIONSMINNOM MAX UNITSOutput Smoothing FilterOutput ImpedanceOutput LoadTXA pinTXA pin; FSK Single10200 300 0--kOTone out for THO = -50 dBin 0.3 to 3.4 kHz range50 pFMaximum TransmittedEnergy4 kHz, Guard Tones off10 kHz, Guard Tones off----1---35 dBmO-55 dBmOAnti Alias Low Pass FilterMaximum allowedOut-of-Band Signal Energy(Defines Hybrid Trans-Hybrid loss requirements)Transmit Attenuator12 kHz, Guard Tones offScrambled data at 2400 bit/s inopposite bandSinusoids out of band-65 dBmO--------_.r-14 dBm-9 dBm---Range of Transmit LevelStep AccuracyDefault ATT = 0100 (-10 dBmO)1111-0000-21-0.15-----6 dBmO+0.15 dBClock NoiseCarrier OffsetTXA pin; 153.6 kHz1.5 mVrms--~ -------Capture RangeOriginate or Answer-7±5 r~_ +7 HzRecovered ClockCapture RangeGuard Tone GeneratorTone Accuracy% of data rate originate or answer550 Hz-.02I~ +.02 %+1.2 %1800 Hz-0.8 %Tone Level550 Hz-4.5-3.0 -1.5 dB(Below QAM/DPSK Output)Harmonic Distortion(700 to 2900 Hz)1800 Hz550 or 1800 Hz-7.5-6.1 -4.5 dB----50 dB3-250

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDYNAMIC CHARACTERISTICS AND TIMING (Continued)PARAMETERS CONDITIONS MIN NOM MAX UNITSTiming (Refer to Timing Diagrams)Parallel Mode:- --TAL CS/Addr. setup before ALE Low 30---nsTLA CSI Addr. hold after ALE Low 6-- ----nsTLC ALE Low to RDIWR Low 40 nsTCL RD/WR Control to ALE High 10 nsTRD Data out from RD Low 90 nsTLL ALE width 25 ns--TRDF Data float after RD High 40 ns-TRW RDwidth 70 nsTWW WRwidth 70 nsTOW Data setup ~efore WR High 70 nsTWO Data hold after WR High 20 nsSerial Mode:---TRCK Clock high after RD 250 T1 nsTAR Address setup before RD low 0 nsTRA Address hold after RD low 350 nsTRD RD to data valid 110 ns---~----TRDF Data float after RD high 50 nsTCKDR Read data out after falling edge 300 nsof EXCLKTWW WRwidth 350 nsTAW Address setup before WR 50 ns--TWA Address hold after rising edge of WR 50 nsTCKDW Write data hold after falling edge 200 nsof EXCLKTCKW WR high after falling edge of EXCLK 330 T1& T2 ns----TDCK Data setup before falling edge 50 nsof EXCLKT1, T2 Minimum period 500 nsNote: T1 and T2 are the lowlhigh periods, respectively, of EXCLK in Serial mode.----------I3-251

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemTIMING DIAGRAMSBUS TIMING DIAGRAM (PARALLEL VERSION)~ALE ~ ~TlC I..L TRW ~ TCl .JRD -'t-+TlC 1 TWWWR-+ ~TLA TRD TRDF I TWOL TAL " J ~ ~ I.. TOW ~ .. •• 1ADO-AD?---K ADDRESS )t---K READ DATA)t---K ADDRESS )t---K WRITE DAT1--READ TIMING DIAGRAM (SERIAL VERSION)EXCLKcs ~- -4- -~- -4-I~--~------------r-AO-A2 +-----~~------------------------------ -----DATAWRITE TIMING DIAGRAM (SERIAL VERSION)EXCLKAO-A2 -----\-------------------------------------ttADATA3-252

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemAPPLICATIONS INFORMATIONGENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK-Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interface,and a DAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith Intel 8048 and 80C51 microprocessors for controland status monitoring purposes.Two typical DAAarrangements are shown: one for a split ±5 or ±12volt design and one for a single 5 volt design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one for a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039/48 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontrollers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the Serial mode, as explained in the datasheet pin description.In most applications the controllerwill monitor the serialdata for commands from the DTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent over the sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.IRS232LEVELCONVERTERSC9.1 nF+ C822nFC1390 pFCA H>-+--=:~CBKI-~~cc KI-+--=::;..-...lCD H>+-=.!-...jiNAALEcsSSIK-SERIESLOWPOWERFAMILYR45.1KR420KBABBDADDDB1.>-1---::':-"'-+---t----1f---+--+­1.>-r--,=::.=:.:----t----1f---+---RXCLKTXCLKR33.6Kus, usMC14S406VR1..r MOVV250L20R910KFIGURE 1: Basic Box Modem with Dual-Supply Hybrid3-253

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing at the transformer, making the transmitsignal Common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its useeliminates the need for a second power supply. Thiscircuit (Figure 2) uses a bridged drive to allow undistortedsignals to be sent with a single 5 volt supply.Because DTM F tones utilize a higher amplitude thandata, these signals will clip if a single-ended driveapproach is used. The bridged driver uses an extra opamp(U1A) to invert the signal coming from the gainsetting op-amp (U1 B) before sending it to the other legof the transformer. Each op-amp then supplies half thedrive Signal to the transformer. The receive amplifier(U1 C) picks off its signal at the junction of the impedancematching resistor and the transformer. Becausethe bottom leg of the transformer is being driven in onedirection by U1A and the resistor is driven in theoPPOsite direction at the same time by U1 B, the junctionof the transformer and resistor remains relativelyconstant and the receive signal is unaffected.DESIGN CONSIDERATIONSSilicon Systems' 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital bus peripherals.Cl390pFR437.4K 1%. C30.1nf'~Rl201< 1%• Note: Op-amp U1must be rated forsingle 5V operation.R2201

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemUnlike digital logic circuitry, modem designs mustproperly contend with precise frequency tolerancesand very low level analog signals, to ensure acceptableperformance. Using good analog circuit design practiceswill generally result in a sound design. Followingare additional recommendations which should betaken into consideration when starting new designs.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a Parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01% accuracy.In order for a Parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LAYOUT CONSIDERATIONSGood analogldigital design rules must be used to controlsystem noise in order to obtain highest performance inmodem designs. The more digital circuitry present onthe PC board, the more this attention to noise control isneeded. The modem should be treated as a high impedanceanalog device. A 22 mF electrolytic capacitor inparallel with a 0.22 mF ceramic capacitor between VDDand GND is recommended. Liberal use of groundplanes and larger traces on power and ground are alsohighly favored. High speed digital circuits tend to generatea significant amount of EMI (Electro-Magnetic Interference)which must be minimized in order to meetregulatory agency limitations. To accomplish this, highspeed digital devices should be locally bypassed, andthe telephone line interface and K-Series device shouldbe located close to each other near the area of the boardwhere the phone line connection is accessed. To avoidproblems, power supply and ground traces should berouted separately to the analog and digital functions onthe board, and digital signals should not be routed nearlow level or high impedance analog traces. The analogand digital grounds should only connect at one pointnear the K-Series device ground pin to avoid groundloops. The K-Series modem IC's should have both highfrequency and low frequency bypassing as close to thepackage as possible. The ISET resistor and bypasscapacitor need to be as close to device as possible.MODEM PERFORMANCECHARACTERISTICSThe curves presented here define modem IC performanceunder a variety of line conditions while inducingdisturbances that are typical of those encounteredduring data transmission on public service telephonelines. Test data was taken using an AEA Electronics'"Autotest I" modem test set and line Simulator, operatingunder computer control. All tests were run fullduplex,using a Hayes 2400 Smartmodem as thereference modem. A 511 pseudo-random-bit patternwas used for each data point. Noise was C-messageweighted and all signal-to-noise (SIN) ratios reflecttotal power measurements similar to the CCITT V.56measurement specification. The individual tests aredefined as follows.SER vs. SINThis test measures the ability of the modem to operateover noisy lines with a minimum of data-transfer errors.Since some noise is generated in the best of dial-uplines, the modem must operate with the lowest SINratio possible. Better modem performance is indicatedby test curves that are closest to the BER axis. Anarrow spread between curves representing the fourline parameters indicates minimal variation in performancewhile operating over a range of aberrant operatingconditions. Typically, a modem will exhibit betterBER-performance test curves receiving in the lowband than in the high band.SER vs. Receive LevelThis test measures the dynamic range of the modem.Because signal levels vary widely over dial-up lines,the widest possible dynamic range is desirable. Theminimum Bell specification calls for 36 dB of dynamicrange. SIN ratios are held constant at the indicatedvalues while the receive level is lowered from a veryhigh to very low signal levels. The width of the "bowl" ofthese curves, taken at the BER point, is the measure ofdynamic range.I3-255

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip Modem10-310'"SSI 73K324L BER vs SINPRELIMINARY\\ I HIGH BAND RECEIVE t\\ I -30

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip Modem551 73K324L BER vs RECEIVEPRELIMINARYIlOAM OPERATION2400BITISt551 73K324L BER vs 5/NPRELIMINARYI MAIN ~J~NEL t1200 biVs~ACK CHANNEL 75 biVsOPERATION FSK'10~-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 -0RECEIVE LEVEL (dBm)J\V\ l1\/ \ r-LL'-~10- 5 =f:=d BACK CHANNEL =~ CH~~EL =~ 75 MIs !.L 1200bitls _lY-r-r-\ \\\o 1 2 3 4 5 6 7 8 9 10 11 12SNR LEVELSI3-257

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemPACKAGE PIN DESIGNATIONS(Top View)~ 0u.w0< ~:i~~-JZCl4 3 2 28 27 26AD1 25 RESET24 ISETAD3 23 RXClKAD4 22 RXDADS 21 TXDAD6 20 csAD7 19 EXClK12 13 14 15 16 17 18w0~-JI~ I~ 0 ~ -J< > f- I~ xf-28-Pln PLCCN/CAD1AD2AD3AD4ADSAD6AD7N/CN u.0 ~W8 F ~ -J Z ~ c:< x x Cl c: >4 3 2 32 31 305 29 N/C6 28 RESET7 27 ISET8 26 RXCLK9 25 RXD10 24 TXD11 23 CS12 22 EXCLK13 21 N/C14 15 16 17 18 19 20w '0~-JI~ I~ 0 ~ -J< > I~f- xf-32-Pin PLCC:s ...JIii '" '"0o 000 gJ 0 0 0~ :l! ~ ~ ~ ~ ~ :l! ~ 0 ~ :l! ~52 51 50 49 48 47 46 45 44 43 42 41 4039 NIC38 INTB37 NlC38 TXANIC 35 NlCNIC 34 NICGND 33 VDD32 NICNIC 30 ROB29 WRBXTAL2 28 NICNIC 27 ALE15 16 17 18 19 20 21 2223 24 25 268 0 00( ~ 0 g g .:!i00( 00( 00( 00(:g00( ~ ~.... 0 0:l! ~ :l! :l!ClKXTl1XTl2ADOAD1AD2AD3AD4AD5AD6AD7ALEWRADGNDRXAVREFRESETRXAISETVREFRXClKRESETRXDISETTXDRXCLKcs A1 RXDEXCLKTXDTXClKEXCLKINTTXCLKTXA RD lNTVDDTXA52-Lead QFP28-Pin DIP400-Mil22-Pin DIPCAUTION: Use handling procedures necessaryfor a static sensitive component.3-258

SSI73K324LCCITT V.22bis, V.22, V.21 , V.23, Bell 212ASingle-Chip ModemCAUTION: Use handling procedures necessaryfor a static sensitive component.ADO64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 491. ~N/CN/C2 47ISETN/C46N/CN/C45RXCLKNIC44N/CAD143RXDN/C42N/CAD241N/CAD340TXDAD4ADS10113938N/CosAD6N/CAD7NIC1213141537363534EXCLKN/CN/CN/CINIC16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33N/C64-Lead TQFPORDERING INFORMATIONPART DESCRIPTIONORDER NO.PKG.MARKSSI 73K324L with Serial Bus Interface22-Pin Plastic Dual-In-LineSSI 73K324L with Parallell Bus Interface28-Pin Plastic Dual-In-Line28-Pin Plastic Leaded Chip Carrier32-Pin Plastic Leaded Chip Carrier44-Pin Plastic Leaded Chip Carrier52-Pin Quad Flat Pack Package64-Lead Thin Quad Flat Pack Package73K324LS-IP73K324L-IP73K324L-281H73K324L-321H73K324L-IH73K324L-IG73K324L-IGT73K324LS-1 P73K324L-IP73K324L-281H73K324L-321H73K324L-IH73K324L-IG73K324L-IGTNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is g ranted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheetis current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914Protected by the following patents: (4,777,453)(4,789,995) (4,870,370) (4,847,868) (4,866,739) 3-2590494 - rev©1990 Silicon Systems, Inc ..

Notes:3-260

Section 4CONTROLLERS &SPECIAL MODEMPRODUCTSI4

IjjjjIjIjjjj4-0jjj

DESCRIPTIONThe SSI 7302248A12348A Chip Sets consists of twoCMOS integrated circuits which provide the data pumpand protocol functions required to implement a highperformance 2400 biVs modem with error control anddata compression. The 7302248A basic modemfunction is provided by the SSI 73K224L modem chipand is compatible with CCITT V.21, V.22, V.22bis andBell 103 and 212A protocols. The error controlfunctions are provided by modular software running inthe SSI730291 0 controller. Modules are available forMNP4, and V.42. compression software modules canbe can be added to the controller; MNP5 and V.42bisare available. Provisions for customization of thecommand set are provided, forming the basis for aninternational modem.The 7302348 differs from the 7302248A in that it usesthe 73K324L instead of the 73K224L forthe data pump.The 73K324L replaces the Bell 103 300 baud FSKmode of operation withthe CCITTV.231200baud FSKmode. The software is also modified to support V.23.The two products are otherwise identical.SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetRrf'i'em'·]I;1111~·lilFEATURESSeptember 1994Combines modem and protocol controllerSupports 0 - 300, 1200 and 2400 bitls with bothsync and async modesModular software desig n allows custom izationModem protocols:Bell 103, 212ACCITT V.22, V.22bisError control/compression protocolsAvailable: MNP4, MNPS, CCITT V.42, V.42bisSupports non-volatile memory to store userconfigurations and phone numbersCMOS design for low power consumptionTQFP packages available for PCMCIAapplicationsIMNP5, V.42bis DatacomModem Device Set0994 - rev 4-1CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetFUNCTIONAL DESCRIPTIONThe SS173D2248A12348A chip set forms the basis foran international modem design incorporating the mostadvanced error control and compression algorithms.The set consists of two chips, the S81 73K224L(73K324L) modem and the 73D2910 controller.Customization of the controller is one of the features ofthis chip set; software modules allow the modemvendor to provide a range of features from a standardhardware platform.The 73K224L (73K324L) provides the QAM, PSK andFSK modulator and demodulatorfunctions, call progressand handshake tone monitors, test modes and a tonegenerator capable of producing DTMF, answer andCCITI guardtones. This single-chip modem supportsthe V.22bis, V.22, V.21 and Bell 1 03/CCITI V.23/212Aoperating protocols in both sync and async modes.Low level functions of the controller provide for automaticdetection of OTE speed, auto-dial, auto-answer,handshake with fa "back and call progress detection.The 7302910 controller handles both the low levelmodem functions as we" as protocol negotiation andprotocol operation. Software modules can be chosento provide the desired protocols for productcustomization and differentiation. In addition, the "AT'command set source code will be available for thosedesiring to provide unique or country dependentfeatures.Basic capabilities of the modem are those found in the73K224L (73K324L) single-chip modem and are listedin the separate 73K224L (73K324L) data sheet.AUTOMATIC HANDSHAKEThe 73D2248A12348A wi" automatically perform acomplete handshake with a called or calling modemand enterthe data transfer mode. Afterthe link betweenthe two modems has been established, the modemsmay remain in the normal data mode or negotiate a linkwhich has error control and data compression.Commands are provided to inform the modem whichaction is appropriate.TEST MODESThe 7302248A12348A chip set has provisions for threetest modes: analog loopback, digital loopback andremote digitalloopback. Analog loop back allows datato be sent into the local modem, have it modulated andthen demodulated and returned to the local terminal.Oigitalloopback requires the cooperation of the user atthe remote end and allows data to be sent to the remotemodem, demodulated, then remodulated and returnedto the local end. Remote digital loopback allows thesame capability, without the need for a remote operator;signals are sent to the remote modem which performthe switching task that a remote operator would havedone.AT COMMAND INTERPRETERThe SSI 7302248A12348A includes an AT CommandInterpreter which is a superset of the Hayes 2400SmartmodemTM command set. Common applicationsoftware will be able to control the modem though thisinterpreter. Additional commands have been added toprovide for control of the MNP and CCITTV.42 modes.NON-VOLATILE MEMORYA serial NVRAM provides 256 bytes of storage forconfiguration information and telephone numbers.Current hardware provides for a 2K bit memory ofwhich about 400 bytes are used for setup and telephonenumber storage. The remaining 1600 bytes areavaliable. Memory address space allocated to nonvolatileRAM is 8K, so an expansion factor of 4 isavailable. Alternatively, the address space could bedecoded for more hardware functionality.4-2

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetPROTOCOLSMlcrocom Networking Protocol (MNP)MNP4 is a protocol offering error control while MNP5offers data compression. Data to be transmitted isbroken into blocks of varying sizes, depending on lineconditions, and sent to the remote modem along witha 16-bit Cyclic Redundancy Check word. If the algorithmused to derive the CRC word atthe transmitter does notproduce an identical word when exercised on thereceived data, a line error is assumed, and the block isrepeated. Data compression is obtained by transmittinga short set of characters for a longer redundant set. Atthe receiver, the short string is replaced with the longerstring that it represented, and the data stream isreturned to its original state.cCln V.42 AND V.42BISThe CCITT has ratified a set of protocols which operatein a mannersimilarto MNP. MNP4corresponds to V.42while MNP5 corresponds with V.42bis. Greaterefficiency is offered, but the tradeoff is a larger memoryspace requirement. MNP5 requires an 8K buffer, whileV.42bis requires 32K. Data files which showcompression ratios approaching 2:1 with MNP5 mayshow ratios of nearly 4:1 with V.42bis.IADDITIONAL INFORMATIONThe Silicon Systems 7302248/2348 Design Manualdefines the AT commands. Please contact your localSilicon Systems sales office or Silicon Systemsheadquarters in Tustin for a copy of the SSi ProtocolDesign Manual.4-3

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetCommandDescriptionAT COMMAND SUMMARYCommandDescriptionATAAIcommand prefix - precedes command linecarriage return character - terminates command linego into answer mode; attempt to go to on-line statere-execute previous command line;not preceded by AT nor followed by 80 select CCITI V.22 standard for 1200 biVs communication81 select 8e11212A standard for 1200 bitls communicationDdial number that follows; attempt to go to on-line state, originatemodeDS=n dial stored number in location "n" (0-3)EOE1HOH1Disable character echo in command stateEnable character echo in command statego on hook (hang up)go off hook; operate auxiliary relay10 request product indentification code11 perform checksum on firmware ROM; return checksum12 perform checksum on firmware ROM;returns OK or ERROR result codesLO or L 1 low speaker volumeL2L3MOM1M2M300010001SrSr=nSr?VOV1WOW1XOmedium speaker volumehigh speaker volumespeaker offspeaker on until carrier detectedspeaker always onspeaker on until carrier detected, except during dialinggo to on-line statego to on-line state and initiate equalizer retrain at 2400 biVsmodem returns result codesmodem does not return result codesset pointer to register "r"set register "r" to value "n"display value stored in register "r"display result codes in numeric formdisplay result codes in verbose form (as words)negotiation progress result codes not returnednegotiation progress result codes returnedenable features represented by result codes 0-4X1 enable features represented by result codes 0-5, 10-12X2 enable features represented by result codes 0-6, 10-12X3 enable features represented by result codes 0-5, 7,10-12X4YOY1ZO&CO&C1&00&D1&D2&D3&F&GO&G1&G2&K&MO&M1enable features represented by result codes 0-7, 10-12disable long space disconnectenable long space disconnectreset modemassume data carrier always presenttrack presence of data carrierignore DTR signalassume command state when an on-to-offtransition of DTR occurshang up and assume command state when an on-to-offtransition of DTR occursreset when an on-to-off transition of DTR occursrecall factory settings as active configurationno guard tone550 Hz guard tone1800 Hz guard toneflow control methodasynchronous modesynchronous mode 1&M2 synchronous mode 2&M3 synchronous mode 3&05 error control mode&06 automatic speed buffering (ASS)&TO&T1&T3& T4&T5&T6&T7&T8&V&WO&XO&X1&X2terminate test in progressinitiate local analog loopbackinitiate local digitalloopbackgrant request from remote modem for RDLdeny request from remote modem for RDLinitiate remote digitalloopbackinitiate remote digital loop back with self testinitiate local analog loopback with self testview active configuration, user profiles, and stored numberssave storable parameters of active configurationmodem provides transmit clock signaldata terminal provides transmit clock signalreceive carrier provides transmit clock signal&Zn=x store phone number "x" in location "n" (0-3)4-4

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetDial string arguments:,= delay; = return to command@ = silent answers = dial stored number! = flashW = wait for toneR=reverse modeIf the Nov RAM has not been initialized it may be necessary to power down/power up and type A T&F& Wto properly initialize modem state.TABLE 1: Result CodesXnVERBOSEITERSE RESULT CODESXO OKlO, CONNECT/1, RING/2, NO CARRIER/3, ERROR/4X1 All functions of XO + CONNECT (RATE)/1 = 300, 5 = 1200, 10 = 2400X2 All functions of X1 + NO DIAL TONE/6X3 All functions of X1 + BUSY/7X4 All functions of X3 + NO DIAL TONE/6, NO ANSWER/8TABLE 2: S Registers SupportedSn FUNCTION UNITS DEFAULTISOl Answer on ring No. of rings on which to answer 000 2S1 Ring counter No. of rings accumulated 000S2 Escape code ASCII CHR Decimal 0-127 043S3 Carriage return ASCII CHR Decimal 0-127 013S4 Line feed ASCII CHR Decimal 0-127 010S5 Back space ASCIICHR 008S6 Wait for dial tone Seconds 002S7 Wait for carrier Seconds 030S8 Pause time Seconds 002S9 Carrier valid 100 milliseconds (0.1 sec) 006S10 Carrier drop out 100 milliseconds (0.1 sec) 014S11 DTMF tone duration 1 millisecond (0.001 sec) 070S12 Escape guard time 20 milliseconds (0.05 sec) 050S13 Unused N/A*S14 1 Bit mapped register Decimal 0-255 170Stored in NVRAM with &W command.Modem will not answer until value is changed to 1 or greater.4-5

SS173D2248A/2348AMNP5, V.42bis DatacomModem Device SetTABLE 2: S Registers Supported (Continued)NUMBERFUNCTION815 Unused816 Test register817 8pecial test register818 Test timer819 Unused820 Unused*8211 Bitmapped register*8221 Bitmapped register*823 1 Bitmapped register824 Unused825 1 DTR delay826 1 CT8 delay*8271 Bitmapped register836 Negotiation failure treatment837 Desired modem line speed838 Hang-up timeout839 Current flow control setting843 Current DCE speed846 Protocol/Compression selection848 Feature negotiation action849 A8B Buffer low limit850 A8B Buffer high limit882 Break select register895 Extended result code bit mapUNITSDecimal #Decimal 0-255Decimal 0-255Decimal 0-255Decimal 0-255Decimal 0-25510 milliseconds (0.01 sec)10 milliseconds (0.01 sec)Decimal 0-255Decimal 0-91-2492-250*The bitmapped register functions are equivalent to normal "AT" command modem registers.1 8tored in NVRAM with & W commandDEFAULTN/A000096000N/AN/A000118007N/A005001064500020302781612804-6

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetPACKAGE PIN DESIGNATIONS(Top View)NlCNlCNlCNlCNlCA1A2A3A4A5A6A7ASA9A10A11A12A13A14A15PSENRESETVNDOSCOUTOSCINNlCNlCClK20UTNlCNlCN/CN/CUSR50NlCUSR51USR31USR30USR40USR41USR42USR43USR44USR45USR46USR47VNDVPDUSR20USR21USR22USR23USR24USR25USR26USR27N/CN/CN/CNlCN/CIClI-ClCla..:Jxx>Ol-CI:;;;:...J()5517302910Controller100-Lead QFPCAUTION: Use handling procedures necessaryfor a static sensitive component.4-7

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetPACKAGE PIN DESIGNATIONS (continued)(Top View)N!CNICNlCA1A2A3A4A5A6A7ASA9A10A11A12A13A14A15PSENRESETVNDOSCOUTOSCINNICNlC13141516171819202122232475 NlC74 NlC73 USR5172 USR3171 USR3070 USR4069 USR4168 USR4267 USR43USR44USR45USR46USR47VNDVPDUSR20USR21USR22USR23USR24USR25USR26USR27NlCNlC5517302910Controller100-Lead TQFPCAUTION: Use handling procedures necessaryfor a static sensitive comp~nent.4-8

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device Set~ :::i~ ~~ ~ ~~u. tii:.:: 0 « UI en..J Z x a: UIu ~ (!) ~ ~ a: ~ > ~ a:ADON/C64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49N/CN/CN/CAD1N/C 42AD2 41AD3AD4 39AD5AD6NlC 36AD7N/C 34NlC 3317 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32NlCISETNlCRXClKNlCRXDNlCNlCTXDNlCcsEXClKNlCNlCNlCNlCI~ ~ ~ Q 10 U Q Q~ I~~ I~~ Q« z a: Z z z U z~Xfo-~SSI73K224LSingle Chip Modem64-Lead TQFPfo-UI~~52 51:.::..J:.::..J:.::..JU 00 U UX X~ ~ x ~ ~ xI~ ~ xa: a: f0- Ul fo-50 49 48 47 46 45 44 43 42 41 4039 NlC38 INTNlC37 NIC36 TXANlC35 NlCIIVC34 IIVCGND33 VDDIIVC32 NlCClKNlC31 NlC30 RDXTL129 WRXTL228 NlCIIVC0«15~27 ALE16 17 18 19 20 21 22 23 24 25 26N C'lQ v It'l (Q,....0 0 0 0 0 0~« « «

SSI 73D2248A/2348AMNP5, V.42bis DatacomModem Device SetPACKAGE PIN DESIGNATIONS (continued)(Top View)NlC§~ ::i l

SSI73M2910/2910AMicrocontrollerDESCRIPTIONThe Silicon Systems 73M2910 high performancemicrocontroller is based on the industry standard 8-bit8052 implemented in Silicon Systems' advancedsubmicron CMOS process. The processor has thesame attributes of the 8052 including Instruction cycletime, UART, timers, interrupts, 256 bytes of on-chipRAM and programmable lID. The architecture hasbeen optimized for low power portable modem orcommunication applications by integrating uniquefeatures with the core CPU.The main feature is a user friendly HDLC packetizer,accessed through the special function registers. It hasa serial 110, hardware support for 16- and 32-bit CRC,zero insert/delete control, a dedicated interrupt and aclear channel mode for by-passing the packetizer.Other features include additional user programmablelID with programmable bank select and chip selectlogic, designed to eliminate board level glue logic. Italso includes two general purpose input ports withprogrammable wakeup capability.For devices that require non-multiplexed address anddata buses, eight latched outputs forthe low byte of theaddress are available.(continued)FEATURES8052 Compatible Instruction set34 MHz Operation @ 4.5 - 5.5VNovember 199444 MHz Operation @ 4.75 - 5.5V (2910A)22 MHz Operation @ 3.3 - 5.5VHOLC Support logic (Packetizer, 16 and 32CRC, zero 10)24 pins for user programmable I/O ports8 pins programmable Chip select log Ic or I/O formemory mapped peripheral eliminating gluelogic3 external interrupt sources (programmablepolarity)16 dedicated latched address pinsMultiplexed data/address busInstruction cycle time identical to 8052Buffered oscillator (or OSC/2) output pin1.8432 MHz UART clock availableBank select circuitry to support up to 128K ofexternal program memory100-Lead TQFP package available for PCMCIAapplicationsAlso available in 100-Lead QFP packageIBLOCK DIAGRAM1194 - rev. 4-11

SSI 73M291 0/291 OAMicrocontrollerDESCRIPTION (continued)The 73M2910 has two extra interrupt sources, anexternal interrupt and a HDLC interrupt. The HDLCinterrupt has two registers associated with it; the HDLCInterrupt Register which is used to determine thesource of the interrupt, and the HDLC Interr~pt EnableRegister that enables the source of the interrupt.The state of the external interrupts can be read througha register allowing the interrupt pins to be used asinputs. The interrupt pins INTO and INT1 can be eithernegative edge, positive edge or level triggered. TheINT2 pin is always edge triggered.Two buffered clock outputs have been added tosupport peripheral functions such as UARTs, modemsand other clocked devices. The main internalprocessor clock frequency can be divided by 2 forpower conservation in functional modes that onlyrequire half the clock speed.Additional internal special function registers are usedfor firmware control over the HDLC Packetizer, theclocks and the programmable I/O ports.To accommodate processor peripherals whenoperating at 22 MHz the processor's timing has beenaltered somewhat to allow more address setup time forslower peripheral program ROM and memory mappedperipherals. This can offer the system designers anadvantage when using higher (22 MHz) oscillatorfrequencies.For low power applications the 73M2910 operatesfrom 3 to 5 volts at 22 MHz and supports two powerconservation modes: Idle and Power-down. In thePower-down state the total current consumption is lessthan 10 J.LA at room temperature.This device is offered in small form factor 100-leadTQFP packages for PCMCIA applications and100-lead QFP packages.DEVELOPER'S NOTE:The 73M2910 is also available in a 100-pin PGApackage for system developers. The PGA packageis more convenient and reliable for developmentemulation systems than the other package styles.Emulation systems for the 73M2910 are availablethrough Signum Systems, 171 E. Thousand OaksBlvd., #202, Thousand Oaks, CA 91360(805) 371-4608.8052 REFERENCEThis Document will describe the features unique to the73M2910. Please refer to an 8052 Programmer'sGuide, Architectural Overview and HardwareDescription for details on the instruction set, timers,UART, interrupt control, and memory structure.4-12

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTIONINTERRUPTSThe core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt, andan HOLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M291 O. They do not existin a normal 8052 product. Previously unused bits in the IE and IP registers are now serving functions for theseadditional interrupt sources. The interrupt vector addresses are as follows:SOURCEINTO (lEO)TFOINT1 (IE1)TF1RI + TITF2 + EXF2INT2 - ADDED INTERRUPTHDLC-ADDEDINTERRUPTVECTOR ADDRESS003HOOBH013H01BH023H02BH033H03BHThe external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pinsis individually controlled by bits in a special interrupt direction register, I DIR (address A9). The interrupt pins INT1and INTO can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON register(address 88). Pin INT2 is always an edge generated interrupt. A flag is set when a falling transition (riSing if IDIRbit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is processed.IINTERRUPT ENABLE REGISTER (IE) SFR ADDRESS A8Bit AddressableReset State OOhBIT7 BIT6 BITS BIT4 BIT3EA EX2 ET2 ES ET1BIT2 BIT 1 BITOEX1 ETO EXONote: BIT 6 differs from the 8052. This is a reserved bit in the 8052 and is used as a mask bit for external interrupt2 in the core implementation. When BIT 6 is set to a 0, external interrupt 2 is disabled.The mask bit for the HDLC interrupt source is BIT 0 of the HDLC control register.INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS B8Bit AddressableReset State OOhBIT7 BIT6 BITS BIT4 BIT3PHDLC PX2 PT2 PS PT1BIT2PX1BIT 1PTOBITOPXONote: BIT 6 and BIT 7 differ from the 8052. These are reserved bits in the 8052 and are used to determine thepriority of external interrupt 2 and the HDLC in the core implementation. When BIT 6 is set to a 1, the interruptis set to the higher priority level.4-13

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)EXTERNAL INTERRUPT DIRECTION REGISTER (lDIR) SFR ADDRESS 92Byte AddressableReset State OOhBIT7 BIT6 BIT5 BIT4 BIT3 BIT20 0 INT2 INT1 INTO INTD2BIT 1INTD1BITOINTDOThese bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interruptand will also allow the user to directly read the logic level at the pads INT(2:0).BITS(5:3) INT(2 :0)BITS(5:3) are read only bits that reflect the logic value at the corresponding pin. The value is not affected byBITS(2:0).BITS(2:0) Interrupt Polarity ControlIf the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1 , a rising edge will trigger theinterrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high andthe internal pin signal to the timer controls will be inverted.Bits 6 and 7 will always be read as O's.CLOCK CONTROL REGISTER SFR ADDRESS DAByte AddressableReset State OOhBIT7 BIT6 BIT5 BIT4Activity CLK1 MCLK CLK2ENCTRL1 CTRLBIT3 BIT2 BIT 1 BITOCLK2 CLK2 CLK1EN CLK1CTRL1 CTRLO CTRLOThese bits determine the behavior at the CLK1 OUT and CLK20UT pins and allow the user to divide the maininternal processor clock frequency by two for power conservation.BIT7BIT 7 is an activity bit. It is cleared by a read of this register. If the activity bit is set it will prevent the 73M291 0from entering Sleep mode.BIT6When BIT 6 = 1, CLK10UT will be OSC/1.5 if bit 1 is a 1 and bit 0 is O.BIT5CLOCK OUT0 OSC1 OSC/2BIT 5 Master Clock ControlWhen BIT 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. If this bit is a 0, theprocessor clock is the same frequency as the oscillator's.4-14

551 73M291 0/291 OAMicrocontrollerBIT 4 Clock 2 Output EnableBIT 4 enables the clock at the CLOCK 2 output pin if it is set to a 1. The CLOCK 2 pin output is held to a 0, bywriting this bit to a O. This will reduce system power if the clock pin is not used or if a power reduction mode isrequired.BIT 3 BIT 2 Clock 2 Output ControlThese bits determine the oscillator divisor for the CLOCK 2 output pin. They were designed to provide a 1.8432MHz clock for an external UART given an oscillator frequency of 11.0592 MHz, 22.1184 MHz, 18.432 MHz, or13.824 MHz.BIT3 BIT2 CLK20UT OSC FREQUENCY0 0 OSC/7.5 13.824 MHz0 1 OSC/6 11.059 MHz1 0 OSC/12 22.118 MHz1 1 OSC/10 18.432 MHzBIT 1 CLOCK 1 Output EnableBIT 1 enables the clock at the clock 1 output pin if it is set to a 1. The clock pin output is held to a 0, by writinga 0 to this bit. This will reduce system power if the clock pin is not used or if a power reduction mode is required.BIT 6 is cleared to a 0 upon a reset.IBIT 0 Clock 1 Output ControlBIT 0 controls the frequency of the clock 1 output pin. The clock output is either the oscillator's output signaldivided by two or a buffered oscillator output signalPOWER SAVING MODESLow Power ModesThe SSI 73M291 0 supports two power conservation modes, which are controlled by the PCON.1 and PCON.Ocontrol bits of the PCON register.If PCON.O is set, the SSI 73M291 0 will go into a power saving mode where the oscillator is running, clocks aresupplied to the UART, timers, HDLC, and interrupt blocks, but no clocks are supplied to the CPU. Instructionprocessing and activity on the address and data ports is halted. Normal operation is resumed when an unmaskedinterrupt is requested or when a reset occurs.If PCON.1 is set, the SSI 73M291 0 goes into its lowest power mode where the oscillator is halted. The total currentconsumption in this state should be less than 10 IJ-a. The SSI 73M2910 will start its oscillator and begin to returnto normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge ofan unmasked external interrupt from pins INT(2:0) is detected, or when the USR5(1 :0) pins change to a stateaccording to the USR 5 port register. Edges used in wakeup modes are not filtered in the SSI 73M291 0, so theuser must be cautious of noise or small glitches inadvertently waking up the chip. From the time the edge thatresults in the wake up occurs, to the point at which an instruction is executed, depends on the oscillator start-uptime. Three good oscillator pulses must be detected before the main internal clocks are generated.During Power Down mode, both the ALE and PSEN pins are pulled high since these signals often provide theoutput enable and chip enable forthe ROM (active low). This ensures that the external components are in theirlowest power state.4-15

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)USER PROGRAMMABLE I/OPort Control USR1, USR2, USR3, USR4, USR5The core chip provides 32 user I/O pins. Each pin is programmed separately as either an input or as an outputby a bit in a direction register. If the bit in the direction register is set to a 1, the I/O control will treat thecorresponding pin as an input. If it is a 0, the pin will be treated as an output whose value is determined by theport data register. The USR1 and USR2 port registers are accessed through the internal SFR bus. The USR3and USR4 ports are accessed through the external memory bus by a MOVX instruction. The USR4 port providesthe user with an automatic chip select function if selected by the user. If the user does not require some (or any)of the chip select pin options, he may program the USR4 port pins to operate in the same way as USR3 port pins.The USR DATA register contents determine pin values if chosen as an output. When reading from the DATAregister's SFR address, the pin logic values are returned as data except when the port address is the destinationaddress for a read-modify-write instruction. In this case, the latched register values are returnedas data. When reading data from a DATA register that is mapped in the external memory space, the pin valuesare always retu rned as data.The USR5 register allows for 2 additional input pins. In normal operation these pins can be used as generalpurpose inputs. In Power Down mode, the user can program either rising or falling transitions or logicalcombinations of these pins to wake up the chip.USER 1 PORTUSR1 DATA SFR Address 90Bit AddressableReset State OOhBIT7 BITS BIT5USR17 USR16 USR15BIT4 BIT3 BIT2 BIT 1 BITOUSR14 USR13 USR12 USR1 1 USR10Bits in this register will be asserted on the USR1 (7:0) pins if the corresponding direction register bit is a O.Reading this SFR's address will return data reflecting the values of pins USR1 (7:0) except when address 90his the destination address for a read-modify-write instruction. In this case, the latched register values arereturned as data.USR1 port signals are also used as timer controls. In applications where the external signals are required fortimer count modes, the corresponding port pin should be configured as an input.USR1 BITOUSR1 BIT1USR1 BIT2USR1 BIT3TIMER 0 TO PINTIMER 1 T1 PINTIMER 2 T2EX PINTIMER 2 T2 PINUSR1 Port Direction (DIR1) SFR Address 91Byte AddressableReset State FFhBIT7 BIT6 BIT5 BIT4DIR17 DIR16 DIR15 DIR14BIT3 BIT2 BIT 1 BITODIR13 DIR12 DIR1 1 DIR10This register is used to designate the USR1 pins as either inputs or outputs. If the register bit is reset to a 0, thecorresponding USR1 pin is programmed as an output that will be driven by the corresponding USR1 DATAregister bit. If the register bit is a 1, the corresponding pin will be treated as an input.4-16

SSI 73M291 0/291 OAMicrocontrollerAfter a reset, the USR1 pins will present a high impedance output state and the input values will not be drivenfrom the pin, but will be driven to a 1 internally. The pins will assume normal 1/0 operation once the processorhas written the port direction register. This feature will ensure a low current state at reset(you don't want to drive out against external inputs, and you don't want floating inputs).USER2 PORTUSR2 Port Data SFR Address D8Bit AddressableReset State OOhBIT7 BIT6 BITSUSR27 USR26 USR25BIT4 BIT3 BIT2 BIT 1 BITOUSR24 USR23 USR22 USR21 USR20Bits in this register will be asserted on the USR2(7:0) pins if the corresponding direction register bit is a O.Reading this SFR's address will return data reflecting the values of pins USR2(7:0) except when address D8his the destination address for a read-modify-write instruction. In this case, the latched register values arereturned as data.USR2 Port Direction (DIR2) SFR Address D9Byte AddressableReset State FFhBIT7 BIT6 BITS BIT4DIR27 DIR26 DIR25 DIR24BIT3 BIT2 BIT 1 BITODIR23 DIR22 DIR21 DIR20•This register is used to designate the USR2 pins as either inputs or outputs. If the register bit is reset to a 0, thecorresponding USR2 pin is programmed as an output that will be driven by the corresponding USR2 1/0 OAT Aregister bit. If the register bit is a 1 , the corresponding pin will treated as an input.After a reset, the USR2 pins will present a high impedance output state and the input values will not be drivenfrom the pin, but will be driven to a 1 internally. The pins will assume normal 1/0 operation once the processorhas written the port direction register. This feature will ensure a low current state at reset (you don't want to driveout against external inputs, and you don't want floating inputs).USR3 Port Data External address 0000Byte AddressableReset State OOhBIT7 BIT6 BIT 5USR37 USR36 USR35BIT4USR34BIT 3 BIT2 BIT 1 BITOUSR33 USR32 USR31 USR30Bits in this register will be asserted on the USR3(7:0) pins if the corresponding direction register bit is a o.Reading this SFR's address will return data reflecting the values of pins USR3(7:0).If the bank select feature is chosen, USR3 PIN7 acts as address bit 17 and USR3 data bit 7 is ignored.4-17

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)USR3 I/O Port Direction (DIR3) External Address 0001Byte AddressableReset State FFhBIT7 BIT6 BIT5 BIT4 BIT3DIR37 DIR36 DIR35 DIR34 DIR33BIT2 BIT 1 BIT 0DIR32 DIR31 DIR3 °This register is used to designate the USR3 pins as either inputs or outputs. If the register bit is reset to a 0, thecorresponding USR3 pin is programmed as an output that will be driven by the corresponding USR3 DATAregister bit. If the register bit is a 1, the corresponding pin will be treated as an input.After a reset, the USR3 pins will present a high impedance output state and the input values will not be drivenfrom the pin, but will be driven to a 1 internally. The pins will assume normal 1/0 operation once the processorhas written the USR3 port direction register. This feature will ensure a low current state at reset (you don't wantto drive out against external inputs, and you don't want floating inputs).If the bank select feature is chosen, USR3 PIN7 is forced to be an output.Bank Select (BNKSEL) External Address 0002Byte AddressableReset State OOhBIT7 BIT6 BIT5 BIT4B7 B6 B5 B4BIT3B3BIT2BSENBIT 1BS1BITOBSOThis resister is used to accommodate systems where more than 64 Kbytes (up to 128 Kbytes) of programmemory are required. USR3 PIN 7 acts as an address pin, A16, if BSEN is set to a 1 and if the processor isfetching an instruction and not data memory. If BSEN is set to a 1, A 15 is also modified during instruction fetchesas shown. If BSEN is a 0, no alterations to address bit A15 are made, and USR3 PIN 7 is a function of USER3bit 7 and DIR3 bit 7.Bits (7-3) are general purpose read/write register bits.A 15 is the value of the 16th address bit as it appears at pin A 15.A 15' is the address from port 2 internal logic, the value that will appear as the most significant address bit ifno bank select feature is chosen.A 16 is the value of the 17th and MSB of the instruction address seen at the USR3 7 port pin, if the bank selectfeature is selected. If the bank select feature is not selected, USR3 7 acts as a normal USR3 I/O port pin.4-18

SSI 73M291 0/291 OAMicrocontrollerBSEN BS1 BSO0 * *0 * *1 0 01 0 01 0 11 0 11 1 01 1 01 1 11 1 1* = Don't care.A15'A150 01 10 01 10 01 00 01 10 01 0A16USR37USR37ADDRESSOK - 32K32K - 64K0 OK - 32K0 32K - 64K0 OK - 32K1 64K - 96K0 OK - 32K1 96K - 128K0 OK - 32K1 64K - 96KBANK 3Example: Bank 2 is selectedBSEN = 1, BS1 = 0, BSO = 1IBANK 2BANK 1Bank 2 is selectedIf A 15' is a 1, fetches will come from Bank 2Bank 2 will overlay Bank 1BANKO0- 32KThat is all fetches that would normally occurfrom Bank 1 will come from Bank 2FIGURE 8: Bank Select4-19

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)USER4 PORTUSR4 Port Data External Address 0003Byte AddressableReset State OOhBIT7 BIT6 BIT 5 BIT4USR47 USR46 USR45 USR44BIT3 BIT2 BIT 1 BITOUSR43 USR42 USR41 USR40Bits in this register will be asserted on the USR4(7:0) pins if the corresponding direction register bit is a 0 andif the corresponding bit in the chip select enable register, 0005, is set to a O. Reading this register will return datareflecting the values of pins USR4(7:0).USR4 1/0 Port Direction (DIR4) External Address 0004Byte AddressableReset State FFhBIT7 BIT6 BIT5 BIT4 BIT3DIR47 DIR46 DIR45 DIR44 DIR43BIT2 BIT 1 BITODIA42 DIR4 1 DIR40This register is used to designate the USR4 pins as either inputs or outputs. If the register bit is reset to a 0, thecorresponding USR4 pin is programmed as an output that will be driven by the corresponding USR4 1/0 DATAregister bit if the corresponding bit in the chip select enable register, 0005, is set to a O. If the register bit is a 1,the corresponding pin will treated as an input only if the corresponding bit in register 0005 is set to a O.After a reset, the USR4 pins will act as chip select outputs.USR4 Port Chip Select Enable (CSEN) External Address 0005Byte AddressableReset State FFhBIT7 BIT6 BIT5 BIT4 BIT3CSEN 7 CSEN6 CSEN5 CSEN4 CSEN3BIT2 BIT 1 BITOCSEN2 CSEN 1 CSEN 0This register is used to designate the USR4 pins as either user programmable II0s or as chip select (CSOB -CS7B) functions on a pin by pin basis. This feature is designed to help reduce external glue logic for peripheralmemory mapped devices. The chip select function is programmed by setting the appropriate bits in the CSENregister. When a chip select pin is enabled by setting the corresponding CSEN bit to a 1, all data and directioninformation from registers 0003 and 0004 for this bit are ignored and the selected port becomes an output. Ifthe bit is reset to a 0, the pin will be treated as a normal programmable user 1/0 pin as defined by registers 0003and 0004.The chip select pins have a defined memory map. The intent is that the outputs can be wire ORed together fora flexible selection of peripheral chip selects. All chip selects will be disabled (forced to a logic 1. It is assumedthat all chip selects are active low) after the read or write is completed, and the appropriate chip select will beenabled as the next new external addresses is asserted. After a reset, the CSB pull-up devices are all enabled,that is, all chip select outputs are high. Users must account for this if these pins are intended to be generalpurpose I/0s.4-20

SSI 73M291 0/291 OAMicrocontrollerThe chip selects partition a 64K memory space as follows:CHIP SELECT PIN ADDRESS # BYTESRESERVED FOR INTERNAL USE OOOOH - OOFFH 256CSO (USR4.0) 0100H - 01 FFH 256CS1 (USR4.1) 0200H - 03FFH 512CS2 (USR 4.2) 0400H - 07FFH 1KCS3 (USR4.3) 0800H - OFFFH 2KCS4 (USR 4.4) 1 OOOH - 1 FFFH 4KCS5 (USR 4.5) 2000H - 3FFFH 8KCS6 (USR 4.6) 4000H - 7FFFH 16KCS7 (USR 4.7) 8000H - FFFFH 32KNote: You can't read from external addresses OOOOH-OOFFH. These are reseNed for SSI 73M291 0 internallydefined registersUSER5PORTUSR5 Port Register External Address 0006Byte AddressableReset State 60hBIT 7 BIT6 BIT5 BIT4USR5EN USR50 USR51 POL50BIT3 BIT2 BIT 1 BITOPOL51 ACTEO ACTE1 AND01IThis register allows user programmable wakeup capability. If this is not required, this register can be used toread external signals at the USR51 and USR50 pins.Bit 7 USR5 Input Port EnableBit 7 is used to enable the USR51 and USR50 input circuitry. If this bit is a 0, the USR5 pad circuitry is drivento a known level internally and any signal level at the chip pin is ignored. When set to a 1 the pad circuitry isenabled and the values of these pins are reflected in BITS 6 and 7. If these pins are not connected at the boardlevel, this bit should remain at a 0 to keep the pad circuitry from drawing unnecessary current.The USR5 register can be programmed such that a transition (bit 4 determines rising or falling) of USR50, atransition (bit 3 determines rising or falling) of USR51, orthe logical combination of USR50(B) (bit 4 determineshigh or low level) AND USR51 (B) (bit 3 determines high or low level) can wakeup the processor from its PowerDown mode.BIT6 USR50BIT 6 reflects the value of chip pin USR50 if the USR5EN bit is set to a 1.BIT5USR50BIT 5 reflects the value of chip pin USR51 if the USR5EN bit is set to a 1.4-21

551 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)BIT 4 USR50 PolarityBIT 4 determines which edge or level is used in the wakeup detection circuit. A low level selects a rising transitionand the true pin value of USR50tothe wakeup combinatorial circuit. When this bit is set to a 1, a falling transitionand complemented USR50 value is presented to the wakeup combinatorial circuit.BIT 3 USR51 PolarityBIT 3 determines which edge or level is used in the wakeup detection circuit. A low level selects a rising transitionand the true pin value of USR51 to the wakeup combinatorial circuit. When this bit is set to a 1 , a falling transitionand complemented USR51 value is presented to the wakeup combinatorial circuit.BIT 2 USR50 Edge Activity EnabledWhen BIT 2 is set to a 1, a transition of USR50 of the appropriate level as dictated by BIT 4, will wake up theprocessor. If this bit is reset to a 0, edge activity on this pin is ignored.BIT 1 USR51 Edge Activity EnabledWhen BIT 1 is set to a 1, a transition of USR50 of the appropriate level as dictated by BIT 3, will wake up theprocessor. If this bit is reset to a 0, edge activity on this pin is ignored. .BIT 0 Combinatorial and of USR50 and USR51 Level EnabledWhen BIT 0 is set to a 1, the value USR50 or its complimented value as dictated by BIT3, ANDed with the valueUSR51 or its complimented value as dictated by BIT 2, will wake up the processor. If this bit is reset to a 0, thelevels of USR50 and USR5i are ignored.USR50 USR51 BIT4 BIT3 BIT2 BIT 1 BITO WAKEUP* * * * 0 0 0 NO0-1 * 0 * 1 * * YES1-0 * 1 * 1 * * YES* 0-1 * 0 * 1 * YES* 1-0 * 1 * 1 * YES0 0 1 1 * * 1 YES1 0 0 1 * * 1 YES0 1 1 0 * * 1 YES1 1 0 0 * * 1 YES* = Don't care.4-22

551 73M291 0/291 OAMicrocontrollerHOLC CONTROL REGISTER 0HOLC Control Register 0 (HOLCO) SFR Address COBit Addressable Reset State OOXX 0000 bBits 5 and 4 are read only bitsBIT7 BIT6 BITS BIT4WRXD WPTXD TXD PRXDRRBIT3 BIT2 BIT 1RXD RXD PTXCTRL1 CTRLO CTRL1BITOPTXCTRLOThis register controls the basic set-up of the DTE and modem pins RXD, TXD, PRXD, and PTXD.61T7WRXOBIT 7 allows the processor to write directly to the SSI 73M291 0 RXD output pin. The value of BIT 7 will appearat the PTXD pin only if BIT 1 is a 1 and BIT 0 is a O.BIT6WPTXOBIT 6 allows the processor to write directly to the SSI 73M291 0 PTXD output pin. The value of BIT 6 will appearat the PTXD pin only if BIT 1 is a 1 and BIT 0 is a O.BITSTXOBIT 5 is a read only bit that reflects the value at the SSI 73M2910 TXD input pin.IBIT4PRXOBIT 4 is a read only bit that reflects the value at the SSI 73M2910 PRXD input pin.BIT 3 BIT 2 RXO ControlBIT 3 and BIT2 control the source of the SSI 73M291 0 RXD output pin. This output goes to the DTE's RS232interface. The source of this signal can be the core's UART TXD output, the PRXD output from a modemperipheral (clear channel), the DTE's TXD(echo), or the value written into bit 7 of this register.BIT3 BIT2 RXO OUTPUT0 0 UART TXD OUTPUT0 1 PRXD BUFFERED (CLEAR CHANNEL)1 0 TXD BUFFERED (ECHO)1 1 WRXD (BIT 7)BIT 1· BIT 0 PTXO ControlBIT 1 and BITO control the source of the SSI73M2910 PTXD output pin. This output goes to the modem's TXdata input. The source of this signal can be the core's HDLC TX output, the DTE's TXD output (clear channel),or the value written into bit 6 of this register.BIT1 BITO PTXD Output0 0 HDLC TX Output0 1 TXD Buffered (Clear Channel)1 0 WPTXD (BIT 6)1 1 04-23

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)HOLC CONTROL REGISTER 1HOLC Control Resister 1 (HOLC1) SFR Address C1Byte AddressableReset State OOhBIT7 BIT6 BITS BIT4HOLC CCITT CRC RXCRCRST PRE 32BIT3 BIT2 BIT 1 BITORXCRC TXCRC ZERO HOLC16 CTRL 10 ENThis register controls the basic set-up of the HOLC block. This register will be written during initialization andnot during normal message processing.BIT 7 HOLC Software ResetWhen BIT7 is a 1 ,the HOLC circuit is reset and held in a low power state and no interrupts from the HOLC circuitrywill be generated. When a 0 is written to this bit, the HOLC circuit will behave according to its control bits. BIT7 and the power on reset Signal are OR'ed together to form a reset signal for the HOLC block.BIT 7 is cleared to a 0 upon a power up reset.BIT 6 CRC Type ControlBIT 6 selects the CRC algorithm used in the 16 bit CRC calculation. There are two types of 16-bit CRCscommonly used, CRC16 and the CCITT 16-bit CRC. If this bit is set to a 1, the CCITT type is selected.BIT 6 is cleared to a 0 upon a reset.BIT S CRC Preset ValueBIT 5 selects the reset value for the CRC generator and receiver. If this bit is set to a 1 , the CRC generator andreceiver are initialized to ones and if this bit is reset to a 0, they are initialized to Os. This bit should be set to a1 for most CCITT polynomials.BIT 5 is cleared to a 0 upon a reset.BIT 4 BIT 3 RX CRC ControlBIT 4 and BIT3 determine the type of CRC remainder that will be checked at the end of a received frame. Thereis a 16-bit CRC, and a 32-bit CRC that the HOLC block can support. If both BIT 4 and BIT 3 are reset, bits 7 and6 of the HOLC STATUS register will be held to a O. If both BIT 4 and BIT 3 are 1 s, a special CRC search modeis enabled where both bits 7 and 6 of the HOLC status register are enabled. This mode is used during aconnection to determine whicnCRC is used by the initiating modem. If the 16-bit CRC remainder is not matchedat the end of the received frame, then BIT 6 of the HOLC STATUS register is set. If the 32-bit CRC remainderis not matched at the end of the received frame, then BIT 7 of the HOLCST ATUS register is set. Once the correctCRC type is established during a connection, either BIT 4 or BIT 3 should be set to a 1 enabling the appropriateINVALID CRC status bit.BIT4 BIT3 CRCTYPE0 0 NO CRC Check0 1 Enable CRC16 Status1 0 Enable CRC32 Status1 1 Enable CRC16 Status and CRC32 Status4-24

SSI 73M291 0/291 OAMicrocontrollerBIT 2 TXCRC ControlBIT 2 controls the CRC type to be transmitted. If BIT 2 is reset to a 0, a 16-bit CRC will be transmitted with theSEND CRC command. If BIT 2 is set to a 1, a 32 bit CRC will be transmitted.BIT 1 Zero Insert/Delete ControlWhen BIT 1 is set to a 1, a 0 will be transmitted if either the SEND DATA or SENDCRC bits of the HDLCTXCONTROL are set after five consecutive 1s have been transmitted. Also, when this bit is set, aO will be removedfrom the received data stream if it immediately follows a pattern of a 0 followed by five consecutive ones. If BIT1 is reset to a 0, no Os will be inserted during transmission, and no Os will be deleted during reception.BIT 1 is cleared to a 0 upon a reset.BIT 0 HOLC Interupt EnableWhen BIT 0 is reset to a 0, the HDLC will be prevented from generating an interrupt. The status bits that indicatethe source of the interrupt can still be set allowing the HDLC block to be serviced in a polled mode.,BIT 0 is cleared to a 0 upon reset.HDLC TX Control Resister (HTXC) SFR Address C2Byte AddressableReset State OOhBIT7 BIT6 BITS BIT40 0 0 DIV16CLKBIT3 BIT2 BIT 1 BITOSEND SEND SEND SENDABORT CRC DATA FLAGIThis register is used to control the source of data that appears on the PTXD pin. Bits are shifted out on everyrising edge of the PTXCLK pin input. If no control bits are set, or more than 1 TX CONTROLbit is set, the PTXDpin will go to a binary 1.BIT 7 • BIT 5 Always 0BIT 4 16X Clock SelectUnder normal synchronous operation, the PTXCLKand PRXCLK are used to receive and transmit data PRXDand PTXD. The clock rate is equal to the data rate. In asynchronous modes, a clock 16 times the bit rate isprovided at PTXCLK a.nd PRXCLK.When BIT 4 is set to a 1 for asynchronous operation, the clocks at the PTXCLK and PRXCLK pins are dividedby 16 to provide transmit and receive shift clocks. An internal clock for sampling incoming PRXD data issynchronized by detecting any falling edge on the PRXD data pin. The rising edge of this internal clock, whichused to sample incoming data, is delayed from the falling data edge by 8 PRXCLK periods and will continue atthis phase and at a PRXCLK/16 frequency until another falling PRXD edge is detected.If BIT 4 is reset to a 0, the rising edge of PTXCLK is used to sample the data at PRXD, and the falling edge ofPTXCLK is used to shift new data onto PTXD.BIT 3 is cleared to a 1 upon a reset.4-25

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)BIT 3 AbortWhen BIT 3 is set to a 1, a series of consecutive ones will immediately be transmitted through the PTXO pin onevery falling edge of PTXCLK. The message will have been aborted after 2 TX ready interrupts are received.No zeros will be inserted during the abort transmission.BIT 3 is cleared to a 1 upon a reset.BIT 2 Send CRCWhen BIT 2 is set, the bytes in the TX CRC generatorwill be inverted and serially transmitted to the PTXO outputon the falling edge on PTXCLK as soon as the present data byte transmission is completed. If BIT 1 of the HOLCcontrol register is a 0, aO will be inserted into the CRC data stream after five consecutive ones are transmitted.As soon as the last bit of the CRC is sent, a series of Flags will be automatically sent until another TX controlbit is set. No TX Ready interrupts will be generated during the transmission of the CRC bytes. A TX Readyinterrupt will be generated as the first bit of each Flag byte is transmitted indicating that the CRC transmissionhas been completed. This should be cleared by a dummy write to the TX DATA register.BIT 2 will be cleared to a 0 upon a reset.BIT 1 Send DataWhen BIT 1 is set, the data is the TX data register will be serially transmitted through the PTXO pin on everyfalling edge of PTXCLK, LSB first. If BIT 1 of the HOLC control register is a 0, a 0 will be inserted into the datastream after five consecutive 1 s are transmitted. After all eight data register bits have been sent, the HOLC willcontinue to send data by loading the parallel serial transmit register with new transmit register data, unless eithera TX underrun is detected or one of the other TX control bits has been set. This bit will be cleared by the HOLCcircuitry as soon as a TX underrun is detected. A TXROY interrupt will be generated at as the first data of eachdata byte is transmitted. BIT 1 will be cleared to a 0 upon a reset.BIT 0 Send FlagWhen BIT 0 is set, a pattern of 7E will be transmitted to the PTXO output as soon as either the next data byteor CRC has completed transmission. No Os will be inserted during the flag transmission. When BIT 0 is resetback to a 0, the HOLC circuitry will complete the flag byte in progress and then transmit according to bits in theTX CONTROL register. TX Ready interrupts will be generated as each byte of flag transmission is initiated.BIT 0 will be cleared to a 0 upon a reset.HOLC STATUS REGISTERHOLC Status Register (HSTAT) SFR Address C3Byte AddressableReset state OOhRead only registerIf any of the HOLC status bits are set, BIT 1 of the HOLC INTERRUPT register (NEW STATUS) will be setif the corresponding bit in the HOLC INTERRUPT ENABLE register is set.BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT 1 BITOINVAL INVAL TX RX INVAL ABORT IDLE FLAGCRC32 CRC16 UNDRN OVRN FLAG OET DET OET4-26

551 73M291 0/291 OAMicrocontrollerBIT 7 Invalid CRC32BIT 7 will be set if the CRC search mode or the 32-bit CRC is enabled by the HDLC control register and anincorrect remainder for the 32-bit CRC is detected at the last received byte prior to receiving a flag.BIT 7 will by cleared upon a reset and is cleared by a read of the HDLCSTAT register.BIT 6 Invalid CRC16BIT 6 will be set if the CRC search mode or the 16-bit CRC is enabled by the HDLC CONTROL register and anincorrect remainder for the 16-bit CRC is detected at the last received byte prior to receiving a flag.BIT 6 will by cleared upon a reset and is cleared by a read of the HDLC STAT register.BIT 5 TX UnderrunWhen BIT 5 is set, a transmit underrun condition has been detected. This is a condition where the HDLC hasfinished transmitting a message byte, but no new data has been loaded into the TX DATA register, and no othertransmit control bit has been set. This bit will be set only if the SEND DATA bit, BIT 1 ofthe TXCONTROL registeris set. The transmit data is double buffered since the TX data register is downloaded into a TX serial registerwhen the HDLC begins to transmit a new data byte. At the time of loading the TX serial register, a TX READYinterrupt is generated. This interrupt must be serviced by either loading a new data byte (the next data byte tobe transmitted) into the TX data register, or by setting another TX control bit, before the current data byte hascompleted transmission (at which point another TX READY interrupt would be generated). If a TX UNDER RUNis detected, the HDLC will abort the current transmission by sending continuous ones and will reset the SENDDATA control bit in the TX CONTROL register.BIT 5 will by cleared upon a reset and is cleared by a read of the HOLCSTAT register.IAiBIT 4 RX OverrunWhen BIT 4 is set, a receive overrun condition has been detected. This is a condition where the HOLC hasreceived a new byte, but the last received data byte has not yet been read from the RX data register. As soonas a new data byte has been received in an eight bit serial register, it is loaded into the RX data register and aNEW RX DATA interrupt is generated. If this interrupt is not serviced by reading the RX data register during thetime another new data byte is received, the RX OVERRUN status bit will be set. The new received data will notoverwrite the older unread data.BIT 4 will by cleared upon a reset and is cleared by a read of the HOLCSTAT register.BIT 3 Invalid FlagWhen BIT 3 is set, an invalid flag has been detected. This is a condition where a 7E pattern with no inserted Osis detected, and this pattern did not originate on a byte boundary. Note, two consecutive flags may share a 0,so that the second (or subsequent) flag may not appearto be on a byte boundary. This condition does not resultin an invalid flag indication.BIT 3 will by cleared upon a reset and is cleared by a read of the HOLC STAT register.BIT 2 Abort DetectWhen BIT 2 is set, an abort condition has been detected. This is a condition where seven consecutive ones, withno inserted zeros, are received after an active state. BIT 2 will be cleared upon a reset and is cleared by a readof the HOLC STAT register.4-27

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)BIT 1 Idle DetectWhen BIT 1 is set, the first indication of an idle state is detected. An idle state is declared when 15 consecutiveones, with no inserted zeros, are received after an active state.BIT 1 will be cleared upon a reset and is cleared by a read of the HOLC STAT register.BIT 0 Flag DetectWhen BIT 0 is set, the HOLC has received a 7E pattern with no inserted O's. BIT 0 will by cleared upon a resetand is cleared by a read of the HOLCSTAT register.HDLC INTERRUPT ENABLE REGISTERHDLC Interrupt Enable Register (HIE) SFR Address C4Byte AddressableReset state OOhIf the bit is set, the corresponding interrupt source is enabled.BIT 7 BIT6 BIT5 BIT4 BIT3TXROY RXROY TX ROY RX ROY INVALIE IE EN EN FLG IEBIT 2 BIT 1 BITOABORT IDLE FLAGIE IE IEBIT 7 Transmitter Ready Interrupt EnableWhen BIT 7 is set, an HOLC interrupt will be generated if BIT 0 ( TX ROY) of the HOLC INTERRUPT registeris also set. If BIT 7 is reset to a 0, no HOLC interrupt indication will be given as TX ROY is set. This interrupt enableallows the TX ROY to be a polled bit. Note that BIT 5 of this register is a pre-mask to the TX ROY bit, that is, itwill prevent the TX ROY bit from ever being set.BIT 7 will be cleared upon a reset.BIT 6 Receiver Ready Interrupt EnableWhen BIT 6 is set, an HOLC interrupt will be generated if BIT 1 ( RXROY) of the HOLC INTERRUPT registeris also set. If BIT 6 is reset to a 0, no HOLC interrupt indication will be given as RX ROY is set. This interruptenable allows the RX ROY to be a polled bit. Note that BIT 4 of this register is a pre-mask to the RX ROY bit,that is, it will prevent the RX ROY bit from ever being set.BIT 6 will be cleared upon a reset.BIT 5 Transmit Ready EnableBIT 5 is used to enable the TX ROY and TX UNOERRUN interrupt sources. When BIT 5 is set, the transmitterready indication will set BIT 0 of the HOLC interrupt register. The TX ROY indication will go active as the firstbit of a message byte is being transmitted, except during CRC transmission. Also, if this bit is set, the TX underruncondition will result in a NEW STATUS interrupt. If IT5 is reset to a 0, BIT 0 of the HOLC INTERRUPT registerwill not be set, and no corresponding HOLe interrupt will be generated. Also, a Tx underrun condition, asindicated by BIT 5 of the HOLC STATUS register, will not result in an HOLC interrupt or in setting the NEWSTATUS interrupt bit.BIT 5 will be cleared upon a reset.4-28

SSI 73M291 0/291 OAMicrocontrollerBIT 4 Receiver Ready EnableBIT 4 is used to enable the RX RDY and RX OVERRUN interrupt sources. When BIT 4 is set, the receiver readyindication will set BIT 1 of the HDLC INTERRUPT register. The RX RDY indication will go active when a databyte (a byte that is not a flag, idle, or an abort pattern) is loaded into the RX DATA register. Also, if this bit is set,the RX overrun condition will result in a NEW STATUS interrupt. If BIT 4 is reset to a 0, BIT 1 of the HDLCINTERRUPT registerwill not be set, and no corresponding HOLC interrupt will be generated. Also, a Rx overruncondition, as indicated by BIT 4 of the HDLC STATUS register, will not result in a HOLC interrupt or in settingthe NEW STATUS interrupt bit.BIT 4 will be cleared upon a reset.BIT 3 Invalid Flag Interrupt EnableWhen BIT 3 is set, a HOLC interrupt will be generated if BIT 3 ( INVALI D FLAG) of the HDLC STATUS registeris also set. If BIT 3 is reset to a 0, BIT 2 ( NEW STATUS) of the HOLC INTERRUPT register will not be set asa result of an invalid flag boundary detection and no HOLC interrupt will be generated.BIT 3 will be cleared upon a reset.BIT 2 Abort Detect Interrupt EnableWhen BIT 2 is set, a HOLC interrupt will be generated if BIT 2 (ABORT DETECT) of the HDLC STATUS registeris also set. If BIT 2 is reset to a 0, BIT 2 ( NEW STATUS) of the HOLC INTERRUPT register will not be set asa result of an abort pattern detection and no HDLC interrupt will be generated.BIT 2 will be cleared upon a reset.IBIT 1 Idle Detect Interrupt EnableWhen BIT 1 is set, an HDLC interrupt will be generated if BIT 1 (IDLE DETECT) of the HOLC STATUS registeris also set. If BIT 1 is reset to a 0, BIT 2 (NEW STATUS) of the HOLC INTERRUPT register will not be set asa result of an idle pattern detection and no HDLC interrupt will be generated.BIT 1 will be cleared upon a reset.BIT 0 Flag Detect Interrupt EnableWhen BIT 0 is set, a HDLC interrupt will be generated if BIT 0 (FLAG DETECT) of the HDLC STATUS registeris also set. If BIT 0 is reset to a 0, BIT 2 (NEW STATUS) of the HDLC INTERRUPT register will not be set asa result of a flag pattern detection and no HOLC interrupt will be generated.BIT 0 will be cleared upon a reset.HDLC INTERRUPT REGISTERHDLC Interrupt Register (HINT) SFR Address CSByte AddressableRead Only registerReset State OOhBIT7 BIT6 BITS BIT40 0 0 0BIT 3 BIT 2 BIT 1 BITO0 NEW DATA TXSTAT ROY RDYThis register is used to determine the source of HDLC interrupts. If one or more of these register bits areset, the HOLC interrupt will go active if BIT 0 of the HDLC CONTROL register is set to a 1.4-29

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)BIT 2 New StatusWhen BIT 2 is set, an unmasked HDLC status bit from the HDLC STATUS register is set.BIT 2 will by cleared upon a reset and is cleared by a read of the HDLC STATUS register.BIT 1 Data ReadyWhen BIT 1 is set, a new received byte has been loaded into the RX DATA register. Note, received bits that areflag, abort, or idle patterns are not considered data, and will not be loaded into the RX DATA register. All insertedOs have been removed from this byte. The RX DATA register must be read priorto the completed reception ofthe next data byte.BIT 1 will by cleared upon a reset and is cleared by a read of the RX DATA register.BIT 0 TX READYBIT 0 is set if any TX control bit is set as the first bit of data, flag or an idle byte is being transmitted. Whiletransmitting the current byte, the HDLC state machines are ready for commands pertaining to the next byte tobe transmitted. A new data byte must be loaded into the TX DATA register to clear the TX READY status bit.BIT 0 will by cleared upon a reset and is cleared by writing to the TX DATA register.RX DATA REGISTERRX Data Register (RXD) SFR Address C6Byte AddressableReset state XXhRead OnlyBIT7 BIT6 BITS BIT4RX RX RX RXDAT7 DAT6 DAT5 DAT4BIT3RXDAT3BIT2RXDAT2BIT 1RXOATBITORXDATOBIT 7 • BIT 0 Received Data ByteBIT7through BITO isthe received data byte (LSB is received first) with all inserted Os removed. A DATA READYinterrupt will be generated when a new data byte is received. Reading this register will clear the DATA READYinterrupt.TX DATA REGISTERTX Data Register (TXD) SFR Address C7Byte AddressableReset state XXhWrite OnlyBIT7 BIT6 BITSTX TX TXDAT7 DAT6 DAT5BIT4 BIT3 BIT2 BIT 1 BITOTX TX TX TX TXDAT4 DAT3 DAT2 DAT1 DATOBIT 7 • BIT 0 Transmit Data ByteBIT 7through BIT Owi" be transmitted atthe next byte boundary (LSB first) if the TX CONTROL SEND DATAbit is set. The HDLC will insert all necessary Os. A TX READY interrupt will be generated when a new databyte can be loaded into the TX DATA register. Writing this register will clear the TX READY interrupt.4-30

SSI 73M291 0/291 OAMicrocontro'llerREGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT4HDLC CORXD RXD PTXD PTXWRXD WPTXD TXD PRXDCONTROL 0CTRL1 CTRLO CTRL1 CTRLOHDLCC1 RESET CCIDCRCRXCRC32 RXCRC16 TXCRC32ZERO HDLCCONTROL1PRE10 ENTX C2 0 0 0DIV16 SEND SEND SEND SENDCONTROLCLK ABORT CRC DATA FLAGHDLCC3INVAL INVAL TX RX INVAL ABORT IDLE FLAGSTATUSCRC32 CRC16 UNDERRUN UNDERRUN FLAG DETECT DETECT DETECTHDLCINTC4TX RDY RXRDY TXRDY RX RDY INVAL ABORT IDLE FLAGENABLE IE IE EN EN FLAG IE IE IE IEHDLCINTC5 0 0 0 0 0NEW RX TXSOURCE STATUS READY READYBIT3BIT 2 BIT 1 BITORX DATA C6 RXDAT7 RXDAT6 RXDAT5 RXDAT4 RXDAT3 RXDAT2 RXDAT1 RXDATOTX DATA C7 TXDAT7 TXDAT6 TXDAT5 TXDAT4 TXDAT3 TXDAT2 TXDAT1 TXDATOFIGURE 9: HOLC SFR RegistersICCID 16 Bit CRC X'S + X'2 + X5 + 1FIGURE 10: CCITI TypeThe CRC check field is generated by the transmitter.The computation starts with the first transmitted bitafter the opening flag and stops at the last data bit priorto the frame check sequence bytes, and excludesinserted Os. The CRG generating logic is initialized toall ones. The bits are shifted in and operated on by thegenerating polynomial, X 16 + X 12 + X 5 + 1. During CRCtransmission, the bytes in the CRC generating logic areinverted and transmitted, high order bit first.The receiver also initializes its C RC computation logicto all ones after the beginning flag. Its polynomialgenerator (also X 16 + X12+ X 5 + 1) should see the samevalue as the transmitter's polynomial generator as thelast data bit is received. Note the receiver's polynomialgenerator does not process inserted Os. After the bytesare received in the frame check sequence, a remainderof 1111 0000 1011 1000 (X o through X 15 , respectively)should be detected in the receiver's polynomial generator.If this is not the case, it is assumed that thepreceding frame was in error and an invalid eRe isdeclared.4-31

SSI 73M291 0/291 OAMicrocontrollerREGISTER DESCRIPTION (continued)RESET (option to set)COMPUTEDATAFIGURE 11: CRC 16The CRC check field is generated by the transmitter.The computation starts with the first transmitted bit afterthe opening flag and stops at the last data bit prior to theframe check sequence bytes, and excludes insertedas. The CRC generating logic is initialized to all as. Thebits are shifted in and operated on by the generatingpolynomial, X 16 + X 12 + X 5 + 1. During CRC transmission,the bytes in the CRC generating logic are transmitted,high order bit first.The receiver also initializes its C RC computation logicto all ones after the beginning flag. Its polynomialgenerator (also X 16 + X 12 + X 5 + 1) should see the samevalue as the transmitter's polynomial generator as thelast data bit is received. Note the receiver's polynomialgenerator does not process inserted Os.·Afterthe bytesare received in the frame check sequence, a remainderof 1111 0000 1011 1000 should be detected in thereceiver's polynomial generator. If this is not the case,it is assumed that the preceding frame was in error andan invalid CRC is declared.4-32

SSI 73M291 0/291 OAMicrocontrollerSETDATAIFIGURE 12: 32 Bit CRCThe CRC check field is generated by the transmitter.The computation starts with the first transmitted bitafter the opening flag and stops at the last data bit priorto the frame check sequence bytes, and excludesinserted Os. The CRC generating logic is initialized toall ones. The bits are shifted in and operated on by thegenerating polynomial, X 32 +X 26 +X23 + X22 + X 16 + X 12+ X 11 +X 10 +X8+X7 + X5+X4 + X2+ X+ 1. DuringCRCtransmission, the bytes in the CRC generating logic areinverted and transmitted, high order bit first. The receiveralso initializes its CRC computation logic to allones after the beginning flag. Its polynomial generatorshould see the same value as the transmitter's polynomialgenerator as the last data bit is received. Note thereceiver's polynomial generator does not process insertedOs. After the bytes are received in the framechecksequence,aremainderof11011110101110110010 0000 1110 0011 (Xo) through X 32 , respectively)should be detected in the receiver's polynomial generator.If this is not the case, it is assumed that thepreceding frame was in error and an invalid CRC isdeclared.4-33

SSI 73M291 0/291 OAMicrocontrollerPIN DESCRIPTIONNAME TYPE DESCRIPTIONPSEN 0 Program store enable. This output occurs only during a fetch to externalprogram memory.RESET I Input which is used to initialize the processor.VND GND Negative digital voltage groundOSCIN I Crystal input for internal oscillator, also input for external source.OSCOUT 0 Crystal oscillator output.VPD I Positive digital voltage (+5V Digital Supply)CLKOUn 0 Clock output programmable either OSC/2, OSC/1 or logic O.CLKOUT2 0 Clock output 1.8432 MHz clock for an external UART given an oscillatorfrequency of 11.0592 MHz, 22.1184 MHz, 18.432 MHz, or 13.824 MHz.TXD I Serial input port to 73M2910 from DTE same as RXD UART input.RXD 0 Serial output port of 73M291 0 UART to DTE.PTXCLK I Input clock used to transmit data PTXD.PTXD 0 HDLC Packetizer TX output. This pin can also be programmed to the DTE'sTXD output (clear channel) or the value written into bit 6 of the HDLC controlregister. Connects to modem device TXD.PRXCLK I Input clock used to receive data PRXD.PRXD I Serial input port (from modem device).INT(O)-INT(2) I External interrupt 0,1 and 2.USR1 (0) -USR1 (7) 110 User programmable I/O port.USR2(0) -USR2(7) I/O User programmable 110 port.USR3(0) -USR3(7) 110 User programmable I/O port. If the bank select feature is chosen, USR (7) actsas address bit 17and USR3databit7is ignored. Register BNKSELbit2 (BSEN)enables bank select, bit 1 (BS1) and bit 0 (BSO) select the appropriate bank.USR4(O) -USR4(7) 110 User programmable I/O port also Chip select enable.USR5(0) - USR5(1) 110 General purpose input port, can also be used for wakeup.RD 0 Output strobe activated during a bus read. Can be used to enable data ontothe bus from an external device. Used as a read strobe to external datamemory.WR 0 Output strobe during a bus write. Used as a write strobe to external datamemory.ALE 0 Address Latch Enable output pulse for latching the low byte of the addressduring accesses to external memory.AD(0)-AD(7) I/O Data bus lines-I/O for devices that require multiplexed address and data bus.A(O)-A(15) 0 Address bus lines-output latched address for devices that require separatedata and address bus.NO CONNECTSNo connections, leave open.4-34

SSI 73M291 0/291 OAMicrocontrollerExternal RAM(Movx data, addr)FFhOOhInternal RAMIndirect addressing only(mov@Ri)SFRs direct addressing only(Mov data, addr)IOOhDirect & Indirect addressing(mov data, addr)(mov@Ri)FIGURE 1: Memory MapBANK 3ADDRESS32K -64K96K -128K64K - 96K32K -64KBANKOADDRESSO·32KBANKOADDRESS0-32KBANKOADDRESS0-32K0-32KBANK 1SELECTEDBANK 2SELECTEDBANK 3SELECTEDFIGURE 2: 128K of Bank-Selected Program Memory4-35

SSI 73M291 0/291 OAM icrocontro IlerAddress locations 0008 - OOFF are reserved for future use00080000IUSER3IDIR3I I I I II BNKSEL I USER4I DIR4 I CSEN IIIOOOF0007FIGURE 3: Memory Mapped RegistersF8FFFOBF7E8EFEOACCE708"USER2"DIR2CLKCTRLOFDOPSW07C8coT2CON"HDLCO"HDLC1RCAP2L RCAP2H TL2 TH2"TXC "HSTAT "HIE "HINT "HRXD"HTXDCFC7B880IPBFB7A8IEAFAO98P2SOONSBUFA79F90"USER1"DIR1"IDIR9788TCONTMODTLO TL1 THO TH18F80POSPDPLDPHPeON87" Unique to the SSI 73M2910. There may not be an equivalent function on an 8052.BIT ADDRESSABLEFIGURE 4: 73M2910 SFR Map4-36

SSt 73M291 0/291 OAMicrocontrollerELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSRecommended conditions apply unless otherwise specified.PARAMETERSupply VoltagePin Input VoltageStorage TemperatureRECOMMENDED OPERATING CONDITIONSSupply VoltageOscillator FrequencySupply VoltageOscillator FrequencySupply VoltageOscillator Frequency~Operating TemperatureDC CHARACTERISTICSPARAMETERInput Low VoltageVIL(Except OSCIN, RESET, TEST)Input Low VoltageOSCIN, RESET, TESTVILInput High Voltage VIH(Except OSCIN, RESET, TEST)Input High VoltageOSCIN, RESET, TESTVIHCONDITIONOutput Low Voltage VOL 101 = 3.2 rnA(Except OSCOUT)Output Low Voltage VOLOSC 101 = 1.5 rnAOSCOUTOutput High Voltage VOH loh = -3.2 rnA(Except OSCOUT)Output High Voltage VOHOSC loh = 1.5 rnAOSCOUTInput Leakage Current ilL Vss < Vin < VeeMaximum Power Supply IDD1 22MHzNormal Operation30 pF/pinMaximum Power Supply IDD2 22 MHzIdle ModeRATING-0.5 to +7.0V-0.5 to Vcc +0.5V-55 to + 150°C4.5 to 5.5VDC to 33 MHz4.75 to 5.5VDC to 44 MHz3.0 to 5.5VDC to 22 MHz-40 to +85°CMIN NOM MAX UNIT-0.5 0.2 Vee - 0.1 V-0.5 0.2 Vcc V0.5 Vcc Vee + 0.5 V0.7 Vce Vee + 0.5 V0.45 V0.7 VVee - 0.45VVee - 0.7V±10 IlA40 rnA10 rnAI4-37

SSI 73M291 0/291 OAM icrocontro IlerELECTRICAL SPECIFICATIONS (continued)DC CHARACTERISTICSPARAMETERMaximum Power Supply 1003Power Down ModeCONDITIONPin Capacitance CIO @1 MHzACTIMINGOscillator FrequencyOscillator PeriodALE Pulse WidthAddress Valid To ALE lowAddress Valid ALE lowALE low to PSEN lowPSEN Pulse width lowPSEN Low to Valid Inst InAddress to Valid Inst InInput Instr Hold-PSEN HiPSEN Instr Float-PSEN HiFOSCTOSCTLHLLTAVLLTLLAXTLLPLTPLPHTPLIVTAVIVTPXIXTPXIZPSEN Low to Address HIZ TPLAZRD Pulse WidthWR Pulse WidthRD Low to Vlaid Data InData Hold After RDData Float After RDALE Low to Valid Data InALE low to RD or WR lowData Valid to WR lowData Hold After WR HiRD low to Address FloatTRLRHTWLWHTRLDVTRHDXTRHDZTLLDVTLLWLTQVWXTWHQXTRLAZMIN NOM MAX UNIT10 /-1A10 pF0 22.2 MHz45 ns2TOSe -10TOSCTOSe -10TOSe -103TOSe - 203TOSe - 50STOSe -50nsnsnsnsnsnsns0 ns6TOSe - 206TaSe - 2020+ ns10 nsSTaSe - 50nsnsns0 ns20+ ns8TaSe -50ns3TOSe - 20 3TOSe +20 nsTOSCrose -10nsns10 ns4-38

SSI 73M291 0/291 OAM icrocontro IlerAC TIMING (continued)The SSI 73M2910 timing is very similar to the 8051except in AD(7:0), the multiplexed address data portknown as port 0 in the 8051. Its timing has been alteredsomewhat to allow more address setup time forperipheral program ROM and memory mappedperipherals. This is important at 22 MHz operation.The 8052 has a "dead" cycle of one oscillator periodbetween the time PSEN goes high, indicating that theinstruction ROM will release the AD(7:0) bus, to thetime the processor will assert address on the AD(7:0)bus. This dead time of one whole oscillator cycle hasbeen shortened to approximately 15 ns afterthe PSEN(or RD) signal is sensed to be high.The timing specification for TPXIZ and TRHDZ of amaximum of 20 ns can be violated at the expense ofincreased operating current. The SSI 73M2910 willbegin asserting the AD(7:0) bus approximately 20 nsafter PSEN or RD go high. This should be ample timeforthe control signals in the peripheral device to turn offtheir pad drivers. If the peripheral device does notrelease the bus promptly, there will be a short timewhere there is contention on the AD(7:0) bus betweenthe processor and peripheral. This should not preventproper operation, but it will increase operating currentslightly.I4-39

SSI 73M291 0/291 OAMicrocontrollerUSER INTERFACESSI 73D2248A DEVICE SETTELEPHOI'IIE INTERFACEfAMRCDAAOHHSAi ...-..,.;DCD ~~~ ..EXCLK ~DTR ...RTS ..TXD_ ...DSR ....RXCLK ...TXCLKfAMRCDAA ..OH TXA -RS'- - ...~~ RXA ...~ DCD~ CTS- RXD'- --~ EXCLK~ DRT~ RTSTXDL.. _~ DSR~ RXCLK- TXCLK,.. TXAL..r- RXA...It. AGOIt.~.. POWERHOOKIa._"" AUXt.._~ RING,---.---RINGAUXHOOKPOWERAG1AGOFIGURE 13: Modem Block Diagram4-40

~~~~~ ~,..1~,..1~v~SSI 73M291 0/291 OAMicrocontrollerVCC(~R~ 1R ~)I)I2.4KR33-A. A2.4KrI~D~)I)ID7R39-A. A TD ~)I)I2.4KD8R34 RD ~)I)I...,...,2.4KrJD91' 3 CD1 ••..1)1)1~v2.4KrJD101'~AAA ~)I)I2.4K'"ID11.A.R;Z OH ~)I)IrI24KD12R38 HS.A. A~)I)I,..12.4KIfAMi:asAli.a:

Cl.ol~ .o.l~FIAl 052.okAl.o611kTXA ~---18AXA-rn---2MOIISUM""2s'~-'23Cl021000pF+SVDlOOPXMOUTXMOUTRl09511**Cl07 '\ AlII38.4 k390pF+5VORJll3: _. en(')-Ow""" ......Ss:::IN"CD"""....L2.0--.....CDN"""CD....L0l>CUTOFF~1:..I\)C104.0.1 ~FCl0SCl.o6Al0?DGND+5 VA.. SVDR11356kJl02~RJlRJ2il~ III ~I ~RJSRJ6RJllS.l KAINGRING+svo330Rl14C112Rl0833~FNOlI-POlARIZED CAPACITORSO112WAGND150101TI1119lN914** The tracks to the wires within the dashed lines should be as short as possible.FIGURE 15: Telephone Interface

551 73M291 0/291 OAM icrocontro Iler>NV(;jOveer;::~N~ve;:K =t=~ ~~ s~jJCONTFO...lERHGND20pFe,DI1e!~20pF~~rru--s~IRll~f=K\I !ITATXDlONGI,."OSCINUSR3.1 WRUSR3.0 AD" USR2.6USR2.5 A14USR2.46DUSR2.~'"USR2.2-rr-USR2.1 A10USA2.DAll.,USA1.?USR1.6.~~USR1.3..::USR1.2USA1.5'0 ,A3A2YOINT, '7INTO'8 PRXDPTXD::PRXCLK~e ~ --tr USR5.0...::::!!: USR5.1r-US~.O~ us~.,7:JM2S100000 ~r~,------------------~ClK'oull-,:-:-,--------------PE~:~rIT---«> GNO~~88·;_'--_ -.::_ -.::_-.::_-_-_-_-.::_-_-1-+-_-_-_-_-_-_-_-_-_-_::,. A1317 A12,. "0AB,AS12 A7AS" AOM:i-------If+_""*~;-: __--..... 1- ADO· AD7ADO r.;.,:~-----_--If+--"D"-O ---.....USR4.7L-",-,=-----'t-"!t:.-======ilj=~---rr::"P=D'I~~i'Owe!.~All 120'D'A1A2 0'D'~~A3 0, D'"D'~ ,D'..,.A7 AS ~ AS~."~A14.,62D22CEFIGURE 16A: SSI73D2248A Modem System Interconnect - Front End4-43

~T ________________________________~SSI 73M291 0/291 OAMicrocontroller1 ~;~ l~eLKOUT2 -----------------.., ~:6 J~----~--~~v~~WR--------------.-----------------~--..,~----------~~---------------_r_,ALE--++------t-! IGNO~ R4~ 10K~U3'-+---~-o In~-----":-

SSI 73M291 0/291 OAMicrocontroller100-Pln PGA (For developement purposes only; not a production package.)BOND PIN# SIGNAL NAME BOND PIN # SIGNAL NAMEPROPRO1 B2 NO CONNECT 37 M7 WR2 B1 NO CONNECT 38 L7 ALE3 C1 USR26 39 N7 004 C2 USR27 40 N8 015 02 USR25 41 M8 026 01 USR24 42 L8 037 E2 USR23 43 N9 048 E1 USR22 44 M9 D59 F3 USR21 45 N10 0610 F2 USR20 46 M10 0711 F1 VPO 47 N11 VPO12 G2 GNO 48 N12 AO13 G2 USR47 49 M11 NO CONNECT14 G1 USR46 50 N13 NO CONNECT15 H1 USR45 51 .. M12 NO CONNECT16 H2 USR44 52 M13 NO CONNECT17 H3 USR43 53 L12 NO CONNECT18 J1 USR42 54 L13 A119 J2 USR41 55 K12 A220 K1 USR40 56 K13 A321 K2 USR30 57 J12 A422 L1 USR31 58 J13 A523 M1 USR51 59 H11 A624 L2 NO CONNECT 60 H12 A725 N1 NO CONNECT 61 H13 A826 M2 NO CONNECT 62 G12 A927 N2 NO CONNECT 63 G11 A1028 M3 USR50 64 G13 A1129 N3 USR32 65 F13 A1230 M4 USR33 66 F12 A1331 N4 USR34 67 F11 A1432 M5 USR35 68 E13 A1533 N5 USR36 69 E12 PSEN34 L6 USR37 70 013 RESET35 M6 GNO 71 012 GND36 N6 RD 72 C13 OSCOUTI4-45

SSI 73M291 0/291 OAMicrocontroller10o-Pin PGA (continued)BOND PIN# SIGNAL NAME BOND PIN #PROPRO73 813 OSCIN87 8774 C12 NO CONNECT88 C775 A13 NO CONNECT89 A776 812 NO CONNECT90 A677 A12 CLK20UT91 8678 811 VPD92 C679 A11 CLK10UT93 A580 810 TXD94 8581 A10 RXD95 A482 89 PTXCLK96 8483 A9 PTXD97 A384 C8 PRXCLK98 A285 88 PRXD99 8386 A8 INT2100 A1SIGNAL NAMEINT1INTOGNDUSR10USR11USR12USR13USR14USR15USR16USR17NO CONNECTNO CONNECTNO CONNECT100-Pin PGA (For developement purposes only; not a production package.)NMLKJHGFEDCBA2 3 4 5 6 7 8 9 10 11 12 13FIGURE 17: 100-Pln Plug-In Package4-46

SSI 73M291 0/291 OAMicrocontrollerPACKAGE PIN DESIGNATIONS(Top View)N/CN/CN/CA1A2A3A4A5A6A7A8A9A10A11A12A13A14A15PSENRESETVNDOSCOUTOSCINN/CN/C75 N/C74 N/C73 USR5172 USR3171 USR3070 USR4069 USR4168 USR42USR43USR44USR45USR46USR47VNDVPDUSR20USR21USR22USR23USR24USR25USR26USR27N/CN/CI100-Lead TQFPCAUTION: Use handling procedures necessaryfor a static sensitive component.4-47

SSI 73M291 0/291 OAMicrocontrollerPACKAGE PIN DESIGNATIONS(Top View)NICNICNICNICNlCAlA2A3A4ASASA7ASA9A10AllA12A13A14A15PSENRESETVNDOSCOUTOSCINNICNICCLK20UTNICNlC8m~s;~~-a;~~;;gm~s:;~~:;~S5co~ 807978n767514731211106968fi1666564636261liD595851565554535251N/CN/CUSR50N/CUSR51USR3lUSR30USR40USR4lUSR42USR43USR44USR45USR4SUSR47VNDVPDUSR20USR2lUSR22USR23USR24USR25USR26USR27N/CN/CN/CN/CN/C100-Lead QFPCAUTION: Use handling procedures necessaryfor a static sensitive component.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheetis current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA92680-7022 (714) 573-6000, FAX (714) 573-69141194- rev.4-48 ©1994 Silicon Systems, Inc.

_.f.(iJkon¥}rJfonj®Abridged Version SSI73M2918/2918APlug and Play0' Microcontroller and UARTA TDK Group CompanyDESCRIPTIONThe SSI 73M2918 is a combination of the SSI73M2910 modem microcontroller, a virtual 550 UART,and built-in hardware to support the Plug and Play ISAstandard, implemented in Silicon Systems' advancedCMOS process. The 8-bit processor has the sameattributes as the 8052 including instruction cycle time,UART, timers, interrupts, 256 bytes of on-chip RAMand programmable 110. The virtual 550 UART utilizesproprietary technology, which results in a completeemulation of the industry standard 550 UART, and addssignificant features. The 550 UART emulator providesfamiliar 550 functions to the PC and replaces the seriallink between the PC and the dedicated processor witha parallel data interface. The architecture results in ahigh-performance system solution that is optimized forlow power applications.The 73M2918 also includes the user friendly HDLCpacketizer that is available in the 73M2910. It has aserial 110, hardware support for 16- and 32-bit CRC,zero insertldelete control, a dedicated interrupt and aclear channel mode for by-passing the packetizer.(continued)MFEATURESijj liil line], 11;11 le] II8052-compatible instruction setVirtual 550 UARTJanuary 1995Dedicated Plug and Play ISA bus hardware33 MHz 73M2918, 44 MHz 73M2918A operationOperates at 3.3V and 5VHDLC Support logic (Packetizer, 16 and 32CRC, zero ID)24 pins for user programmable I/O ports8 pins programmable chip select logic formemory mapped peripheral eliminating gluelogic3 external interrupt sources (programmablepolarity)16 dedicated latched address pinsMultiplexed data/address busInstruction cycle time identical to 8052Buffered oscillator (or OSC/2, OSC/1.5) outputpin(continued)IBLOCK DIAGRAM0195 4-49

SSI 73M2918/2918APlug and PlayMicrocontroller and UARTDESCRIPTION (continued)Other features include additional user programmable1/0 with programmable bank select and chip selectlogic, designed to eliminate board level glue logic. Italso includes two general purpose input pins withprogrammable wakeup capability.For devices that require non-multiplexed address anddata buses, eight latched outputs for the low byte ofthe address are available.The 73M2918 has two extra interrupt sources, anexternal interrupt and an HDLC interrupt. The HDLCinterrupt has two registers associated with it: the H DLCinterrupt register which is used to determine the sourceof the interrupt, and the HDLC interrupt enable registerthat enables the source of the interrupt.The state of the external interrupts can be read througha register allowing the interrupt pins to be used asinputs. The interrupt pins INTO and INT1 can be eithernegative edge, positive edge or level triggered. INT2pin is always edge triggered.Two buffered clock outputs have been added to supportperipheral functions such as UARTs, modems andother clocked devices. The main internal processorclock frequency can be divided by 2 for powerconservation in functional modes that only require halfthe clock speed.Additional internal special function registers are usedfor firmware control over the HDLC Packetizer, theclocks and the programmable 1/0 ports.The processor's timing has been altered slightly toallow more address setup time for slower peripheralprogram ROM and memory mapped peripherals. Thiscan offer the system designers an advantage whenusing higher oscillator frequencies.For low power applications the 73M2918 operates from3 to 5 volts at 22 MHz and supports two powerconservation modes: Idle and power-down. In thepower-down state the total current consumption is lessthan 1 JlA at room temperature.This device is offered in a small form factor 1 ~O-leadTOFP package and a 100-lead OFP package.DEVELOPER'S NOTEThe SSI73M2918/2918A is also available in a 1 ~O-pinPGApackageforsystemdevelopers. The PGApackageis more convenient and reliable for developmentemulation systems than the other package styles.Emulation systems for the SSI 73M2918/2918A areavailable through Signum Systems,171 E. ThousandOaks Blvd., # 202, Thousand Oaks, CA 91360,(805) 371-4608.8052 REFERENCEThis document will describe the features unique to theSSI 73M2918/2918A. Please refer to an 8052Programmer's Guide, Architectural Overview andHardware Description for details on the SSI 73M291812918A core processor instruction set, timers, UART,interrupt control, and memory structure.FEATURES (continued)1.8432 MHz UART clock available if crystal frequencies11.0592 MHz, 22.1184 MHz, 18.432 MHz,or 13.824 MHz are usedBank select circuitry to support up to 128K ofexternal program memoryAvailable in a 1 ~O-Lead OFP packageFor a complete SSI 73M2918/2918A data sheetcontact your local Silicon Systems sales office. Seelisting of sales offices in Section 11.Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use forfinal design.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheetis current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1994 Silicon Systems, Inc. 4-50 0195

SSI73M2231200 Baud FSK ModemDecember 1993DESCRIPTIONThe SSI 73M223 modem device receives and transmitsserial and binary data over existing telephonenetworks using Frequency Shift Keying (FSK). Itprovides the filtering, modulation, and demodulation toimplement a serial, asynchronous data communicationchannel. The SSI 73M223 employs the CCITTV.23 signaling frequencies of 1302 and 2097 Hz,operating at 1200 baud, and is intended for half duplexoperation over a two-line system.The SSI 73M223 provides a cost-effective alternativeto existing modem solutions. It is ideally suited for R.F.data links, credit verification systems, point-of-saleterminals, and remote process control.CMOS technology ensures small size, low-power consumptionand enhanced reliability.FEATURES• Low cost FSK Modem• 1200 baud operation• CMOS switched capacitor technology• Built-in self-test feature• On-chip filtering, and Modulation/Demodulation• Uses CCITT V.23 frequencies• On chip crystal oscillatorI• Low power/High reliability• 16-pin plastic packagesBLOCK DIAGRAMPIN DIAGRAMVDDRXACAPRXFFilTESTIX1 SYN VSSTXAClKOSC2OSC1TXDSYNRXF4.I.3 CAP~~VDDVSS1293 - rev. 4-51[ CAUTION: Use handling procedures necessary Ifor a static senSItive component. I

SSI73M2231200 Baud FSK ModemFUNCTIONAL DESCRIPTIONThe SSI 73M223 has four main functional sections:timing, transmit, receive, and test. Each section of thechip will be individually described below.TIMINGThe timing section contains the oscillator (OSC) andrandom logic which generates digital timing signalsused throughout the chip. The time base can be derivedfrom 3.18 MHz crystal or an external digital input.The digital timing logiC divides the oscillator frequencyto give a 1200 Hz output than can be used for systemtiming. The signaling frequencies are 1302 Hz for logic"1" and 2097 Hz for logic "0." The modem will operatewith clock inputs from 330 kHz to 3.3 MHz. However,the signaling frequencies and the system timing will bedirectly proportional to the difference in clock frequency.TRANSMITIERThe SSI 73M223 transmitter consists of a programmabledivider that drives a coherent phase frequencysynthesizer. The programmable divider is digitally controlledvia the Data Input pin (TXD). The output of thedivider clocks a 16 segment phase coherent frequencysynthesizer. A sine wave is constructed by eightweighted capaCitors which are the inputs to a high passfilter. The synthesized signal is output directly to thetransmit pin TXA. The transmit Signal can be disabledby using the digital control pin TX.The demodulator is used to detect a received mark orspace.The synchronization for sampling the digital output atRXD is derived from a digital phase locked loop. Thephase locked loop is clocked at 16 times the bit ratewith a maximum lock period of 8 clocks to lock on thedata output signal. The output is nominally 1200 Hz,but is resynchronized to the center of the data bit oneach data transition.SELF TEST MODEThe SSI 73M223 features an autotest mode whichprovides easy field test capability of the chip's functionality.The modem is placed in the test mode by takingthe test pin high. In the test mode the Data Input pin isdisconnected and the programmable divider is drivenby a pseudo random PN sequence generator and thetransmitter's output is connected to the receiver's input.The input data to the programmable divider isdelayed by the system delay time and compared to thedigital output on sync transitions. If the detected datamatches the delayed input data from the PN sequencecounter, the SSI 73M223 is properly functioning asindicated by RXD low. A high on the RXD pin indicatesa functional problem on the SSI 73M223.RECEIVERThe SSI 73M223's receiver is comprised of threesections: the input bandpass filter, the synchronizationloop, and the demodulator.The input bandpass filter is a four pole Butterworthfilter, implemented using switched capacitor technology.This filter reduces wideband noise which significantlyimproves data error rates. The SSI 73M223 canbe configured with the bandpass filter in series with thereceiver by setting FIL = 1 and inserting the receivedsignal at RXF. The bandpass filter can be deleted fromthe system by setting FIL = 0 and inputting the receivedsignal through RXA.4-52

------------~--~~~~-~~-------~-~--~~~SSI73M2231200 Baud FSK ModemPIN DESCRIPTIONPIN NO.PIN NAMEDESCRIPTION1 VDD2 RXA3 CAP4 RXF5 Fil6 TEST7 TX8 VSS9 SYNC10 SYN11 RXD12 TXD13 OSC114 OSC215 ClK16 TXAPositive Supply Voltage. Bypasses to Vss with 0.1 f.lF capacitor.Receive Analog Input. Analog input from the telephone network.Capacitor. Connect a 0.1f.lF capacitor between Pin 3 and ground (VSS).Filtered Receive Analog InputAnalog Input Control. A logical 1 selects the filtered input. A logical 0 selectsthe non-filtered input.Self-Test Mode Control. Normal operation when a logical O.A logical 1places the device into the self-test mode. A low appears at RXD, to indicatea properly fun?tioning device.Transmitter Control. A logical 0 selects transmit mode. A logical 1 selectsa stand-by condition forcing TXA to VDD/2 VDC.Ground~ ~~~.~ ..-.~~-~-~Synchronous Clock Output. Digital output synchronized with the 1200 bitlsreceived data and used to sample the received eye pattern.Sync Disable. A logical 1 input disables the phase locked signal from thereceived data and locks it to the 1200 Hz reference. Logic 0 enables Rec PlL.- ---Receiver Digital OutputTransmitter Digital InputCrystal Input (3.1872 MHz) or External Clock Input-- ----------------------------Crystal Return-~ -1200 Hz Squarewave Output. Can drive up to 10 CMOS loads.Transmitter Analog OutputIELECTRICAL SPECIFICATIONSRecommended conditions apply unless otherwise specified.ABSOLUTE MAXIMUM RATINGSOperation outside these rating limits may cause permanent damage to this device.PARAMETERPower Supply Voltage (VDD-VSS)Analog Input Voltage at RXAAnalog Input Voltage at RXFRATING14 V-_._------"----_._-_._-------------- 0.3 to VDD V~- r-----~-~----~-~~-~~- -.-------------- 3 to VDD VDigital Input VoltageVSS - 0.3 to VDD + 0.3 V-- ----- ------.----------.--~~--~---Storage Temperature Range - 65 to + 150°C--~- .-----~-~~---Operating Temperature Range - 25 to + 70°C.--"--- ----_._.- -_._._-------~----lead Temperature (10 secs soldering) 260°C4~53

SSI73M2231200 Baud FSK ModemELECTRICAL CHARACTERSITICSUnless otherwise specified, 4.5

SSI73M2231200 Baud FSK ModemAPPLICATION INFORMATIONThe SSI73M223 modem chip allows low cost communicationsin a private network, utilizing twisted pairtelephone wires. This chip is the prime choice of thosedesigners who require an efficient, high performancemodem solution for dedicated private networks, HDXdial-up and other specialized applications. Suchapplications include credit verification systems, pointof-saleterminals, remote process control, privatedata links and acoustic modem designs. No microprocessorsor external adjustments are necessary withthis device.Utilizing a crystal input of 3.1872 MHz, the SSI73M223 is a 1200 Baud, FSK modem. The signalingfrequencies generated are 1302Hz for a logic "1" and2097Hz for a logic "0." Crystals with frequenciesvarying between 330 kHz to 3.3 MHz or higher can beused. The baud rate and signaling frequencies varylinearly with variation in crystal frequency.A typical implementation on the SSI73M223 is shownin the figure below. An S81 73M1550 UART receivesdata to be transmitted from a microprocessor bus.The UART sends the data in a serial format to the SSI73M223 modem after inserting the necessary startand stop bits. The modem transmits this data to the farend via the TXA pin. Full-duplex operation can beimplemented by utilizing separate transmit and receivecircuits. A USART can be used instead of aUART if synchronous operation is desired. With synchronousoperation, a USART uses the modem'sSYNC signal for timing to sample the received data,and the modem's ClK signal to send data clock to betransmitted.ITXA[BE~> 0.1 ).IF''L3.187~1MHz Y1 ~ R1~ 1Mn.J...C11: 30pF 1: 30pF= Typ. = Typ.VOOQ vgo U1R2 ~1 VOOTXA~100K ~ C4",~ I ----1. RXA CLK~ci" 3 CAP OSC2~II C51 ).IFrrl ~> C3:;;"100K -l.0.1 ).IF'::;".I 4 RXF OSC1 13L--.§. FIL TXO12RXO 11TEST8 VSS SYNC ~I 73M223R3 :> rin< SYN ~.---HU1 01--4- vee 00 S~ 5GB 01 2~ OSR 02 3T~ CTS 03 4245MRD4~ OTR 05 6227 IRTS 06~ AD 07 8209 NA1SIN19A2 SOUT ~ T18INTRPT11 CS2XIN ~ EXOUT ~---1L VSS14WR R~~D73M1550FACE"---SSI 73M223 TYPICAL APPLICATION4-55

SSI73M2231200 Baud FSK ModemPACKAGE PIN DESIGNATIONS(Top View)VDDRXACAPRXFFILTESTTXVSSTXA2 CLK3 OSC24 OSC15 TXD6 11 RXD7 SYN8 SYNC16-Pin DIP and16-Lead SOLCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONORDER NO.PKG.MARKSSI73M223 16-Pin Plastic DIPSSI 73M223 16-Lead SOL73M223 - CP73M223 - CLSSI 73M223 - CPSSI 73M223 - CLNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69141293 - rev. 4-56 ©1989 Silicon Systems, Inc.

Section 5ANALOG SIGNALLING& SWITCHINGI5

5-0

SSI75T201IntegratedDTMF ReceiverDESCRIPTIONFEATURESOctober 1991The 881 75T201 is a complete Dual-Tone Multifrequency(DTMF) receiver detecting a selectable groupof 12 or 16 standard digits. No front-end prefiltering isneeded. The only external components required are aninexpensive 3.58 MHz television "colorburst" crystal(for frequency reference) and two low-tolerance bypasscapacitors. Extremely high system density ismade possible by using the clock output of a crystalconnected 881 75T201 receiver to drive the time basesof additional receivers. The 881 75T201 is a monolithicintegrated circuit fabricated with low-power, complementarysymmetry M08 (CM08) processing. It requiresonly a single low tolerance voltage supply and ispackaged in a standard 22-pin DIP. (Continued)• Central office quality• NO front-end band-splitting filters required• Single, low-tolerance, 12-volt supply• Detects either 12 or 16 standard DTMF digits• Uses inexpensive 3.579545 MHz crystal forreference• Excellent speech immunity• Output in either 4-bit hexadecimal code orbinary coded 2-of-8• 22-pin DIP package for high system density• Synchronous or handshake interface• Three-state outputsBLOCK DIAGRAMBANDPASS FILTERSIiTIMING ICIRCUITRY I,-------0 CLRDVDV,-------t-------LJ H/B28011MzD2D408EN.01mF01mFIN16331091 - rev. 5-1CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI75T201IntegratedDTMF ReceiverDESCRIPTION (Continued)The SSI 75T201 employs state-of-the-art circuit technologyto combine digital and analog functions on thesame CMOS chip using a standard digital semicondutorprocess. The analog input is preprocessed by60 Hz reject and band splitting filters and then hardlimitedto provide AGC. Eight bandpass filters detectthe individual tones. The digital post-processor timesthe tone durations and provides the correctly codeddigital outputs. Outputs interface directly to standardCMOS circuitry, and are three-state enabled to facilitatebus-oriented architectures.ANALOG INCRYSTAL OSCILLATORThe SSI 75T201 contains an onboard inverter withsufficient gain to provide oscillation when connected toa low-cost television "colorburst" crystal. The crystaloscillator is enabled by tying XEN high. The crystal isconnected between XIN and XOUT. A 1 MQ 10%resistor is also connected between these pins. In thismode, ATB is a clock frequency output. OtherSSI 75T201 's may use the same frequency referenceby tying their A TB pins to the A TB of a crystal connecteddevice. XIN and XEN of the auxiliary devicesmust then be tied high and low respectively. Twentyfivedevices may run off a single crystal-connectedSSI 75T201 as shown in Figure 2.This pin accepts the analog input. It is internally biasedso that the input signal may be AC coupled. The inputmay be DC coupled as long as it does not exceed thepositive supply. Proper input coupling is illustrated inFigure 1.IIIIIVINVP:IIII.OlmF I ->1~Analog In I Q.IIIII!FIGURE 1: Input Couplingvpf-ATBr--- 17- 17I!Up to 25 Devices~DF~AA~XIN YYV XOUTvp15 14XENSSI75T201 16-15XIN Connected to VpSSI75T201XEN16f---VNDFIGURE 2: Crystal Connections5-2

551 75T201IntegratedDTMF ReceiverH/B28This pin selects the format of the digital output code. When H/B28 is tied high, the output is hexadecimal. Whentied low, the output is binary coded 2-of-8. The table below describes the two output codes.Hexadecimal Binar~ Cod~d 2-of-8Digit 08 04 02 01 Digit 08 04 02 011 0 0 0 1 1 0 0 0 02 0 0 1 0 2 0 0 0 13 0 0 1 1 3 0 0 1 04 0 1 0 0 4 0 1 0 05 0 1 0 1 5 0 1 0 16 0 1 1 0 6 0 1_~ -- 1 07 0 1 1 1 7 1 0 0 08 1 0 0 0 8 1 0 0 19 1 0 0 1 9 1 0 1 00 1 0 1 0 0 1 1 0 1* 1 0 1 1 * 1 1 0 0# 1 1 0 0 # 1 1 1 0A 1 1 0 1 A 0 0 1 1B 1 1 1 0 B 0 1 1 1C 1 1 1 1 C 1 0 1 1D 0 0 0 0 D 1 1 1 1ITABLE 1: Output CodesIN1633When tied high, this pin inhibits detection of tone pairscontaining the 1633 Hz component. For detection of all16 standard digits, IN1633 must be tied low.OUTPUTS 01, 02, 04, 08 and ENOutputs D1 , D2, D4, and D8 are CMOS push-pull whenenabled (EN high) and open circuited (high impedance)when disabled by pulling EN low. These digitaloutputs provide the code corresponding to the detecteddigit in the format programmed by the H/B28 pin.The digital outputs become valid after a tone pair hasbeen detected and they are then cleared when a validpause is timed.OV and CLROVDV signals a detection by going high after a valid tonepair is sensed and decoded at the output pins D1, D2,D4, and D8. DV remains high until a valid pause occursor the CLRDV is raised high, whichever comes first.INTERNAL BYPASS PINS, S1, S2Inorderforthe SSI75T201 DTMF Receivertofunctionproperly, these pins must be bypassed to VNA with0.01 /J-F ±20% capacitors.5-3

--------------~----~-------SSI75T201IntegratedDTMF ReceiverPOWER SUPPLY PINS, Vp, VNA, VNDThe analog (VNA) and digital (VND) supplies are broughtout separately to enhance analog noise immunity onthe chip. VNA and VND should be connected externallyas shown in Figure 3.+-==- 12Vr- =10%6SSI75T20113 4Row 0ColO Coil Col 2 Col 3~ G G GRow 1 G G G ~Row 2 L2J G G GRow 3 D G G GNOTE: Column 3 is for special applicationsand is not normally used in telephone dialing.FIGURE 4: DTMF Dialing MatrixDETECTION FREQUENCYN/C PINSFIGURE 3: 12V SystemThese pins have no internal connection and may be leftfloating.Low Group foRow 0 = 697 HzRow 1 = 770 HzRow 2 = 852 HzRow 3 = 941 HzHigh Group foColumn 0 = 1209 HzColumn 1 = 1336 HzColumn 2 = 1477 HzColumn 3 = 1633 HzELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGSOperation above absolute maximum ratings may damage the device. All SSI75T201 unused inputs must beconnected to Vp or VND, as appropriate.PARAMETERRATINGDC Supply Voltage - Vp Referenced to VNA, VND +16VOperating Temperature-40 to +85°C Ambient--- ----- --Storage Temperature -65 to + 150°CPower Dissipation (25°C)Input Voltage (All inputs except ANALOG IN)1W(VP+ 0.5V) to (VND -0.5V)- --.-------- --ANALOG IN Voltage (Vp + 0.5V) to (Vp - 22V)- -----.-----~-------DC Current into any Input±1.0 rnALead Temperature - Soldering, 10 sec. 300°C--------------5-4

551 75T201IntegratedDTMF ReceiverELECTRICAL CHARACTERISTICS(-40°C ~ Ta ~ +85°C, Vp - VND = Vp - VNA = 12V ± 10%)PARAMETERCONDITIONSMINTVP MAX UNITSFrequency Detect Bandwidth± (1.5+2 Hz)±2.3 ±3.0 %of foAmplitude for Detectioneach tone-24+6 dBm ref.to 600nTwist ToleranceTwistHigh Tonelow Tone-8+4 dB60 Hz ToleranceDial Tone Tolerance"precise" dial tone2 Vrmsa dB*Talk Off M ITEl tape #CM 72902 hitsDigital Outputs"a" level, 750 JlA loadVNDVNo+0.5V(except XOUT)"1" level, 750 JlA loadVp-O.5VpVDigital Inputs"0" levelVNO** V(except H/B28, XEN)"1" level***VpVDigital Inputs"a" level. H/B28, XEN "1" levelVNOVp-1VNo+1VpVVIPower Supply Noisewide band25 mVp-pSupply Current Ta = 25°CVP - VNA = VP - VND = 12V±10%Noise Tolerance M ITEl tape #CM 729029 50 mA------12 dB*I nput Impedance Vp ~ VIN ~ Vp - 22100 kQI15 pF--------* dB referenced to lowest amplitude tone** VND + 0.3(Vp - VNO)*** Vp - 0.3(Vp - VNO)TIMING CHARACTERISTICS(-40°C ~ Ta ~ +85°C, Vp - VNO = Vp - VNA = 12V ± 10%)PARAMETERCONDITIONSMINTVP MAX UNITStvTone Detection Time2025 40 mstslh Data Overlap of DV ClRDV = VNO, EN = VpRising Edge7JlStpPause Detection Time2532 40 mstdvTime between end ofTone and Fall of DV4045 50 ms5-5

SSI75T201IntegratedDTMF ReceiverTIMING CHARACTERISTICS (Continued)PARAMETERCONDITIONSMIN TYP MAX UNITStshlData overlap of DVFalling Edgetphl Prop. Delay: Rise of CI = 300 pFCLRDV to fall of DV Measured at 50% pointsOutput Enable TimeCI = 300 pF, RI = 10KMeasured from 50% pointof Rising Edge of EN tothe 50% point of the dataoutput with RI toopposite rail.Output Disable Time CI = 300 pF, RI = 1K,!:N= 1VMeasured from 50% pointof Falling Edge of EN totime at which output haschanged 1 V with RI toopposite rail.Output 10-90%Transition TimeCI = 300 pF4 4.56 4.8 mst-----~-~~ ---~-.----1 IlS1 IlS-_._------1 IlS1 IlSANALOG INPUTTONE BURST...--___ -+-_..:..J-+-,j.- tshl01 , 02, 04, 08 I P---ts'h-~~~---~~~F----~----~ovtphl~ ~CLROV __________________ ---1-D_...I-.-___ _FIGURE 5: Timing Diagram5-6

SSI75T201IntegratedDTMF ReceiverAPPLICATION INFORMATIONTELEPHONE LINE INTERFACEIn applications that use the SSI 75T201 to decodeDTMF signals from a phone line, a DAA (Direct AccessArrangement) must be implemented. Equipment intendedfor connection to the public telephone networkmust comply with and be registered in accordance withFCC Part 68. For PBX applications refer to EIA StandardRS-464.Some of the basic guidelines are:1) Maximum voltage and current ratings of theSSI75T201 must not be exceeded; this calls for protectionfrom ringing voltage, if applicable, which rangesfrom 80 to 120 volts RMS over a 20 to 80Hz frequencyrange.2) The interface equipment must not breakdown withhigh-voltage transient tests (including a 2500 volt peaksurge) as defined in the applicable document.3) Phone line termination must be less than 2000. DCand approximately 6000. AC (200-3200 Hz).4) Termination must be capable of sustaining phoneline loop current (off-hook condition) which is typically18 to 120 rnA DC.5) The phone line termination must be electricallybalanced with respect to ground.6) Public phone line termination equipment must beregistered in accordance to FCC Part 68 or connectedthrough registered protection circuitry. Registrationtypically takes about six months.Figure 6 shows a simplified phone line interface usinga 6000. 1:1 line transformer. Transformers speciallydesigned for phone line coupling are available frommany transformer manufacturers.Figure 7 shows a more featured version of Figure 6.These added options include:1) A 150-volt surge protector to eliminate high voltagespikes.2) A Texas Instruments TCM1520A ring detector,optically isolated from the supervisory circuitry.3) Back-to-back Zener diodes to protect the DTMF(and optional multiplexer Op-Amp) from ringer voltage.I4) Audio multiplexer which allows voice or other audioto be placed on the line (a recorded message, forexample) and not interfere with incoming DTMF tonedetection.An integrated voice circuit may also be implementedfor line coupling, such as the Texas InstrumentsTCM1705A, however, this approach is typically moreexpensive than using a transformer as shown above.TIP :JRINGII1:1600z,._-----l ANALOGINPUTSSI75T201FIGURE 6: Simplified Interface::u:: 1SOVFIGURE 7: Full Featured Interface5-7

551 75T201IntegratedDTMF ReceiverPACKAGE PIN DESIGNATIONS(TOP VIEW)01H/B28ENVNOIN1633VpN/CN/C8182N/C. 1 22 022 21 043 20 084 19 CLROV5 18 OV6 17 ATB7 16 XEN8 15 XIN9 14 XOUT10 13 VNA11 12 ANALOG IN22-Pin DIPCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONSSI75T20122-Pin Plastic DIPORDER NO.75T201 - IPPKG.MARK75T201 - IPNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and 'trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing ordersSilicon Systems, Inc., 14351 Myford Road, Tustin, CA ~2680-7022, (714) 573-6000, FAX: (714) 573-69141091 - rev. 5-8 ©1989 Silicon Systems, Inc.

SSI 75T202/2035V Low-PowerDTMF ReceiverDESCRIPTIONFEATURESOctober 1991The SSI 75T202 and 75T203 are complete Dual-ToneMultifrequency (DTMF) receivers detecting a selectablegroup of 12 or 16 standard digits. No front -endpre-filtering is needed. The only externally requiredcomponents are an inexpensive 3.58-MHz television"colorburst" crystal (for frequency reference) and abias resistor. Extremely high system density is madepossible by using the clock output of a crystal-connectedSSI75T202 or 75T203 receiver to drive the timebases of additional receivers. Both are monolithicintegrated circuits fabricated with low-power, complementarysymmetry MOS (CMOS) processing. Theyrequire only a single low tolerance voltage supply andare packaged in a standard 18-pin plastic DIP.(Continued)•••••••••••Central office qualityNO front-end band-splitting filters requiredSingle, low-tolerance, 5-volt supplyDetects either 12 or 16 standard DTMF digitsUses inexpensive 3.579545-MHz crystal forreferenceExcellent speech immunityOutput in either 4-bit hexadecimal code or binarycoded 2-of-818-pin DIP package for high system densitySynchronous or handshake interfaceThree-state outputsEarly detect output (551 75T203 only)BLOCK DIAGRAMBANDPASS FILTERSIANALOGIN[-------------0 ED (75T203\TIMINGONLY)CIRCUITRYr-----Q CLRDVATB 0------------,DV1MzCHIP CLOCKS,-------+------LJ HEXlB280102D408ENVpGNOIN16331091 - rev.5-9I CAUTION: use .. h.a. ndling procedures necessaryfor a static sensitive component.

551 75T202/2035V Low-PowerDTMF ReceiverDESCRIPTION (Continued)The 551 75T202 and 75T203 employ state-of-the-artcircuit technology to combine digital and analog functionson the same CM05 chip using a standard digitalsemicondutor process. The analog input is pre-processedby 60-Hz reject and band splitting filters and thenhard-limited to provide AGC. Eight bandpass filtersdetect the individual tones. The digital post-processortimes the tone durations and provides the correctlycoded digital outputs. Outputs interface directly tostandard CM05 circuitry, and are three-state enabledto facilitate bus-oriented architectures.ANALOG INThis pin accepts the analog input. It is internally biasedso that the input signal may be AC coupled. The inputmay be DC coupled as long as it does not exceed thepositive supply. Proper input coupling is illustrated inFigure 1.The 551 75T202 is deSigned to accept sinusoidal inputwave forms but will operate satisfactorily with any inputthat has the correct fundamental frequency with harmonicsless then -20 dB below the fundamental.CRYSTAL OSCILLATORThe 551 75T202 and 75T203 contain an onboardinverter with sufficient gain to provide oscillation whenconnected to a low-cost television "colorburst" crystal.The crystal OSCillator is enabled by tying XEN high. Thecrystal is connected between XIN and XOUT. A 1 Mz10% resistor is also connected between these pins. Inthis mode, ATB is a clock frequency output. Other S5175T202's (or 75T203's) may use the same frequencyreference by tying their ATB pins to the ATB of a crystalconnected device. XIN and XEN of the auxiliarydevices must then be tied high and low respectively.Tendevices may run off a single crystal-connected SSI75T202 or 75T203 as shown in Figure 2.HEX/B28This pin selects the format ofthe digital output code. When HEX/B28 is tied high, the output is hexadecimal. Whentied low, the output is binary coded 2-of-8. The table below describes the two output codes.HexadecimalDigit 08 041 0 02 a 03 0 04 a 15 0 16 a 17 0 18 1 09 1 00 1 0* 1 0# 1 1A 1 1B 1 1C 1 1D 0 002a110a1100110011001 Digit1 1a 21 30 41 50 61 70 81 90 01 *0 #1 A0 B1 C0 DBinary Coded_~-of-808 04 02 010 0 0-- -0--0 0 0 1i---0 0 1 00 1 0 00 1 0 10 1 1 01 0 0 01 0 0 11 0 1 01 1 0 11 1 0 01 1 1 00 0 1 10 1-----1 1--1 0 1 1---------1 1 1 1TABLE 1: Output Codes5-10

551 75T202/2035V Low-PowerDTMF ReceiverVpVpVINVPc:>--( ~.-----I ~Analog In : Q.IIIIIIIGND.01mF ->-H-(,-1~~Analog In : -IIIIIIGNDFIGURE 1: Input CouplingIATBXINXOUT12 11SSI75T202 813XENVpXIN Connected to Vp1312SSI75T202 8XENUp to 1 0 DevicesFIGURE 2: Crystal Connections5-11

SSI 75T202/2035V Low-PowerDTMF ReceiverIN1633When tied high, this pin inhibits detection of tone pairscontaining the 1633 Hz component. Fordetectionof all16 standard digits, IN1633 must be tied low.OUTPUTS 01, 02, 04, 08 and ENOutputs 01, 02, 04, 08 are CMOS push-pull whenenabled (EN high) and open circuited (high impedance)when disabled by pulling EN low. These digitaloutputs provide the code corresponding to the detecteddigit in the format programmed by the HEX/B28pin. The digital outputs become valid after a tone pairhas been detected and they are then cleared when avalid pause is timed.DV and CLRDVOV signals a detection by going high after a valid tonepair is sensed and decoded at the output pins 01,02,04, and 08. OV remains high until a valid pause occursor the ClROV is raised high, whichever is earlier.ED (SSI 75T203 only)The ED output goes high as soon as the 551 75T203begins to detect a OTM F tone pair and falls when the75T203 begins to detect a pause. The 01,02,04, and08 outputs are guaranteed to be valid when OV is high,but are not necessarily valid when ED is high.N/C PINSThese pins have no internal connection and may be leftfloating.DTMF DIALING MATRIXSee Figure 3. Please make note that column 3 is forspecial applications and is not normally used in telephonedialing.ColO Col 1 Col 2 Col 3Row 0 G 0 0 0Row 1 G G G 0Row 2~ G 0 GRow 3 D G G 0FIGURE 3: DTMF Dialing MatrixDETECTION FREQUENCYLow Group foRow 0 = 697 HzRow 1 = 770 HzRow 2 = 852 HzRow 3 = 941 HzHigh Group foColumn 0 = 1209 HzColumn 1 = 1336 HzColumn 2 = 1477 HzColumn 3 = 1633 Hz5-12

~----SSI 75T202/2035V Low-PowerDTMF ReceiverABSOLUTE MAXIMUM RATINGS(Operation above absolute maximum ratings may damage the device. All SSI 7ST202/203 unused inputs mustbe connected to Vp or GND, as appropriate.)PARAMETERDC Supply Voltage - VpOperating TemperatureStorage TemperaturePower Dissipation (25°C)Input Voltage (All inputs except ANALOG IN)ANALOG IN VoltageDC Current into any InputLead Temperature - Soldering, 10 sec.RATING+7V-40°C to +8S o C Ambient-65°C to + 150°C- --_.- --~6SmW(Vp + .SV) to -.SV(Vp + .SV) to (Vp - 10V)±1.0mA300°C--------ELECTRICAL CHARACTERISTICS(-40°C ~ TA ~ +8S o C, Vp = SV ± 10%)PARAMETERFrequency Detect BandwidthAmplitude for DetectionTwist Tolerance60-Hz ToleranceDial Tone ToleranceCONDITIONSeach toneTwistHigh ToneLow Tone"precise" dial toneTalk Off MITEL tape #CM 7290Digital Outputs(except XOUT)Digital InputsPower Supply Noise"0" level, 400flA load"1" level, 200llA load"0" level"1" levelwide bandSupply Current TA = 25°CNoise Tolerance M ITEL tape #CM 7290Input ImpedanceVp~VIN~Vp-10* dB referenced to lowest amplitude toneMIN TYP MAX UNITS±(1.S+2Hz) ±2.3 ±3.S %offo-32 -2 dBm ref.to 600n-10 +10 dB_... _----0.8 VrmsOdBdB*------- - --2_____ 0 _____._--r----hits0 0.5 VVP-O.S VP V0 0.3Vp V--0.7Vp VP V--------10 mV p-p._-10 16 mA100kQI11SpF-12 dB*-----------1-------------I5-13

SSI 75T202/2035V Low-PowerDTMF ReceiverSSI 75T202/203 TIMINGPARAMETERCONDITIONSMINNOM MAX UNITStONTone Timefor detection 40- - msfor rejection -- 20 ms-- ------tOFFPause Timefor detection 40- ms- -for rejection -20 mstoDetect Time25- 46 mstRRelease Time35- 50 mstsuData Setup Time7- - IlstHData Hold Time4.2- 5.0 msc-------tClDV Clear Time-160 250 nstpwCLRDV Pulse Width200------- - nstEDED Detect Time7- 22 msf--tERED Release Time2- 18 msOutput Enable TimeC L = 50pF, RL = 1kQ -- 200 nsOutput Disable TimeC L = 35pF, RL = 500n -- 200 nsOutput Rise TimeC L = 50pF ----- 200 nsOutput Fall TimeC L = 50pF -160 200 ns5-14

SSI 75T202/2035V Low-PowerDTMF ReceiverSSI 75T202/203 TIMING (Continued)AnalogInputI--ton -I- tott---lPauseD1, D2,D4,D8DV~~CLRDVIEDtED~ liERFIGURE 4: Timing Diagram5-15

SSI 75T202/2035V Low-PowerDTMF ReceiverPACKAGE PIN DESIGNATIONS(TOP VIEW)01020102HEX/82804HEX/B2804EN08EN08IN1633GlRDVIN1633GlRDVVpOVVpOVN/GN/GATBXINEDN/G6ATBXINXEN 11XOUTXENXOUTANALOG INGNOANALOG INGNO18· Pin DIPSSI75T20218· Pin DIPSSI75T203CAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONSSI75T20218-pin Plastic DIPSSI75T20318-pin Plastic DIPORDER NO.75T202-IP75T203-IPPKG.MARK75T202-IP75T203-IPNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69141091 - rev.5-16©1989 Silicon Systems, Inc.

5517512045V Low-PowerSubscriberDTMF ReceiverDESCRIPTIONFEATURESOctober 1991The SSI 75T204 is a complete Dual-Tone Multifrequency(DTMF) receiver that detects 16 standarddigits. No front-end pre-filtering is needed. The onlyexternal components required are an inexpensive3.58-MHz television "colorburst" crystal for frequencyreference and a bias resistor. An Alternate Time Base(ATB) is provided to permit operation of up to 10 SSI75T204's from a single crystal. The SSI 75T204employs state-of-the-art "switched-capacitor" filtertechnology, resulting in approximately 40 poles offiltering, and digital circuitry on the same CMOS chip.The analog input signal is pre-processed by 60-Hzreject and band split filters and then zero-cross detectedto provide AGC. Eight bandpass filters detectthe individual tones. Digital processing is used to(Continued)• Intended for applications with less requirementsthan the SSI 75T202• 14-pin plastic DIP or 16-pin SO package for highsystem density• NO front-end band-splitting filters required• Single low-tolerance 5-volt supply• Detects all 16 standard DTMF digits.• Uses an inexpensive 3.579545-MHz crystal• Excellent speech immunity• Output in 4-bit hexadecimal code• Three-state outputs for microprocessor interfaceBLOCK DIAGRAMITIMINGCIRCUITRYL---------------DovDATA STROBE1Mz01020408ENvpGNO1091 rev.5-17CAUTION: Use handling procedures necessarylor a static sensitive component.

--~-551 75T2045V Low-PowerSubscriber DTMF ReceiverDESCRIPTION (Continued)measure the tone and pause durations and to provideoutput timing and decoding. The outputs interfacedirectly to standard CMOS circuitry and are three-stateenabled to facilitate bus-oriented architectures.ANALOG INThis pin accepts the analog input. It is internally biasedso that the input signal may be AC coupled. The inputmay be DC coupled as long as it does not exceed thepositive supply. Proper input coupling is illustrated inFigure 1.The SSI 75T204 is designed to accept sinusoidal inputwave forms but will operate satisfactorily with any inputthat has the correct fundamental frequency with harmonicsless then -20 dB below the fundamental.CRYSTAL OSCILLATORThe SSI 75T204 contains an onboard inverter withsufficient gain to provide oscill~tion when connected toa low-cost television "colorburst" crystal. The crystaloscillator is enabled by tying XEN high. The crystal isconnected between XIN and XOUT. A 1 Mz 10%resistor is also connected between these pins. In thismode, ATB is a clock frequency output. Other SSI75T204's (or 75T202's) may use the same frequencyreference by tying their A TB pins to the A TB of a crystalconnected device. XIN and XEN of the auxiliarydevices must then be tied high and low respectively.Ten devices may run off a single crystal-connected SSI75T204 (or 75T202) as shown in Figure 2.OUTPUTS 01, 02, 04, 08 and ENOutputs D1, D2, D4, D8 are CMOS push-pull whenenabled (EN high) and open circuited (high impedance)when disabled by pulling EN low. These digitaloutputs provide the hexadecimal code correspondingto the detected digit. The digital outputs become validafter a tone pair has been detected (DV is high) andthey are then cleared when a valid pause is timed. Thehexadecimal codes are described in Table 1.DVDV signals a detection by going high after a valid tonepair is sensed and decoded at the output pins D1, D2,D4, and D8: DV remains high until a valid pauseoccurs.N/C PINSThese pins have no internal connection and may be leftfloating.Output CodeDigit 08 04 02 011 0 0 0 12 0 0 1 03 0 0 1 1--4 0 1 0 0-----5 0 1 0 1---6 a 1 1 a7 a 1 1 18 1 a a a9 1 a a 10 1 0 1 a* 1 0 1 1# 1 1 a aA 1 1 a 1B 1 1 1 aC 1 1 1 1D a a a aTABLE 1: Output Codes5-18

SSI75T2045V Low-PowerSubscriber DTMF ReceiverVpVpVIN < VPVIN> VPa::>--%BAnalog In I Q.I~0.01 ~F 0..>1 t----

551 75T2045V Low-PowerSubscriber DTMF ReceiverDTMF DIALING MATRIXSee Figure 3. Please note that column 3 is for special applications and is not normally used in telephone dialing.ColO Col 1 Col 2 Col 3Row 0~ 0 0 0Row 1G 0 G 0Row 20 G 0 ~Row 3 [] G 0 0FIGURE 3: DTMF Dialing MatrixAnalogInputr---ton . I- toff~Pause01,02,04,08OVtotsdrtHtRr-FIGURE 4: Timing Diagram5-20

-~SSI75T2045V Low-PowerSubscriber DTMF ReceiverDETECTION FREQUENCYLow Group foRow 0 = 697 HzRow 1 = 770 HzRow 2 = 852 HzRow 3 = 941 HzHigh Group foColumn 0 = 1209 HzColumn 1 = 1336 HzColumn 2 = 1477 HzColumn 3 = 1633 Hz--SSI 75T204 TIMING (Refer to Figure 4.)PARAMETERCONDITIONSMIN NOM MAX UNITStONtOFFTone TimePause Timefor detectionfor rejectionfor detection40 - - ms--- - 20 ms- - --- ---------~-40 - - ms--"---~-------Ifor rejection- - 20 mstDDetect Time25 - 46 mstRRelease Time35 - 50 mstsutHData Setup TimeData Hold TimeOutput Enable TimeOutput Disable TimeOutput Rise TimeOutput Fall Time7 ~s- ----4.2 - 5.0 msC L = 50pF, RL = 1kQ - 200 nsC L = 35pF, RL = 500n - - 200 nsC L = 50pF - - 200 ns----~----------------C L = 50pF - - 200 ns5-21

551 75T2045V Low-PowerSubscriber DTMF ReceiverAPPLICATION INFORMATIONThe SSI 75T204 will tolerate total input RMS noise upto 12dB below the lowest amplitude tone. For mosttelephone applications, the combination of the highfrequency attenuation of the telephone line and internalband-limiting make special circuitry at the input tothe SSI 75T204 unnecessary. However, noise nearthe 56kHz internal sampling frequency will be aliased(folded back) into the audio spectrum, so if excessivenoise is present above 28kHz, the simple RC filtershown in Figure 5 may be employed to band limit theincoming signal.Noise will also be reduced by placing a grounded tracearound the XIN and XOUT pins on the circuit boardlayout when using a crystal. It is important to note thatXOUT is not intended to drive an additional device. XI Nmay be driven externally; in this case leave XOUTfloating.2.4K = 5%NOISYSIGNALANALOG IN881 75T204.01mF=20%IFIGURE 5: RC Filter5-22

~----SSI75T2045V Low-PowerSubscriber DTMF ReceiverABSOLUTE MAXIMUM RATINGS(Operation above absolute maximum ratings may damage the device. All SSI 7ST204 unused inputs must beconnected to Vp or GND, as appropriate.)PARAMETERDC Supply Voltage - VPOperating TemperatureStorage TemperaturePower Dissipation (2S0C)Input Voltage (All inputs except ANALOG IN)ANALOG IN VoltageDC Current into any InputLead Temperature - Soldering, 10 sec.RATING+7V-40°C to +8SoC Ambient-6SoC to + 1 SO°C6SmW(Vp + O.SV) to -0.5V(Vp + .SV) to (Vp - 10V)±1.0mA300°CELECTRICAL CHARACTERISTICS(-40°C ~ TA ~ +8SoC, VP = SV ± 10%)PARAMETERFrequency Detect BandwidthAmplitude for DetectionTwist Tolerance60-Hz ToleranceDial Tone ToleranceCONDITIONSeach toneTwistHigh ToneLow Tone-"precise" dial toneTalk Off M ITEL tape #CM 7290Digital Outputs(except XOUT)Digital InputsPower Supply NoiseSupply Current"0" level, 4001JA load"1" level, 2001JA load"O"level"1" levelwide bandTA = 2SoCNoise Tolerance M ITEL tape #CM 7290Input Impedance Vp~VIN~Vp-1 0* dB referenced to lowest amplitude toneMIN TVP MAX UNITS±(1.S+2Hz) ±2.3 ±3.S %offo-32 -2 dBm ref.to 600n-10 +10 dB_.0.8 VrmsOdBdB*2 hits0 O.S VVP-O.S VP V_.-0 0.3Vp V0.7Vp VP V100Knll1SpF10 mV p-p10 16 mA---12 dB*I5-23

551 75T2045V Low-PowerSubscriber DTMF ReceiverPACKAGE PIN DESIGNATIONS(TOP VIEW)0201 2EN 3 12SSI75T204VP 4 11N/C 5XEN 6ANALOG IN 70408OVATBXINXOUTGNO04;)1 08ENOVVPN/CN/CATBN/CXINXENXOUTANALOG INGNO14· Pin DIP16· Lead SOLCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONSSI75T20414-pin POIPSSI75T20416-lead SOLORDER NO.75T204-IP75T204-ILPKG.MARK75T204-IP75T204-ILNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69141091 - rev. 5-24 ©1989 Silicon Systems, Inc.

551 75T2089/2090/2091DTMF TransceiversDESCRIPTIONSilicon Systems' SSI 75T2089/2090/2091 are completeDual-Tone Multifrequency (DTMF) Transceiversthat can both generate and detect all 16 DTMF tonepairs.These les integrate the performance-provenSSI 75T202 DTMF receiver with a DTMF generatorcircuit.The DTMF receiver electrical characteristics are identicalto the standard SSI 75T202 device characteristics.The DTMF generator provides performance similar tothe Mostek MK5380, but with an improved (tighter)output amplitude range specification and with the additionof independent latch and reset controls.An additional feature of the SSI 75T2090/2091 is "imprecise"call progress detector. The detector detectsthe presence of signals in the 305-640 Hz band.BLOCK DIAGRAMLIN D--4-----j(209()12091 only)(Continued)FEATURES November 1991•••••••••••DTMF Generator and Receiver on one-chipCall progress detection (2090/2091 only)Early detect output (2091 only)DTMF Receiver exhibits excellent speech immunityAnalog input range from -32 to -2 dBm (ref 600.0)Three-state outputs (4-bit hexadecimal) from DTMFReceiverAC coupled, internally biased analog inputLatched DTMF Generator inputsDTMF output typo -8 dBm (Low Band) and -5.5 dBm(High Band)Easy interface for microprocessor dialingUses inexpensive 3.579545 MHz crystal for reference• Low-power 5 volt CMOSf--------O DET(2090/2091 only)I070605RESET D--4----------lBANDPASSFILTERSonly)1191CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI· 75T2089/2090/2091DTMF TransceiversDESCRIPTION (Continued)The SSI 75T2091 also incorporates an early detectfunction which is useful in multi-channel radio scanningapplications. The only external components necessaryfor the S8175T2089/2090/2091 are a 3.58 MHz"colorburst" crystal with a parallel 1 MQ resistor. Thisprovides the time base for digital functions andswitched-capacitor filters in the device. No externalfiltering is required.CIRCUIT OPERATIONRECEIVERThe DTMF Receiver in the SSI 75T2089/2090/2091detects the presence of a valid tone pair (indicating asingle dialed digit) on a telephone line or other transmissionmedium. The analog input is pre-processed by60 Hz reject and band-splitting filters, then hard-limitedto provide Automatic Gain Control. Eight bandpassfilters detect the individual tones. The digital postprocessortimes the tone durations and provides thecorrectly coded digital outputs. The outputs will drivestandard CMOS circuitry, and are three-state enabledto facilitate bus-oriented architectures.DINThis pin accepts the analog input. It is internally biasedso that the input signal may be AC coupled. The inputmay be DC coupled as long as it does not exceed thepositive supply. Proper input coupling is illustrated inFigure 1.The IC is designed to accept sinusoidal input waveformsbut will operate satisfactorily with any input thathas the correct fundamental frequency with harmonicsgreater than -20 dB below the fundamental.CRYSTAL OSCILLATORThe IC contains an onboard inverter with sufficient gainto provide oscillation when connected to a low-costtelevision "color-burst" crystal. The crystal is placedbetween XIN and XOUT in parallel with a 1 Mz resistor,while XEN is tied high. Since the switched-capacitorfiltertime base is derived from the crystal oscillator, thefrequency accuracy of all portions of the IC depends onthe time base tolerance. The SSI DTMF Receiverfrequency response and timing is specified for a timebase accuracy of at least =0.005%. ATB is a clockoutput with the frequency of 1/8 of crystal. Otherdevices may use the same frequency reference bytying their ATB pin!? to the ATB of; a crystal connecteddevice. XIN and XEN of the auxiliary devices mustthenbe tied high and low respectively, XOUT is left floating.XOUT is designed to drive a resonant circuit only andis not intended to drive additional devices. Ten devicesmay run off a single crystal-connected transceiver asshown in Figure 2.vpIIIIVINVP IIIIO.01I1F IVpATBSSI75T20XXXIN Connected to VpATBSSI75T20XXXENGNDFIGURE 1: Input CouplingUp to 10 DevicesFIGURE 2: Crystal Connections5-26

SSI 75T2089/2090/2091DTMF TransceiversRECEIVER OUTPUTS AND THE DE PINOutputs ~O, 01, 02, 03 are CMOS push-pull whenenabled (DE low) and open-circuited (high impedance)when disabled (DE high). These digital outputs providethe hexadecimal code corresponding to the detecteddigit. Figure 3 shows that code.The digital outputs become valid and OV signals adetection after a valid tone pair has been sensed. Theoutputs and OV are cleared when a valid pause hasbeen timed.Hexadecimal CodeDigit In 07 06 05 04Out 03 02 01 DO1 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 1--6 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 10 1 0 1 0* 1 0 1 1# 1 1 0 0A 1 1 0 1B 1 1 1 0C 1 1 1 10 0 0 0 0FIGURE 3GENERATORThe OTMF generator responds to a hexadecimal codeinput with a valid tone pair. Pins 04-07 are the datainputs for the generator. A high to low transition onLATCH causes the hexadecimal code to be latchedinternally and generation of the appropriate OTM Ftonepairto begin. The OTM F output is disabled by a high onRESET and will not resume until new data is latched in.DIGITAL INPUTSThe 04, 05, 06, 07, LATCH, RESET inputs to theOTMF generator may be interfaced to open-collectorTTL with a pull-up resistor or standard CMOS. Theseinputs follow the same hexadecimal code format as theOTMF receiver output. Figure 4 shows the code foreach digit. The dialing matrix and detection frequencytable below list the frequencies of the digits.ColO Col 1 Col 2 Col 3Row 0 G ~ G 0Row1 G G G 0Row 2 D ~ G 0Row 3 D G G 0NOTE: Column 3 is for special applicationsand is not normally used in telephone dialing.FIGURE 4: DTMF Dialing MatrixDETECTION FREQUENCYIED OUTPUT (75T2091 only)The ED output goes high as soon as the SSI 75T2091begins to detect a OTMF tone pair and falls when theSSI75T2091 begins to detect a pause. The 01,02,04,and 08 outputs are guaranteed to be valid when OV ishigh, but are not necessarily valid when ED is high.Low Group foRow 0 = 697HzRow 1 = 770HzRow 2 = 852HzRow 3 = 941HzHigh Group foColumn 0 = 1209HzColumn 1 = 1336HzColumn 2 = 1477HzColumn 3 = 1633Hz5-27

551 75T2089/2090/2091DTMF TransceiversDTMF OUTThe output amplitude characteristics listed in thespecifications are given for a supply voltage of 5.0V.However, the output level is directly proportional to thesupply, so variations in it will affect the DTM F output. Arecommended line interface for this output is shown inFigure 5.CALL PROGRESS DETECTION (75T2090/2091)The 75T2090/2091 have a Call Progress Detector thatconsists of a bandpass filter and an energy detector forturning the on/off cadences into a microprocessorcompatible signal.DET OUTPUT (75T2090/2091)The output is TTL compatible and will be of a frequencycorresponding to the various candences of Call Progresssignals such as: on 0.5 sec/off 0.5 sec for a busytone, on 0.25 sec/off 0.25 sec for a reordertone and on0.8-1.2 sec/off 2.7-3.3 sec for an audible ring tone.LIN INPUT (75T2090/2091)This analog input accepts the call progress signal andshould be used in the same manner as the receiverinput DIN.~(f{ f--__ ---.,1 :1cTIP100nFIGURE 5: DTMF OutputRINGELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperating above absolute maximum ratings may damage the device.PARAM~TERDC Supply Voltage (Vp - Vn) +7VRATINGVoltage at any Pin (Vn = 0) -0.3 to Vp + 0.3VDIN VoltageCurrent through any Protection DeviceVp + 0.5 to Vp - 10V=20mAOperating Temperature Range -40 to + 85°CStorage Temperature -65 to 150°CRECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITSupply Voltage 4.5 5.5 VPower Supply Noise (wide band) 10 mVp-pAmbient Temperature -40 +85 °CCrystal Frequency -(}'01 +0.01 %(F Nominal = 3.579545MHz)Crystal Shunt Resistor 0.8 1.2 MQ-- -DTMF OUT Load Resistance 100 Q5-28

551 75T2089/2090/2091DTMF TransceiversDIGITAL AND DC REQUIREMENTSThe following electrical specifications apply to the digital input and output signals over the recommendedoperating range unless otherwise noted. The specifications do not apply to the following pins: LIN, DIN, XIN,XOUT, and DTMF OUT. Positive current is defined as entering the circuit. Vn = 0 unless otherwise stated.PARAMETER CONDITIONS MIN NOM MAX UNITSupply Current* 15 30 rnA~Power Dissipation 225 mWInput Voltage High 0.7Vp VInput Voltage Low 0.3Vp VInput Current High 10 IJAInput Current Low -10 IJAOutput Voltage High loh = -0.2mA Vp-0.5 V-~~----- ~Output Voltage Low 101 = +O.4mA Vn+0.5 V* with DTMF output disabledDTMF RECEIVER: Electrical CharacteristicsPARAMETER CONDITIONS MIN NOM MAX UNITFrequency Detect Bandwidth =(1.S+2Hz) =2.3 =3.5 %FoIAmplitude for Detection Each Tone -32 -2 dBm/toneTwist Tolerance -10 +10 dB----------60Hz Tolerance 0.8 Vrms--_..-Dial Tone Tolerance Precise Dial Tone 0 dB*-----Speech Immunity MITEL Tape #CM7290 2 hits- -~Noise Tolerance MITEL Tape #CM7290 -12 dB*I nput Impedance 100 kQ-- ~~~--~~- ~-~.~~--'-------~* Referenced to lowest amplitude toneDTMF RECEIVER: Timing CharacteristicsPARAMETER CONDITIONS MIN NOM MAX UNITTON Tone Time for Detect 40 ms---------------TON Tone Time for No Detect 20 ms----- ----TOFF Pause Time for Redetection 40 msTOFF Pause Time for Bridging 20 ms------ ---------_...TD1 Detect Time 25 46 ms.- ----TR1 Release Time 35 50 ms5-29

SSI 75T2089/2090/2091DTMF TransceiversDTMF RECEIVER: Timing Characteristics (Continued)PARAMETERCONDITIONSMINNOMMAXUNITTSU1 Data Set Up TimeTHD1 Data Hold TimeTED ED Detect Time 75T2091 onlyBER ED Release Time 75T2091 onlyOutput Enable TimeOutput Disable TimeDTMF GENERATOR: Electrical CharacteristicsFrequency AccuracyOutput Amplitude R1 = 1 Don to Vn, Vp - Vn = 5.0VLow BandHigh BandOutput DistortionDC to 50 kHz74.272-1.0-9.2-6.6--_.-_ ..--.j.Js5.0 ms22 ms18 ms200 ns200 ns+1.0 %Fo-7.2 dBm-4.6---- --_.-dBm-20 dBDTMF GENERATOR: Timing CharacteristicsTSTART Start-Up TimeTSU2 Data Set-Up TimeTHD2 Data Hold TimeTRP RESET Pulse Width100501002.5 !-ISnsnsnsTPWLATCH Pulse Width100nsCALL PROGRESS DETECTOR: Electrical Characteristics (75T2090/2091 only)Amplitude for Detection 305 Hz-640 Hz -40Amplitude for No Detection 305 Hz-640 Hz1>2200 Hz,

_--'L_----'L551 75T2089/2090/2091DTMF TransceiversCALL PROGRESS DETECTOR: Electrical Characteristics (Continued)PARAMETER CONDITIONS MIN NOM MAX UNITTON Signal Time for Detect 40-- _._--msTON Signal Time for No Detect--_...__.- ---10 msTOFF Interval Time for Detect 40 ms.._- ----- ---~--c-------TOFF Interval Time for No Detect 20 ms--- -- --------'-----TD2 Detect Time 40 msTR2 Release Time 40 msDINOVTONI TOFF I~~:::'::::::'I mM''- ___~I 1-1.... ==-------'i!!! ......,toneburst2 t!!'-__ _DINI~:: :l tonebursl1IITOFFlonebursl2!:::100,01,0203~I-ED * ~ 1....-1~I-DV00.01,02,03I* 75T2091 onlyFIGURE 6: DTMF DecoderFIGURE 7: Call Progress Detector(75T2090/2091 only)04, 05, 06, 07TH02 j/TSU2-.----------L-l-----iL-----TP-----,W~'-r-I --­TPWI-------r~--- (SEE NOTE) -------IRESETOTMFOUTI TSTARTII TRP~ 1-----1------------~~-----------------NOTE: THE INDICATED TIME MAY BE AS SMALL AS 0 SEC., MEANING THAT THE LATCH AND RESET LINES MAY BE TIED TOGETHER.FIGURE 8: DTMF Generator5-31

551·75T2089/2090/2091DTMF TransceiversPACKAGE PIN DESIGNATIONS(Top View)03 OV02 0701 0600 05OE 04VPXENOINXOUTXINATB- 75T2090 onlyLATCHRSTOET-LIN-DTMFOUTVN02 0301 OV00 07N/C 06OE 05VP 04EDXENN/CN/CDINXOUTXINATBLATCHRSTNlCN/CDETLINDTMFOUTVNOE0C\I M0> r-... toa a a a a a4 3 2 28 27 2625VP 24EO 23N/C 22N/C 21XEN 20N/C 19012 13 14 15 16 17 18Z r- z co z r- z0 ::> X r- :; ::>

SSI75T980Call ProgressTone DetectorDESCRIPTIONThe 551 75T980 Call Progress Tone Detector circuitallows automatic equipment to monitor tones in dialtelephone systems that relate to the routing of calls.5uch tones commonly include dial tones, circuits-busytones, station-busy tones, audible ringing tones andothers. By sensing signals in the range of 315 to640 Hz, the SSI 75T980 does not require the use ofprecision tones to function. This means that toneswhich vary with location or call destination can bedetected regardless of their exact frequency.The low powerCM05 switched capacitorfilters used inthe 5S1 75T980 derive their accuracy from a 3.58 MHzclock, which in turn may be derived from other devicesin the system being designed. The S51 75T980 isavailable in a plastic 8-pin DIP and 16-pin 50packages.FEATURESJune 1994Detects tones throughout the telephone progresssupervision band (315 to 640 Hz)Sensitivity to -38 dBmDynamic range over 36 dB40 ms minimum detect (50 ms to output)Single supply CMOS (lOW power)Supply range 4.5 to 5.5 VDCUses 3.58 MHz crystal or external clock8-pin DIP and 16-pin SO packagesSecond source of Teltone M-980------1BLOCK DIAGRAMPIN DIAGRAMXIN8VDDXOUT27VREFENABLE36VSSDETECT45SIGIN8-Pin DIPXIN XOUT ENABLECAUTION: Use handling procedures necessaryfor a static sensitive component.0694 - rev. 5-33

551 75T980Call ProgressTone DetectorPIN DESCRIPTIONNAMESIGINTYPEDETECT 0ENABLEVREF 0XIN, XOUTVoo -Vss -IIIDESCRIPTIONAccepts analog input signal. See "Electrical Characteristics" for voltage levels,and "Timing Characteristics" for timing.Call progress detect output. Goes to logic "1" when signal in 315-640 Hz bandis sensed. See "Timing Characteristics."Application of logic "1" on this pin enables the output; logic "0" disables output.Supplies voltage at half Voo for voltage reference of on-chip op amps.Crystal connections to on-chip oscillator circuit.Positive power supply connectionNegative power supply connectionOdBm-+==SIGNALLEVELMUST DETECTREGION-38dBm-50dBmNOTDETECTREGION190Hz 315Hz 640Hz 1025HzFREQUENCYFIGURE 1: Detect and Reject Regions5-34

SSI75T980Call ProgressTone DetectorELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGS(Operation above absolute maximum ratings may permanently damage the device.)PARAMETERDC Supply Voltage VOD-VSS 16VRATINGInput Voltage All inputs except SIGNAL IN (Voo + 0.5V) to (Vss - 0.5V)SIGNAL IN Voltage (Voo + 0.5V) to (Vss - 22V)--Storage Temperature-65°C to 1S0°COperating Temperature -30°C to 70°CLead Temperature Soldering, 5 sec. 260°CELECTRICAL CHARACTERISTICS(TA = 2SoC, Voo - Vss = 4.5V to S.SV, dBm is referenced to 6000.)PARAMETER CONDITIONS MIN NOM MAX UNITSSupply Current Voo- Vss = 5V - 4 10 mASignal level for detection 31S-640 Hz -38 0 dBmSignal level for rejection 315-640 Hz - -SO dBmf >1025 Hz, f

SS175T980Call ProgressTone DetectorELECTRICAL SPECIFICATIONS (continued)TIMING CHARACTERISTICS(TA = 25°C, VDD - Vss = 4.SV TO S.SV)PARAMETERCONDITIONStMD Signal duration for detection 315-640 HztsInterval duration for detectionTone dropout bridgingSignal dropping from-38 dBm to -50 dBm (t 2)Signal dropping fromo dBm to -50 dBm (t 1)MIN NOM MAX40 -- 40--------- 90- 20UNITSmsf---------msmsmsIf-IMD -tjf-----------il L..----.....JI----D-D~~ IS If-SIGIN ------ll-----------LCtF-------..... :~~::~:FIGURE 2: Basic Timing5-36

551 75T980Call ProgressTone DetectorSIGIN-q~DETECT IL ut1 --tl--. t2I*-~FIGURE 3: Effect of Amplitude on TimingIPHONE ,----'--....,LINEDAA....----_.1 SIGIN881 75T9803.58 MHzDXINDIALER ICDETECTPHONE LINEAUDIOSIGIN881 75T9803.58 MHzDXINDETECT551 75T202/3/4DVANALOG STROBEINDATA t---..DIALERDTMF RECEIVERFIGURE 4: Applications Circuits5-37

SSI·75T980Call ProgressTone DetectorPACKAGE PIN DESIGNATIONS(Top View)XIN 8XOUT 2 7ENABLE 3 6DETECT 4 58-Pin DIPVDDVREFVSSSIGINN/C 16 N/CXIN 2 15 VDDN/C 3 14 VREFXOUT 4 13 N/CEN 5 12 VSSN/C 6 11 N/CDET 7 10 SIGINN/C 8 9 N/C16-Lead SOCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONSSI75T980 8-pin Plastic DIPSSI 75T980 16-pin SO PackageORDER NO.75T980-CP75T980-CLPKG.MARK75T980-CP75T980CNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheetis current before placing ordersSilicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914©1989 Silicon Systems, Inc. 5-38 0694 - rev.

551 78A207MFR1 ReceiverJuly 1990DESCRIPTIONThe SSI78A207 is a single-chip, Multi-Frequency (M F)receiver that can detect all 15 tone-pairs, including STand KP framing tones. This receiver is intended for usein equal access applications and thus meets both Belland CCITT R1 central office register signalling specifications.The SSI 78A207 employs state-of-the-art switchedcapacitor filters in CMOS technology. The receiverconsists of a bank of channel-separation bandpassfilters followed by zero-crossing detectors and frequency-measurementbandpass filters, an amplitudecheck circuit, a timer and decoder circuit, and a clockgenerator. The device does not attempt to identifystrings of digits by the KP (key pulse) and ST (stop)tone pairs.No anti-alias filtering is needed if the input signal isband-limited to 26 KHz. The only external componentrequired is an inexpensive television "color burst" 3.58MHz crystal.The outputs interface directly with standard CMOS orTTL circuitry and are three-state enabled to facilitatebus-oriented architecture.FEATURES• Meets Bell and CCITT R1 specifications• 20-pin plastic DIP• Single low-tolerance 5V supplyDetects all 15 tone-pairs including ST and KP• Long KP capability• Built-in amplitude discrimination• Excellent noise tolerance• Outputs in either "n of 6" or hexadecimal code• Three-state outputs, CMOS-compatibleand TTL-compatibleIBLOCK DIAGRAMVDD AGN DGND 5-390790 - rev.

SSI78A207MFR1 ReceiverFUNCTIONAL DESCRIPTIONVINThis pin accepts the analog input. It is internally biasedto half the supply and is capacitively coupled to thechannel separation filters. The input may be DCcoupled as long as it does not exceed VOO or dropbelow GND. Equivalent input circuit is shown below inFigure 1.CRYSTAL OSCILLATORThe SSI 78A207 contains an on-board inverter withsufficient gain to provide oscillation when connected toa low cost television "color-burst" crystal. The on-chipclock signals are generated from the oscillator. Thecrystal is connected between X1 and X2.XOUT is a 3.58 MHz square wave capable of drivingother circuits as long as the capacitive load does notexceed 50 pF. Other devices driven by XOUT shoulduse X1 as the input pin, while X2 should be left floating.LKPThe KP timer control: When high, the KP detect timeis increased. When low, the KPdetecttime is the sameas for other tones.QUALEnables tone pair qualification. When low, the thresholddetector outputs are passed to the data outputs(00-05) without validation in the format selected by theHEX pin. These outputs, plus strobes OV and DE, areupdated once per 2.3 ms frame. Note that the strobeswill cycle once per frame (even when the inputs arestable.) As always, data changes only when bothstrobes are low.CSTRThis input clears both the OV and DE strobes, and isactive low. After CSTR is released, the strobes willremain low until a new detect (or error) occurs. Theoutput data is latched by CSTR and will not changewhile CSTR is low, even in the event that a new detectis qualified internally. (Note that improper use of CSTRmay result in missed detects.)ENThe three-state enable control: When low, the 00-05outputs are in the low impedance state. In an interruptoriented microprocessor interface, EN and CSTR willoften be tied together to provide automatic reset of thestrobes when the output data is enabled.STROBE PINS· DV AND DEValid data is indicated on the OV strobe pin, and dataerrors are indicated on the DE strobe pin. Whenever avalid 2 of 6 code has been detected, the OV stroberises. It remains high until the code goes away, or theCSTR line is activated. When an invalid code isdetected, e.g., 1 of 6,3 of 6, etc., the DE strobe remainshigh until all errors stop, a valid tone pair is detected, orthe CSTR line is activated. Once cleared by CSTR, DEwill not reactivate until a new invalid condition is detected.The DE and OV strobes will never be highsimultaneously.DATA OUTPUT MODESThe digital output format may be either "n of 6" or 4-bithexadecimal.For"hex" mode, the HEX pin is pulled high. Outputs 00to 03 provide a 4-bit code identifying one of the 15 validtone combinations according to Table1.The outputs will be cleared to zero when no valid tonepair is present.For the "n of 6" mode, the HEX pin is pulled low, andeach output represents one of the six frequencies asshown below:FREQUENCY7009001100130015001700OUTPUT PIN000102030405The outputs will be cleared to zero when no valid toneis present.5-40

--~---SSI78A207MFR1 ReceiverTABLE 1:Channels Tone Pair Freq. Name 030-1 700, 900 1 00-2 700,1100 2 01-2 900,1100 3 00-3 700, 1300 4 a1-3 900, 1300 5 02-3 1100,1300 6 00-4 700, 1500 7 a1-4 900, 1500 8 12-4 1100,1500 9 13-4 1300, 1500 0 12-5 1100,1700 KP 14-5 1500,1700 ST 11-5 900, 1700 5T1 13-5 1300, 1700 5T2 10-5 700,1700 5T3 1any other signalaNOTE: In the hex mode, 04 = DE and 05 = OV.02 01 000 0 1------ -- ----.--.~- ----.... ~-a 1 a-~~-~----.-a 1 1--.1 a 0----- -- --_.--~1 a 1---1 1 a1-_.-._--1f--1a a 0-------~a 0 1a 1 0--"------f------a 1 1-~1 a 0--f----------.- -------r-------1--._-0 1---_._-------1 1 0-----~-~-~-.---1 1 1-------- - -0 a a---- - --.~.-.--~~.---IVDDVINFIGURE 1: VIN Equivalent Input Circuit5-41

-~---SSI78A207MFR1 ReceiverTIMING SPECIFICATIONSPARAMETERCONDITIONSMINNOM MAX UNITTonTonTonTone Time, KP(LKP = VDD)Tone Time, KP(LKP = DGND)TonTon Tone Time, All OthersTonTpse Pause TimeTbrTsu Data Setup TimeTh Data Hold TimeTskew Tone Skew ToleranceTstr Minimum Strobe Pulse WidthQUAL HighQUAL LowTsep Minimum Strobe SeparationQUAL HighQUAL LowTr Rise Time DV, DE, DO-OS10-90%Tf Fall Time DV, DE, DO-OS10-90%Tw CSTR WidthTen Data Enable TimeTdis Data Disable TimeTrst Strobe Reset Timedetect 55rejectdetect 30rejectdetect 30reject--detect 20reject67CL = 20 pFCL = 20 pFCL = 20 pFCL = 20 pF20220250- .. _---------- ---_._---- ----~- ---~----ms30 msms10 msms10 ms1------ms10 ms__ I-l_S __--------I-lS4 ms-.---~------.. - -_ ...--.--------.-----msms----- -------------ms----------~.-~ -~---ms----".100 ns---- ----- -100 ns- --~-.-."._-ns100 ns----~-~-100 ns100 ns5-42

SSI78A207MFR1 Receiver114 ...------ Tpse ----~TONE'TONE 2i-T ,-s_kew_______---,DO-D5DV (QUAL -') --------'TSU~ == Tstr--~~ ~ Th,----------,DV (QUAL - 0) -----'Tstr-----1~ -.j ~TsepDE (QUAL-O)------------------------+-JIFIGURE 2: SSI 78A207 Timing DiagramELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGS(Operating above absolute maximum ratings may damage the device.)PARAMETERRATINGDC Supply Voltage V DD+ 7VOperating Temperatureo to 70 (AmbienWCStorage Temperature 65 to 150°CPower Dissipation (25°C)650mW(Derate above TA=25°C @ 6.25 mW/°C)Input Voltage(VDD + 0.3V) to-9.3VDC Current into any input±10mALead Temperature (Soldering, 10 sec.) 300°C5-43

SSI·78A207MFR1 ReceiverDC ELECTRICAL CHARACTERISTICS (O°C $ TA ~ 70°C, VDD = 5V ± 10%)PARAMETER CONDITIONS MINIddSupply CurrentVol Output Logic 0101 = 8 rnA101 = 1 rnAVoh Output Logic 1loh = -4 rnAloh=-1 rnAVDD-1.0VDD-O.5Vih Input Logic 1 2.0Voh Input logic 0Zin Analog Input Impedance 100K(Input between VDD and AGND)30pFlin Digital Input Current -50(Input between VDD and DGND)NOM MAX UNIT~ ..-20 rnA.--0.5 V- -.~---0.4 V-_._--- f--------..- - .•_...• -.----•.. --.~-1---------- --- ~--.-... ---VV --V.--e---.. --0.8 V._--_..._- 1-------Q50 ~AC CHARACTERISTICS (O°C ~ TA ~ 70°, VDD = 5V ± 10%)PARAMETER CONDITIONS MINF Frequency for Detect ±(0.015Tolerance xFo + 5)A Amplitude for Detect each tone -25ANAmplitude for no Detect0.123TW Twist Tolerance TW= high tone -6low toneNOM MAX UNITHz0 dBm2.191 Vpp---_ ...-35 dB0.039 Vpp+6 dBT3 Third MF Tone Reject Amp relative to highest -15amplitude toneN60 60 HZ Tolerance not more than one error 81in 2500 1 a-digit calls 0.777N180 180 HZ Tolerance same as above 68Nn Noise Tolerance 1 same as aboveNI Impulse Noise Tolerance 2 same as aboveNOTES: 1. C-message weighted. Measured with respect to highest amplitude tone.2. With noise tape 201 per PUB 56201. Measured with respect to highest amplitude tone.5-440.174~-1----..dBdBrnVppdBrnVpp-20 dB+12 dB

SSI78A207MFR1 ReceiverICAUTION: Use handling procedures necessary______________________________________________________________ ~~~~~fo~ra~s~ta~ti~c~se~n~si~tiv~e~co~m~p~on~e~nt~.~~PART DESCRIPTION ORDER NO. PKG.MARKSSI 78A207 20-Pin Plastic DIP 78A207-CP 78A207-CPNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914©1989 Silicon Systems, Inc. 5-45 0890 - rev.

Notes:5-46

Section 6PCM PRODUCTSI6

6-0

SSI78P300T1/E1 Integrated Short Haul Transceiverwith Receive Jitter AttenuationDESCRIPTIONThe SSI78P300 is a fully integrated transceiver for bothNorth American 1.544 MHz (T1), and European 2.048MHz (E1/CEPT) applications. Transmit pulse shapes(DSX-1 or E1/CEPT) are selectable for various linelengths and cable types.The SSI 78P300 provides receive jitter attenuationstarting at 3 Hz, and is microprocessor controllablethrough a serial interface.The SSI 78P300 offers a variety of diagnostic featuresincluding transmit and receive monitoring. Clock inputsmay be derived from an on-chip crystal oscillator ordigttal inputs. The SSI 78P300 uses an advanceddouble-poly, double-metal CMOS process and requiresonly a single 5-volt power supply.December 1993FEATURES• Compatible with most popular PCM framersincluding the 2180A and 2181• Line driver, data recovery and clock recoveryfunctions• Pin and functionally compatible with CrystalCS61574• Minimum receive signal of 500 mV• Selectable slicer levels (CEPT/DSX-1) ImproveSNR• Programmable transmit equalizer shapespulses to meet DSX-1 pulse template from 0 to655 ft• Local and remote loopback functions• Transmit Driver Performance Monitor (DPM)output• Receive monitor with Loss of Signal (LOS) output• Receiver jitter tolerance 0.4 UI from 40 kHz to100 kHz• Microprocessor controllable• Receive jitter attenuation starting at 6 Hz• Available in 28 pin DIP or PLCCBLOCK DIAGRAMMODE-----------r--~~HOST R7WINT EC1SOi EC2SDo EC3a RLOOPSCLK LLOOPCLKE TAOSTPOS --+---~TNEG __ +-__ ~TCLK --+---~CONTROLEQUALIZERSYNCHRONIZER'r-______ +- TTIPTRINGMCLK--+--~XTALlN--L-...... r==:Jc=lXTALOUT--t-----iRCLK __ I----L_r--~t4-..-~RTIPj41-

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationFUNCTIONAL DESCRIPTIONThe SSI 78P300 is a fully integrated PCM transceiverfor both 1.544 MHz (DSX-1) and 2.048 MHz (CEPT)applications. This transceiver allows transmission ofdigital data over existing twisted-pair installations.The SSI78P300 transceiver interfaces with two twistedpairlines (one twisted-pair for transmit, one twistedpairfor receive) through standard pulse transformersand appropriate resistors.TRANSMITTERData received for transmission onto the line is clockedserially into the device at TPOS and TNEG. Inputsynchronization is supplied by the transmit clock (TCLK).The transmitted pulse shape is determined by EqualizerControl signals EC 1 through EC3 as shown inTable 1. Refer toTable 2 and Figure 1 for master andtransmit clock timing characteristics. Shaped pulsesare applied to the AM I line driver for transmission ontothe line at TTIP and TRING. Equalizer Control signalsmay be hardwired in the Hardware mode, or input aspart of the serial data stream (SDI) in the Host mode.Pulses can be shaped for either 1.544 or 2.048 MHzapplications. 1.544 MHz pulses for DSX-1 applicationscan be programmed to match line lengths from 0 to 655feet of ABAM cable. The SSI 78P300 also matchesFCC and ECSA specifications for CSU applications.2.048 MHz pulses can drive coaxial or shielded twistedpairlines using appropriate resistors in line with theoutput transformer.DRIVER PERFORMANCE MONITORThe transceiver incorporates a Driver PerformanceMonitor (DPM) in parallel with the TTIP and TRING atthe output transformer. The DPM output level goeshigh upon detection of 63 consecutive zeros. It is resetwhen a one is detected on the transmit line, orwhen areset command is received.LINE CODEThe SSI78P300 transmits data as a 50% AM I line codeas shown in Figure 2. Power consumption is reducedby activating the AM I line driver only to transmit a mark.The output driver is disabled during transmission of aspace.RECEIVERThe SSI78P300 receives AM I signals from one twistedpairline on each side of a center-grounded transformer.Positive pulses are received at RTIP andnegative pulses are received at RRING. Recovereddata is output at RPOS and RNEG, and the recoveredclock is output at RCLK. Refer to Table 3 and Figure 3for SSI 78P300 receiver timing.The signal received at RPOS and RNEG is processedthrough the peak detector and data slicers. The peakdetector samples the inputs and determines the maximumvalue of the received signal. A percentage of thepeak value is provided to the data slicers as a thresholdlevel to ensure optimum signal-to-noise ratio.For DSX-1 applications (determined by Equalizer Controlinputs EC 1 - EC3 :;:. 000) the threshold is set to 70%of the peak value. This threshold is maintained above65% for up to 15 successive zeros over the range ofspecified operating conditions. For CEPT applications(EC inputs = 000) the threshold is set to 50 %.The receiver is capable of accurately recovering signalswith up to -13.6 dB of cable attenuation (from 2.4V), corresponding to a received signal level of approximately500 mV (1500 feet of ABAM cable.) Regardlessof received signal level, the peak detectors are heldabove aminimum level of .3 Vto provide immunityfromimpulsive noise;After processing through the data slicers, the receivedsignal is routed to the data and clock recovery sections,and to the receive monitor. The receive monitor generatesa Loss of Signal (LOS) output upon receipt of 175consecutive zeros (spaces). The receiver monitor loadsa digital counter at the RCLK frequency. The count isincremented each time a zero is received, and reset tozero each time a one (mark) is received. Upon receiptof 175 consecutive zeros the LOS pin goes high, andthe RCLK output is replaced with the MCLK. If MCLKis not supplied the RCLK output will be replaced withthe centered crystal clock.The LOS pin will reset as soon as a one (mark) isdetected.Recovered clock Signals are supplied to thejitter attenuator and the data latch. The recovered datais passed to the elastic store where it is buffered andsynchronized with the dejittered recovered clock(RCLK).6-2

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationJITTER ATTENUATIONJitter attenuation of the SSI 78P300 clock and dataoutputs is provided by a Jitter Attenuation Loop (JAL)and an Elastic Store (ES). An external crystal oscillatingat 4 times the bit rate provides clock stabilization.Refer to Table 4 for crystal specifications. The ES is a32 x 2-bit register. Recovered data is clocked into theES with the recovered clock signal, and clocked out ofthe ES with the dejittered clock from the JAL. When thebit count in the ES is within two bits of overflowing orunderflowing, the ES adjusts the output clock by 1/8 ofa bit period. The ES produces an average delay of 16bits in the receive path.OPERATING MODESThe SSI78P300 transceiver can be controlled throughhard-wired pins (Hardware mode). This transceivercan also be commanded to operate in one of severaldiagnostic modes.The SSI 78P300 can be controlled by a microprocessorthrougha serial interface (Host mode). The modeof operation is set by the MODE pin logic level.HOST MODE OPERATIONTo allow a host microprocessor to access and controlthe SSI 78P300 through the serial interface, MODE isset to 1. The serial interface (SDI/SDO) uses a 16-bitword consisting of an 8-bit Command/Address byteand an 8-bit Data byte. Figure 4 shows the serialinterface data structure and timing.The Host mode provides a latched Interrupt output(INT) which is triggered by a change in the Loss ofSignal (LOS) and/or Driver Performance Monitor (DPM)bits. The Interrupt is cleared when the interrupt conditionno longer exists, and the host processor enablesthe respective bit in the serial input data byte. Hostmode also allows control of the serial data and receivedata output timing. The Clock Edge (CLKE) signaldetermines when these outputs are valid, relative tothe Serial Clock (SCLK) or RCLK as follows:CLKE OUTPUT CLOCK VALID EDGERPOS RCLK RISINGLOW RNEG RCLK RISINGSDO SCLK FALLINGRPOS RCLK FALLINGHIGH RNEG RCLK FALLINGSDO SCLK RISINGThe SSI78P300 serial port is addressed by setting bitA4 in the Address/Command byte, corresponding toaddress 16. The SSI 78P300 contains only a singleoutput data register so no complex chip addressingscheme is required. The register is accessed by causingthe Chip Select (CS) input to make a transition fromhigh to low. Bit 1 of the serial Address/Command byteprovides Read/Write control when the chip is accessed.A logic 1 indicates a read operation, and a logic 0indicates a write operation. Table 5 lists serial dataoutput bit combinations for each status. Serial data I/Otiming characteristics are shown in Table 6, and Figures5 and 6.HARDWARE MODE OPERATIONIn Hardware mode the transceiver is accessed andcontrolled through individual pins. With the exceptionof the INT and CLKE functions, Hardware mode providesall the functions provided in the Host mode. In theHardware mode RPOS and RNEG outputs are valid onthe rising edge of RCLK. To operate in Hardwaremode, MODE must be set to O. Equalizer Controlsignals (EC1 through EC3) are input on the Interrupt,Serial Data In and Serial Data Out pins. Diagnosticcontrol for Remote Loopback (RLOOP), Local Loopback(LLOOP), and Transmit All Ones (TAOS) modes isprovided through the individual pins used to controlserial interface timing in the Host mode.RESET OPERATIONUpon power up, the transceiver is held static until thepower supply reaches approximately 3V. Upon crossingthis threshold, the device begins a 32 ms reset cycleto calibrate the transmit and receive delay lines andlock the Phase Lock Loop to the receive line. A referenceclock is required to calibrate the delay lines. Thetransmitter reference is provided by TCLK. The crystaloscillator provides the receiver reference in the SSI78P300.lfthe SSI78P300 crystal oscillator is grounded,MCLK is used as the receiver reference clock.The transceiver can also be reset from the Host orHardware mode. In Host mode, reset is commanded bysimultaneously writing RLOOP and LLOOP to theregister. In Hardware mode, reset is commanded byholding RLOOP and LLOOP high simultaneously for200 ns. Reset is initiated 0 n the falling edge of the resetrequest. In either mode, reset clears and sets allregisters to 0 and centers the oscillator, then beginscalibration.I6-3

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationDIAGNOSTIC MODE OPERATIONIn Transmit All Ones (TAOS) mode the TPOS andTNEG inputs to the transceiver are ignored. The transceivertransmits a continuous stream of 1 's when theTAOS mode is activated. TAOS can be commandedsimultaneously with Local Loopback, but is inhibitedduring Remote loopback.In Remote Loopback (RLOOP) mode, the transmitdata and clock inputs (TPOS, TNEG and TCLK) areignored. The RPOS and RNEG outputs are loopedback through the transmit circuits and output on niPand TRING at the RCLK frequency. Receiver circuitsare unaffected by the RLOOP command and continueto output the RPOS, RNEG and RCLK signals receivedfrom the twisted-pair line.In Local Loopback (LLOOP) mode, the receiver circu itsare inhibited. The transmit data and clock inputs (TPOS,TNEG and TCLK) are looped back onto the receivedata and clock outputs (RPOS, RNEG and RCLK.) Thetransmitter circuits are unaffected by the LLOOP command.The TPOS and TNEG inputs (or a stream of 1 'sif the TAOS command is active) will be transmittednormally. When used in this mode with a crystal, thetransceiver can be used as a stand-alone jitter attenuator.POWER REQUIREMENTSThe SSI 78P300 is a low-power CMOS device. Itoperates from a single +5V power supply which can beconnected externally to both the transmitter and receiver.However, the two inputs must be within ±.3V ofeach other, and decoupled to their respective groundsseparately, as shown in Figure 7. Isolation between thetransmit and receive circuits is provided internally.PIN DESCRIPTIONNAME TYPE DESCRIPTIONMCLK I Master Clock: A 1.544 or 2.048 MHz clock input used to generate internalclocks. Upon Loss of Signal (LOS), RCLK is derived from MCLK. If MCLK notapplied, this pin should be grounded.TCLK I Transmit Clock: Transmit clock input. TPOS and TNEG are sampled on thefalling edge of TCLK.TPOS I Transmit Positive Data: Input for positive pulse to be transmitted on the twistedpairor coaxial cable.TNEG I Transmit Negative Data: Input for negative pulse to be transmitted on thetwisted-pair or coaxial cable.MODE I Mode Select: Setting MODE to logic 1 puts the SSI 78P300 in the Host mode.In the Host mode, the serial interface is used to control the SSI 78P300 anddetermined its status. Setting MODE to logic 0 puts the SSI 78P300 in theHardware (H/W) mode. In the Hardware mode the serial interface is disabledand hard-wired pins are used to control configuration and report status.RNEG/RPOS 0 Receive Negative Data/Receive Positive Data: Received data outputs. Asignal on RNEG corresponds receipt of a negative pulse on RTIP and RRING.A signal on RPOS corresponds to receipt of a positive pulse on RTIP andRRING. RNEG and RPOS outputs are Non-Return-to-Zero (NRZ). In the HostMode, CLKE determines the clock edge (RCLK) at which these outputs arestable and valid. In the Hardware mode both outputs are stable and valid on therising edge or RCLK.RCLK 0 Recovered Clock: This is the clock recovered from the signal received at RTIPand RRING.6-4

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationPIN DESCRIPTION (continued)NAME TYPE DESCRIPTIONXTALIN/ I/O CrystallnputlCrystal Output: An external crystal operating at fourtimes the bitXTALOUTrate (6.176 MHz for DSX-1, 8.192 MHz for CEPT applications with an 18.7 pFload) is required to enable the jitter attenuation function of the SSI 78P300.These pins may also be used to disable the jitter attenuator by connecting theXTALIN pin to the positive supply through a resistor, and tying the XTALOUTpin to ground.DPM 0 Driver Performance Monitor: DPM goes to a logic 1 when the transmit monitorloop (MTIP and MRING) does not detect a Signal for 63 ±2 clock periods. DPMremains at logic 1 until a signal is detected.LOS 0 Loss Of Signal: LOS goes to a logic 1 when 175 consecutive spaces have beendetected. LOS returns to a logic 0 when a mark is de~ected.TTIP/TRING 0 Transmit Tip/Transmit Ring: Differential Driver Outputs. These outputs aredesigned to drive a 25 n load. The transmitter will drive 1 00 n shielded twistedpaircable through a 2:1 step-up transformer without additional components.To drive 75 n coaxial cable, two 2.2 n resistors are required in series with thetransformer.TGND - Transmit Ground: Ground return for the transmit drivers power supply TV+_~TV+ I Transmit Power Supply: +5 VDC power supply input for the transmit drivers.TV+ must not vary from RV+ by more than ±0.3V.MTIP/MRING I Monitor Tip/Monitor Ring: These pins are used to monitor the tip and ringtransmit outputs. The transceiver can be connected to monitor its own outputor the output of another SSI 78P300. To prevent false interrupts in the Hostmode if the monitor is not used, apply a clock signal to one of the monitor pinsand tie the other monitor pin to approximately the clock's mod-level voltage.The monitor clock can range from 100 kHz to the TCLK frequency.RTIP/RRING I Receive Tip/Receive Ring: The AMI signal received from the line is applied atthese pins. A center-tapped, center-grounded, 2:1 step-up transformer isrequired on these pins. Data and clock from the signal applied at these pins arerecovered and output on the RPOS/RNEG, and RCLK pins.RV+ I Receive Power Supply: +5 VDC power supply for all circuits except the transmitdrivers. (Transmit drivers are supplied by TV+.)RGND - Receive Gro_ul"I.9~_§round return for power supply RV+.INT 0 Interrupt (Host Mode): This SSI 78P300 Host mode output goes low to flag thehost processor when LOS or DPM go active. INT is an open-drain output andshould be tied to power supply RV+ through a resistor. INT is reset by clearingthe respective register bit (LOS and/or DPM.)EC1 I Equalizer Control 1 (H/W Mode): The signal applied at this pin in the SSI78P300 Hardware mode is used in conjunction with EC2 and EC3 inputs todetermine shape and amplitude of AMI output transmit pulses.I6-5

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationPIN DESCRIPTION (continued)NAME TYPE DESCRIPTIONSOl I Serial Data In (Host Mode): The serial data input stream is applied to this pinwhen the SSI78P300 operates in the Host mode. SOl is sampled on the riSingedge of SCLK.EC2 I Equalizer Control 2 (H/W Mode): The signal applied at this pin in the SSI78P300 Hardware mode is used in conjunction with EC1 and EC3 inputs todetermine shape and amplitude of AMI output transmit pulses.SOO 0 Serial Data Out (Host Mode): The serial data from the on-chip register is outputon this pin in the SSI78P300 Host mode. If CLKE is high, SOO is valid on therising edge of SCLK. If CL..KE is low SOO is valid on the falling edge of SCLK.This pin goes to a high-impedance state when the serial port is being writtento and when CS is high.EC3 I Equalizer Control 3 (H/W Mode): The signal applied at this pin in the SSI78P300 Hardware mode is used in conjunction with EC1 and EC2 inputs todetermine shape and amplitude of AMI output transmit pulses.CS I Chip Select (Host Mode): This input is used to access the serial interface in theSSI78P300 Host mode. For each read orwrite operation, CS must remain lowfor duration of operation.RLOOP I Remote Loopback (H/W Mode): This input controls loopback functions in theSSI78P300 Hardware mode. Setting RLOOP to a logic 1 enables the RemoteLoopback mode. Se~ing both RLOOP and LLOOP caus~~_a Reset_. ____SCLK I Serial Clock (Host Mode): This clock is used in the SSI 78P300 Host mode towrite data to or read data from the serial interface registers.LLOOP I Local Loopback (H/W Mode): This input controls loopback functions in the SSI78P300 Hardware mode. Setting LLOOP to a logic 1 enables the LocalLoopback Mode.CLKE I Clock Edge (Host Mode): Setting CLKE to logic 1 causes RPOS and RNEG tobe valid on the falling edge of RCLK, and SOO to be valid on the rising edgeof SCLK. When CLKE is a logic 0, RPOS and RNEG are valid on the rising edgeof RCLK, and SOO is valid on the falling edge of SCLK.TAOS I Transmit All Ones (H/W Mode): When set to a logic 1, TAOS causes the SSI78P300 (Hardware mode) to transmit ~ continuous stream of marks at theTCLK frequency. Activating TAOS causes TPOS and TNEG inputs to beignored. TAOS is inhibited during Remote Loopback.6-6

----~SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may damage the device.PARAMETERDC Supply (referenced to GND), RV+, TV+Input Voltage, Any Pin, VIN (see note 1)Input Current, Any Pin, lin (see note 2)Ambient Operating Temperature, TAStorage Temperature, T STGRATINGa to 6.0VRGND -0.03 to RV+ +0.03V-10 to 10mA-40 to 85°C-65 to 150°C-----~~------- - ---~-~--------1 Excluding RTIP and RRING which must stay within -6V to RV+ + 0.3V.2 Transient currents of upto 100 rnA will not cuase SCR latch-up. TTIP, TRING, TV+ and TGND can withstanda continuous current of 100 rnA.RECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MIN NOM MAX UNITDC supply, RV+, TV+ (see note 1) 4.75 5.0 5.25 VAmbient Operating Temp., T A -40 25 85 °CTotal Power Dissipation, P D 100% Ones Density & 620 - mW(see note 2)Maximum Line Length@ 5.25V1 TV+ must not exceed RV+ by more than ±0.3V.2 Power dissipation while driving 250 load over operating temperature range. Includes device and load.Digital input levels are within 10% of the supply rails and digital outputs are driving a 50pF capacitive load.DIGITAL CHARACTERISTICSTA = -40° to 85°C, V+ = 5.0 V± 5%, GND = OVIV IH High Level Input Voltage 2.0 -(pins 1-5, 10, 23-28) (see note 1, 2)-----V IL Low Level Input Voltage - 0.8(pins 1-5, 10, 23-28) (see note 1,2)----"_..--r------V OH High Level Output Voltage lOUT = -400 IlA 2.4 - -(pins 6-8, 11, 12, 23, 25)(see note 1, 2)----VOL Low Level Output VoltagelOUT = 1.6 rnA 0.4(pins 6-8, 11, 12, 23, 25)(see note 1, 2)ILL Input Leakage Current a ±1013L Three -State Leakage Currenta ±10(pin 25) (see note 1)1 Functionality of pins 23 and 25 depends on mode. See Host / Hardware Mode descnptlons.2 Output drivers will output CMOS logic levels into CMOS loads.6-7VV---~V---VJ..lAJ..lA

~ ~--SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationELECTRICAL SPECIFICATIONS (continued)ANALOG SPECIFICATIONSTA = -40° to 85°C, V+ = 5.0 V± 5%, GND = OVPARAMETERTEST CONDITIONSMIN NOM MAX UNITAMI Output Pulse Amplitudes DSX-1 Measured at the DSXCEPTLoad Presented to Transmitter OutputJitted Addedby the Transmitter(see note 1)Sensitivity Below DSXLoss of Signal ThresholdData Decision Threshold10 Hz - 8 kHz8 kHz - 40 kHz10 Hz - 40 kHzBroad Band(OdB = 2.4V)DSX-1CEPTAllowable Consecutive Zeros Before LOSInput Jitter Tolerance 10kHz - 100 kHzJitter Attenuation Curve Corner Frequency(see note 2)Measured at Line Side1 Input Signal to TCLK is jitter-free.2 Circuit attenuates jitter at 20 dB/decade above the corner frequency.2.4 3.0 3.6 V2.7 3.0 3.3 V- ------------_ ...•25 .Q0.01 UI0.025 UI~--- 0.025 UI..---_.0.05 UI13.6 - dB500 mV~--------- 0.3 - V63 70 77 %peak43 50 57 %peak160 175 190 -0.4 - UI,-----~---3 - HzTABLE 1: Equalizer Control InputsEC3 EC2 EC1 LINE LENGTH CABLE LOSS0 1 1 0- 133 ft ABAM 0.6dB1 0 0 133 - 266 ft ABAM 1.2 dB1 0 1 266 - 399 ft ABAM 1.8 dB1 1 0 399 - 533 ft ABAM 2.4 dB1 1 1 533 - 655 ft ABAM 3.0 dB0 0 0 cCln Recommendation G.7030 1 0 FCC Part 68, Option A0 1 1 ECSA T1C1.2APPLICATIONDSX-1CEPTCSUt---~-------FREQUENCY1.544 MHz2.048 MHz1.544 MHz6-8

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationTABLE 2: 78P300 Master Clock and Transmit Timing CharacteristicsPARAMETER CONDITIONS MIN NOMMAXUNITMaster clock frequency MCLK DSX-1 - 1.544,--MCLK CEPT 2.048--Master clock tolerance MCLKt - ±100Master clock duty cycle MCLKd 40 -Crystal frequency fc DSX-1 - 6.176f---fc CEPT - 8.192Transmit clock frequency TCLK DSX-1 - 1.544--TCLK CEPT - 2.048Transmit clock tolerance TCLKt - ----Transmit clock duty cycle TCLKd 10 -TPOSfTNEG toTCLK setup timeTCLK to TPOS/TNEGHold timetSUT 25tHT 25--- MHz- MHz- ppm60 %- MHz- MHz- MHz- MHz±50 ppm90 %- ns- nsTCLKTPOSTNEGt,HT>k=f~ II-•FIGURE 1: 78P300 Transmit Clock Timing DiagramHIP1 0BIT CELL I:.. .:-, +­ITRINGFIGURE 2: 50% AMI Coding Diagram6-9

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationRCLKRPOSRNEGRPOSRNEGFIGURE 3: 78P300 Receive Clock Timing DiagramTABLE 3: 78P300 Receive Timing CharacteristicsPARAMETER CONDITIONS MIN NOMl MAX UNITReceive clock duty cycle RCLKd 40 60 %Receive clock pulse width tpw DSX-1 - 324 nstpw CEPT 244 - ns.-RPOS/RNEG to RCLK tSUR DSX-1 - 274 - ns1--rising setup time tSUR CEPT - 194 ns---RCLK rising to RPOSI tHR DSX-1 274 - nsRNEG hold time tHR CEPT -1--194 - ns1 Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.TABLE 4: SSI78P300 Crystal Specifications (External)PARAMETER T1 CEPTFrequency 6.176 MHz 8.192 MHzFrequency Stability ±20 ppm @ 25°C ±20 ppm @ 25°C±25 ppm from -40°C to + 85°C ± 25 ppm from -40°C to + 85°C(Ref 25°C reading)(Ref 25°C reading) ._---------Pullability CL = 11 pF to 18.7 pF, CL = 11 pF to 18.7 pF,+~F = 175 to 195 ppm+~F = 95 to 11 5 ppmCL = 18.7 pF to 34 pF,-~F = 175 to 195 ppm-- ~---CL = 18.7 pF to 34 pF,-~F = 95 to 115 ppmEffective series resistance 40 .Q Maximum 30 .Q MaximumCrystal cut AT ATResonance Parallel ParallelMaximum drive level 2.0mW 2.0mWMode of operation Fundamental FundamentalCrystal holder HC49 (R3W), 'Co = 7 pF Maximum HC49 (R3W), Co = 7 pF MaximumC M= 17 pF typicalC M= 17 pF typical- --_.-------6-10

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationCSI~ ____________ ~ISCLKADDRESS / COMMAND BYTESDI/SDO (MY I AO I A1 I ~ i "I A41 ASI AS I00DATA INPUT / OUTPUT BYTEI 01 I 02 1 03 i041 05 1 06 1 07 JADDRESS/COMMANDBYTERiWoAORm= 1; READRm = 0 : WRITEo o o o XA6x = DON'T CAREINPUTDATABYTECLEAR INTERRUPTSNOTE: Output DataI-----r---+------,,-----.----f------r---+-----. Byte same as InputData Byte shown atLOS DPM EC1 EC2 EC3 REMOTE LOCAL TAOS left. except for Bits 05DO (LSB)D7 (MSB) through 07 shown inL..-__ -'--__.l...-___ L..-_-..L __-1-__--L__-'--__.......J Table 6.FIGURE 4: SSI 78P300 Serial Interface Data StructureTABLE 5: SSI78P300 Serial Data Output Bits (See Figure 4)BIT 05 BIT 06 BIT 07 STATUS0 0 0 Reset has occurred, or no program input.I0 0 1 TAOS active.. - --------0 1 0 Local Loopback active------0 1 1 TAOS and Local Loopback active-1 0 0 Remote Loopback active1 0 1 DPM has c~anged state since last Clear DPM occurred1 1 0 LOS has changed state since last Clear LOS occurred1 1 1 LOS and DPM have both changed state since last Clear DPM andClear LOS occurred6-11

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationSCLKSDIDATA BYTEFIGURE 5: SSI 78P300 Serial Data Input Timing DiagramSCLKSDOCLKE = 1SDOCLKE = o~_---JFIGURE 6: SSI 78P300 Serial Data Output Timing Diagram6-12

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationTABLE 6: SSI78P300 Serial 1/0 Timing Characteristics (See Figures 5 and 6)PARAMETER CONDITIONS MIN NOM' MAX UNITRise/Fall time - any digital output tRF Load 1.6 rnA, 50 pF - - 100 nsSOl to SCLK setup time tDe 50 - - nsSCLK to SOl hold time teDH 50 - - nsSCLK low time tel 240 - nsSCLK high time teH 240 - nsSCLK rise and fall time tR, tF - - 50 nsCS to SCLK setup time tcc 50 - - nsSCLK to CS hold time teCH 50 - - nsCS inactive time teWH 250 - - nsSCLK to SOO valid tCDV - - 200 nsSCLK falling edge or CS rising teDZ - 100 - nsedge to SOO high Z, TYPical figures are at 25°C and are for deslng aid only; not guaranteed and not subject to production testing.APPLICATION INFORMATIONSS178P300 1.544 MHz T1 INTERFACEAPPLICATIONSFigure 7 is a typical 1.544 MHz T1 application. The SSI78P300 is shown in the Host mode with the 2180A T1 /ESF Framer providing the digital interface with the hostcontroller. Both devices are controlled through theserial interface. The power supply inputs are tied to acommon bus with appropriate decoupling capaCitorsinstalled (1.0 ~F on the transmit side, 68 ~F and 0.1 ~Fon the receive side.)SSI 78P300 2.048 MHz E1/CEPT INTERFACEAPPLICATIONSIFigure 8 is a typical 2.048 MHz E1/CEPT application.The SSI 78P300 is shown in Hardware mode with the2181 E1/CRC4 Framer. ReSistors are installed in linewith the transmit transformerfor loading a 75 Q coaxialcable. The in-line resistors are not required fortransmission on 100 Q shielded twisted-pair lines. Asin the T1 application Figure 7, this configuration isillustrated with a crystal in place to enable the SSI78P300 Jitter Attenuation Loop, and a single powersupply bus. The hard-wired control lines for TAOS,LLOOP and RLOOP are individually controllable, andthe LLOOP and RLOOP lines are also tied to a singlecontrol for the Reset function.•6-13

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationTO HOST CONTROLLER2180AT1 ESFFRAMERTMSYNC TFSYNCcs TCLKSDOSOliNTSCLKTPOSTNEGSPSRPOSMCLKTCLKTPOSTNEGMODERNEGSSI78P300TRANSCEIVERCLKESCLKcsSDOSDIHITV+RNEGRPOSRGND~RCLKRCLKXTALINRV+RRINGXTALOUTRTIPDPMMRINGLOSMTiPTTIPTRINGOVTGNDTV+1.011FV+INOTEI11 THE SSI 78P300 IS COMPATIBLE WITH A WIDE VARIETY OF DIGITAL FRAMING AND SIGNALING DEVICES, INCLUDING THELXP 2180A, LXP2181, DS21sOA, MT8976, AND R8070.INOTEI21 WHEN THE SSI 78P300 IS CONNECTED TO THE CROSS-CONNECT FRAME THROUGH A LOW LEVEL MONITOR JACK,RECEIVE TRANSFORMER SHOULD BE 1 : 2 : 2 TO BOOST THE INPUT SIGNAL.FIGURE 7: Typical SSI78P300 1.544 MHz T1 Application (Host Mode)6-14

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter Attenuation2.048 MHz CLOCKLXP2181E1/CRC4FRAMER(NOTEI@SSI78P300TRANSCEIVERMCLKTAOSTCLKTPOSTNEGRNEGRPOSRCLKTCLKTPOSTNEGMODERNEGRPOSRCLKXTALINLLOOPRLOOPEC3EC2EC1RGNDRV+RRINGXTALOUTRTIPDPMLOSniPTGNDMRINGMTIPTRINGTV+I~------~~----------------~~-+-----V+1.011FINOTEI11I NOTE/212.2 n RESISTORS REQUIRED ONLY FOR 75 n COAXIAL CABLE.NOT REQUIRED FOR TRANSMISSION ONTO 100 n CABLE.THE SSI7BP300 IS COMPATIBLE WITH A WIDE VARIETY OF FRAMING ANDSIGNALING DEVICES, INCLUDING THE LXP21 B1, DS21 B1. MTB979, ANDRB070.FIGURE 8: Typical SSI 78P300 2.048 MHz E1 Application (Hardware Mode)6-15

SSI78P300T1/E1 Integrated ShortHaul Transceiver withReceive Jitter AttenuationPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.a..en a..MCLK CLKEITAOS 0 0« ..J..JI:::::0..J(!) en ~TCLK SCLKlLLOOP ~ ill ~ a:ill 0 ..J..J ~ ..Jz a.. ()() ..J ()TPOS CS/RLOOP ~ ~ ~ ::2 () en I~TNEGSDO/EC3MODESDIIEC2MODESDO/EC3RNEGiNT/EC1RNEG 24 SDI/EC2RPOS 23 INT/EC1RPOSRGNDRCLK 22 RGNDRCLKRV+XTALIN 21 RV+XTALINRRINGXTALOUT 20 RRINGXTALOUTRTIPDPM 19 RTIPDPMMRING12 13 14 15 16 17 18LOSMTIPen a.. 0 + (!) a.. (!)niP TRING 0 z > z i= zTGNDTV+..J ~ a: (!) ~ ::2 a:~ ~ ::228·Pin DIP28·Pin PLCCORDERING INFORMATIONPART DESCRIPTION ORDER NO. PKG.MARKSSI 78P300 28-Pin PLCC 78P300-IH 78P300-IHSSI 78P300 28-Pin DIP 78P300-IP 78P300-IPNo responsibility is assume

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receive Jitter AttenuationDESCRIPTIONThe 551 78P304A is a fully integrated low-power transceiverfor both North American 1.544 MHz (T1), andEuropean 2.048 MHz (E1/CEPT) applications. It featuresa constant low output impedance transmitter allowingfor high transmitter return loss in E 1 applications.Transmit pulse shapes (D5X-1 or E1/CEPT) are selectablefor various line lengths and cable types.The 551 78P304A provides receive jitter attenuationstarting at 3 Hz, and is microprocessor controllablethrough a serial interface.The 5S178P304A offers a variety of diagnostic featuresincluding transmit and receive monitoring. The deviceincorporates an on-chip crystal oscillator, and also acceptsdigital clock inputs. It uses an advanced doublepoly,double-metal CM05 process and requires only asingle 5-volt power supply.APPLICATIONS• PCM I Voice Channel Banks• Data Channel Bank I Concentrator• T1 I E1 multiplexer• Digital Access and Cross-connect Systems (DAC5)• Computer to PBX interface (CPI & DMI)• High speed data transmission lines• Interfacing Customer Premises Equipment to a C5U• Digital Loop Carrier (DLC) terminalsDecember 1993FEATURES• Low power consumption (400 mW maximum)40% less than the SSI 78P300• Constant low output impedance transmitterregardless of data pattern• High transmit and receive return loss• Meets or exceeds all industry specificationsIncluding CCITT G.703, ANSI T1.403 and ATTPub 62411• Compatible with most popular PCM framersIncluding the 2180A (T1) and 2181/2181A (E1)• Line driver, data recovery and clock recoveryfunctions• Minimum receive signal of 500 mV• Selectable slicer levels (CEPT/DSX-1) improveSNR• Programmabletransmit equalizer shapes pulsesto meet DSX-1 pulse template from 0 to 655 ft• Local and remote loopback functionsTransmit I Receive perfonnance monitors withDPM and LOS outputs• Receiver jitter tolerance 0.4 UI from 40 kHz to100 kHz• Receive jitter attenuation starting at 6 Hz• Microprocessor controllable• Available in 28 pin DIP or PLCCIFIGURE 1: BLOCK DIAGRAMMODE ------+-~H ST mw[Nf EClSDI EC2SDo EC3CS RLOOPSCLK LLOOPCLKE TAOSTPOS--+-~TNEG --+_-.1TCLK --+--+-/MCLK-f---I~CONTROLEQUALIZERSYNCHRONIZERXTALlN~l--I;=::::::J===1XTALOUT ..... !----!RCLK4r---L-,,---.J~-----~TTIP/-------~TRINGRTIPRRINGRPOS ..... f----iRNEG41--L~:::'--.JLOS -4-1f---------fMTIPMRINGDPM~f----------------~1293 - rev.6-17

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationFUNCTIONAL DESCRIPTIONThe SSI 78P304A is a fully integrated PCM transceiverfor both 1.544 MHz (DSX-1) and 2.048 MHz (E1)applications. It allows transmission of digital data overexisting twisted-pair installations. The SSI 78P304Atransceiver interfaces with two twisted-pair lines, onetwisted-pair for transmit, one twisted-pair for receive.TRANSMITTERData received for transmission onto the line is clockedserially into the device at TPOS and TNEG. Inputsynchronization is supplied by the transmit clock(TCLK). The transmitted pulse shape is determined byEqualizer Control signals EC 1 through EC3 as shownin Table 1. Referto Table 2 and Figure 2 for master andtransmit clock timing characteristics. Shaped pulses areapplied to the AMI line driver for transmission onto theline at niP and TRING. Equalizer Control signals maybe hardwired in the Hardware mode, or input as part ofthe serial data stream (SOl) in the Host mode.Pulses can be shaped for either 1.544 or 2.048 MHzapplications. 1.544 MHz pulses for DSX-1 applicationscan be programmed to match line lengths fromO to 655feet of ABAM cable. The SSI 78P304A also matchesFCC and ECSA specifications for CSU applications. A1 :1.15 transmit transformer is used for all 1.544 MHzsystems.2.048 MHz pulses can drive coaxial or shielded twistedpairlines. For E1 systems, a 1:2 transmit transformerand series resistors are recommended. This designmeets or exceeds all CCIIT and European PIT specificationsfor transmit and receive return loss. A 1: 1 or1 :1.26 transformer may be used without series resistors.DRIVER PERFORMANCE MONITORThe transceiver incorporates a Driver PerformanceMonitor (DPM) in parallel with ITIP and TRING at theoutput transformer. The DPM output goes high upondetection of 63 consecutive zeros. It is reset when a oneis detected on the transmit line, or when a reset commandis received.LINE CODEThe SSI 78P304A transmits data as a 50% AM I linecode as shown in Figure 3. The output driver maintainsa constant low output impedance regardless of whetherit is driving marks or spaces.RECEIVERThe SSI 78P304A receives the signal input from onetwisted-pair line on each side of a center-groundedtransformer. Positive pulses are received at RTIP andnegative pulses are received at RRING. Recovereddata is output at RPOS and RNEG, and the recoveredclock is output at RCLK. Refer to Table 3 and Figure 4for SSI 78P304A receiver timing.The signal received at RPOS and RNEG is processedthrough the peak detector and data slicers. The peakdetector samples the inputs and determines the maximumvalue of the received Signal. A percentage of thepeak value is provided to the data slicers as a thresholdlevel to ensure optimum signal-to-noise ratio. For DSX-1 applications (determined by Equalizer Control inputsEC 1 - EC3 *000) the threshold is set to 70% of the peakvalue. This threshold is maintained above 65% for up to15 successive zeros over the range of specified operatingconditions. For E1 applications (EC inputs = 000 or001) the threshold is 50%.The receiver is capable of accurately recovering Signalswith up to -13.6 dB of attenuation (from 2.4V), correspondingto a received signal level of approximately 500mV. Maximum line length is 1500 feet of ABAM cable(approximately 6 dB of attenuation). Regardless ofreceived signal level , the peak detectors are held abovea minimum level of .3V to provide immunity fromimpulsive noise.After processing through the data slicers, the receivedsignal is routed to the data and clock recovery sections,and to the receive monitor. The receive monitor generatesa Loss of Signal (LOS) output upon receipt of 175consecutive zeros (spaces). The receiver monitor loadsa digital counter at the RCLK frequency. The count isincremented each time a zero is received, and reset tozero each time a one (mark) is received. Upon receiptof 175 consecutive zeros the LOS pin goes high, and asmooth transition replaces the RCLK output with theMCLK. (If MCLK is not supplied the RCLK output will bereplaced with the centered crystal clock.) The LOS pinis reset immediately upon receipt of a one.Recovered clock signals are supplied to the jitter attenuatorand the data latch. The recovered data is passedto the elastic store where it is buffered and synchronizedwith the dejittered recovered clock (RCLK).6-18

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationJITTER ATTENUATIONJitter attenuation of the SSI 78P304A clock and dataoutputs is provided by a Jitter Attenuation Loop (JAL)and an Elastic Store (ES). An external crystal oscillatingat 4 times the bit rate provides clock stabilization. Referto Table 4 for crystal specifications. The ES is a 32 x 2-bit register. Recovered data is clocked into the ES withthe recovered clock signal, and clocked out of the ESwith the dejittered clock from the JAL. When the bitcount in the ES is within two bits of overflowing orunderflowing, the ES adjusts the output clock by 1/8 ofa bit period. The ES produces an average delay of 16 bftsin the receive path.OPERATING MODESThe SSI78P304A transceiver can be controlled throughhard-wired pins (Hardware mode) or by a microprocessorthrougha serial interface (Host mode). The mode ofoperation is set by the MODE pin logic level. The SSI78P304A can also be commanded to operate in one ofseveral diagnostic modes.HOST MODE OPERATIONTo allow a host microprocessor to access and controlthe SSI 78P304A through the serial interface, MODE isset to 1. The serial interface (SDI/SDO) uses a 16-bitword consisting of an 8-bit Command/Address byte andan 8-bit Data byte. Figure 5 shows the serial interfacedata structure and timing.The Host mode provides a latched Interrupt output (INT)which is triggered by a change in the Loss of Signal(LOS) and/or Driver Performance Monitor (DPM) bits.The Interrupt is cleared when the interrupt condition nolonger exists, and the host processor enables the respectivebit in the serial input data byte. Host mode alsoallows control of the serial data and receive data outputtiming. The Clock Edge (CLKE) signal determines whenthese outputs are valid, relative to the Serial Clock(SCLK) or RCLK as follows:CLKE Output Clock Valid EdgeRPOS RCLK RisingLOW RNEG RCLK RisingSDO SCLK FallingRPOS RCLK FallingHIGH RNEG RCLK FallingSDO SCLK RisingThe SSI78P304A serial port is addressed by setting bitA4 in the Address/Command byte, corresponding toaddress 16. The SSI 78P304A contains only a singleoutput data register so no complex chip addressingscheme is required. The register is accessed bycausing the Chip Select (CS) input to make a transitionfrom high to low. Bit 1 of the serial Address/Commandbyte provides Read/Write control when the chip isaccessed. A logic 1 indicates a read operation, and alogic 0 indicates a write operation. Table 6 lists serialdata output bit combinations for each status. Serialdata I/O timing characteristics are shown in Table 6,and Figures 6 and 7.HARDWARE MODE OPERATIONIn Hardware mode the transceiver is accessed andcontrolled through individual pins. With the exception ofthe INT and CLKE functions, Hardware mode providesall the functions provided in the Host mode. In theHardware mode RPOS and RNEG outputs are valid onthe rising edge of RCLK. To operate in Hardware mode,MODE must be setto O. Equalizer Control signals (EC1through EC3) are input on the Interrupt, Serial Data Inand Serial Data Out pins. Diagnostic control for RemoteLoopback (RLOOP), Local Loopback (LLOOP), andTransmit All Ones (TAOS) modes is provided throughthe individual pins used to control serial interface timingin the Host mode.RESET OPERATIONUpon power up, the transceiver is held static until thepower supply reaches approximately 3V. Upon crossingthis threshold, the device begins a 32 ms reset cycleto calibrate the transmit and receive delay lines and lockthe Phase Lock Loop to the receive line. A referenceclock is required to calibrate the delay lines. The transmitterreference is provided by TCLK. The crystal oscillatorprovides the receiver reference. If the 78P304Acrystal oscillator is grounded, MCLK is used as thereceiver reference clock.The transceiver can also be reset from the Host orHardware mode. In Host mode, reset is commanded bysimultaneously writing RLOOP and LLOOP to the register.In Hardware mode, reset is commanded byholding RLOOP and LLOOP high simultaneously for200 ns. Reset is initiated on the falling edge of the resetrequest. In either mode, reset clears and sets all registersto 0 and centers the oscillator, then calibrationbegins.I6-19

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationDIAGNOSTIC MODE OPERATIONIn Transmit All Ones (TAOS) mode the TPOS andTNEG inputs to the transceiver are ignored. The transceivertransmits a continuous stream of 1's when theTAOS mode is activated. TAOS can be commandedsimultaneously with Local Loopback, but is inhibitedduring Remote Loopback.In Remote Loopback(RLOOP) mode, the transmit dataand clock inputs (TPOS, TNEG and TCLK) are ignored.The RPOS and RNEG outputs are looped back throughthe transmit circuits and output on TTIP and TRING atthe RCLK frequency. Receiver circuits are unaffectedby the RLOOP command and continue to output theRPOS, RNEG and RCLK signals received from thetwisted-pair line.In Local Loopback (LLOOP) mode, the receiver circuitsare inhibited. The transmit data and clock inputs (TPOS,TNEG and TCLK) are looped back onto the receive dataand clock outputs (RPOS, RNEG and RCLK.) Thetransmitter circuits are unaffected by the LLOOP command.The TPOS and TNEG inputs (or a stream of 1'sif the TAOS command is active) will be transmittednormally. When used in this mode with a crystal, thetransceiver can be used as a stand-alone jitter attenuator.POWER REQUIREMENTSThe SSI 78P304A is a low-power CMOS device. Itoperates from a single +5 V power supply which can beconnected externally to both the transmitter and receiver.However, the two inputs must be within ± .3V ofeach other, and decoupled to their respective groundsseparately, as shown in Figure 8. Isolation between thetransmit and receive circuits is provided internally.PIN DESCRIPTIONNAME TYPE DESCRIPTIONMCLK I MasterClock:A 1.544or2.048 MHzclock inputusedtogenerate internal clocks.Upon Loss of Signal (LOS), RCLK is derived from MCLK.lf MCLK is not applied,this pin should be 9!_~unded.TCLK I Transmit Clock: Transmit clock input. TPOS and TNEG are sampled on thefalling edge of TCLK.TPOS I Transmit Positive Data: Input for positive pulse to be transmitted on the twistedpairor coaxial cable.TNEG I Transmit Negative Data: Input for negative pulse to be transmitted on thetwisted-pair or coaxial cable.MODE I Mode Select: Setting MODE to logic 1 puts the SSI 78P304A in the Host mode.In the Host mode, the serial interface is used to control the SSI 78Q904A anddetermine its status.Setting MODE to logic 0 puts the SSI 78P304A in the Hardware (H/W) mode. Inthe Hardware mode the serial interface is disabled and hard-wired pins are usedto control configuration and report status.RNEG/RPOS 0 Receive Negative/Positive Data: Received data outputs. A signal on RNEGcorresponds to receipt of a negative pulse on RTIP and RRING. A signal onRPOS corresponds to receipt of a positive pulse on RTIP and RRING. RNEGand RPOS outputs are Non-Return-to-Zero (NRZ). In the Host mode, CLKEdetermines the clock edge at which these outputs are stable and valid. In theHardware mode both outputs are stable and valid on the rising edge of RCLK.RCLK 0 Recovered Clock: This is the clock recovered from the signal received at RTIPand RRING.6-20

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationPIN DESCRIPTION (continued)NAME TYPE DESCRIPTIONXTALIN I XTALOUT I Crystal Input / Crystal Output: An external crystal operating at four times the bitrate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an 18.7pF load)is required to enable the jitter attenuation function of the SSI 78P304A. Thesepins may also be used to disable the jitter attenuator by connecting the XTALINpin to the positive supply through a resistor, and tying the XTALOUT pin toground.DPM 0 Driver Performance Monitor: DPM goes to a logic 1 when the transmit monitorloop (MTIP and MRING) does not detect a signal for 63 ±2 clock periods. DPMremains at logic 1 until a signal is detected.LOS 0 Loss of Signal: LOS goes to a logic 1 when 175 consecutive spaces have beendetected. LOS returns to a logic 0 when a mark is received.TTIP I TTRING 0 Transmit Tip I Transmit Ring: Differential Driver Outputs. These low impedanceoutputs achieve maximum power savings through a 1 :1.15 transformer (T1), ora 1:1 or 1 :1.26 transformer (E1) without additional components. To providehigher return loss for E1 systems, resistors may be used in series with a 1:2transformer (use 150 resistors for 1200 terminations, and 9.30 resistors for 750terminations. )TGND - Transmit Ground: Ground return for the transmit drivers power supply TV +.TV+ I Transmit Power Supply: +5 VDC power supply input forthe transmit drivers. TV +must not vary fro_~ RV+ ~y more than ±0.3V.MTIP / MRING I Monitor Tip I Monitor Ring: These pins are used to monitor the tip and ringtransmit outputs. The transceiver can be connected to monitor its own output orthe output of another 78P304A on the board. To prevent false interrupts in thehost mode if the monitor is not used, apply a clock signal to one of the monitorpins and tie the other monitor pin to approximately the clock's mid-level voltage.The monitor c!c:>~~_~~_~ rang~ from_~ 90k~~~~_!~e TCLK frequency.RTIP I RRING 0 Receive Tip / Receive Ring: The AMI signal received from the line is applied atthese pins. A center-tapped, center-grounded, 2:1 step-up transformer isrequired on these pins. Data and clock from the signal applied at these pins arerecovered an~?~~p~! on the R~OS/~_~5G, an~~~~J~~~s.RV+ I Received Power Supply: +5 VDC power supply for all circuits except thetransmit drivers. (Transmit drivers are supplied by TV+.)RGND --._--_. ----.. -~-....--.-...------.----.- --.~--~----.~Receive Gr()_LJl1d:G_r()LJ_~_gJ:~turn f

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationPIN DESCRIPTION (continued)NAME TYPE DESCRIPTIONSOl I Serial Data In (Host Mode): The serial data input stream is applied to this pinwhen the SSI78P304A operates in the Host mode. SOl is sampled on the riSingedge of SCLKEC2 I Equalizer Control 2 (H/W Mode): The signal applied at this pin in the SSI78P304A Hardware mode is used in conjunction with EC1 and EC3 inputs todetermine shape and amplitude of AMI output transmit pulses.SOO 0 Serial Data Out (Host Mode): The serial data from the on-chip register is outputon this pin in the SSI 78P304A Host mode. If CLKE is high, SOO is valid on therising edge of SCLK. If CLKE is low SOO is valid on the falling edge of SCLK.This pin goes to a high-impedance state when the serial port is being written toand when CS is high.EC3 I Equalizer Control 3 (H/W Mode): The signal applied at this pin in the SSI78P304A Hardware mode is used in conjunction with EC1 and EC2 inputs todetermine shape and amplitude of AMI output transmit pu!~~s.CS I Chip Select (Host Mode): This input is used to access the serial interface in theSSI78P304A Host mode. For each read orwrite operation, CS must remain lowfor the duration of operation.RLOOP I Remote Loopback (H/W Mode): This input controls loopback functions in theSSI78P304A Hardware mode. Setting RLOOP to a logic 1 enables the RemoteLoopback mode. ~_~!t!r:!~L~th RLOOP and LLOOP'cau~e~~ Reset.SCLK I Serial Clock (Host Mode): This clock is used in the SSI78P304A Host modeto write data to or re~d data from the serial interface regi_~!~t~.LLOOP I Local Loopback (H/W Mode): This input controls loopback functions in the SSI78P304A Hardware mode. Setting LLOOP to a logic 1 enables the LocalLoopback Mode.CLKE I Clock Edge (Host Mode): Setting CLKE to logic 1 causes RPOS and RNEG tobe valid on the falling edge of RCLK, and SOO to be valid on the riSing edge ofSCLK. When CLKE is a logic 0, RPOS and RNEG are valid on the rising edgeof RCLK, and SOO is valid on the falling edge of SCLK.TAOS I Transmit All Ones (H/W Mode): When set to a logic 1, TAOS causes the SSI78P304A (Hardware mode) to transmit a continuous stream of marks at theTCLK frequency. Activating TAOS causes TPOS and TNEG inputs to beignored. TAOS is inhibited during Remote Loopback.6-22

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may damage the device. Normal operation not guaranteed at theseextremes.PARAMETER RATING UNITDC supply (referenced to GND) RV+, TV+ -0 to 6.0 VInput voltage, any pin (see note 1) VIN RGND -0.3 to RV+ + 0.3 VInput current, any pin (see note 2) liN -10 to +10 rnAAmbient operating temperature TA -40 to 85 °C-~~-Storage temperature TSTG -65 to 150 °C1 Excluding RTIP and RRING which must stay within -6V to RV+ + 0.3V.2 Transient currents of upto 100 rnA will not cause SCR latch-up. TTIP, TRING, TV+ and TGND can withstanda continuous current of 100 rnA.RECOMMENDED OPERATING CONDITIONSPARAMETER SYMBOL MIN NOM MAX UNITDC supply (see note 1) RV+, TV+ 4.75 5.0 5.25 V- ---Ambient Operating Temperature TA -40 25 85 °C--------Total power dissipation Po 100% ones density & max - - 400 mW(see note 2) line length @ 5.25V1 TV+ must not exceed RV+ by more than ±O.3 V.2 Power dissipation while driving 250 load over operating temperature range. Includes device and load.Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load.IDIGITAL CHARACTERISTICS (TA = -40° to 85°C, V+ = 5.0V ±5%, GND = OV)PARAMETER CONDITIONS MIN NOM MAXHigh level input voltage VIH 2.0 -(see notes 1 & 2)-~------Low level input voltage VIL - 0.8 V(see notes 1 & 2)---_._- - ------High level output voltage VOH lOUT = -400 jJA 2.4V(see notes 1 & 2)..._--_.- --f----- ----_._---- --Low level output voltage VOL lOUT = 1.6 rnA - 0.4 V(see notes 1 & 2)_._--------_.._---Input leakage current ILL 0 ±10 jJA(see note 3)----- .._----._--_. --------"---_. -------------Three-stateleakage current (see note 2) 13L 0 ±10 jJA1 Functionality of pins 23 and 25 depends on mode. See Host / Hardware Mode descriptions.2 Output drivers will output CMOS logic levels into CMOS loads.3 Except MTIP and MRING ILL = ± 50 IJ.A.6-23UNITV

-~--SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationELECTRICAL SPECIFICATIONS (continued)ANALOG SPECIFICATIONS (TA = -40 to 85 oc, V+ = 5.0V ±5%, GND = OV)PARAMETER TEST CONDITIONS MINAMI Output DSX-1 measured at the DSX 2.4Pulse Amplitudes CEPT measured __ ~LljmL$Jc:je 2.7Load presented to transmitter out~t -Jitter added by 10 Hz - 8 kHz -the transmitter 8kHz-40kHz -(see note 1) 10Hz-40kHz -Broad Band -Sensitivity below DSX (0 dB = 2.4V) 13.65~Loss of Signal threshold -Data decision DSX-1 63threshold CEPT 43Allowable consecutive 160zeros before LOSInput jitter 10kHz - 100 kHz 0.4toleranceJitter attenuation -curve corner frequency (see note 2)NOMMAX3.0 3.63.0 ____ c- ___ ~.375 -._--___ 9J)1- 0.025--_.-- 0.025•. ---~-.- 0.05--_ .. ----_.-- -r----------- ----- ---------------0.3--- -70 7750 57175 190----- .--_._--6 -.--.--~--Minimum Return Loss Transmit Receive(see notes 3 & 4) Min Typ Min Typ._----- 51 kHz - 102 kHz 20 28 20 30 dB102 kHz - 2.048 MHz 20 28 20 30------2.048 MHz - 3.072 MHz 20 24 20 251 Input signal to TCLK is jitter-free.2 Circuit attenuates jitter at 20 dB/decade above the corner frequency.3 In accordance with CCITT G.703/RC6367A return loss specifications (CEPT), when wired as shown inFigure 9.4 Guaranteed by design.UNITVVnUIUIUIUIdB __~.Y~V%peako/oQ.eakUIHz------------dBdB6-24

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationTABLE 1: Equalizer Control Inputs for TransmitterEC3 EC2 EC1 Line Length 1 Cable Loss20 1 1 0- 133 ft ABAM O.6dB1 0 0 133 - 266 ft ABAM 1.2 dB1 0 1 266 - 399 ft ABAM 1.8 dB1 1 0 399 - 533 ft ABAM 2.4 dB1 1 1 533 - 655 ft ABAM 3.0 dB0 0 0 CCITT Recommendation G.7030 0 10 1 0 FCC Part 68, Option A0 1 1 ECSA T1C1.21 Line length from transceiver to DSX-1 cross-connect point.2 Maximum cable loss at 772 kHz.ApplicationDSX-1E1 - Coax (75 Q)E1 - Twisted-pair (120 Q)CSUFrequency1.544 MHz2.048 MHz1.544 MHzI6-25

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationTCLKTPOSTNEGtSUTtHTFigure 2: SSI 78P304A Transmit Clock TimingTTIPTAING•, BIT CEll ,1;"III ...,...LI-------t.,.~,,L- ___ I, -',..4--'- ,-,-, , ,-,- .-- - - - fFigure 3: 50% AMI CodingTABLE 2: SSI78P304A Master Clock and Transmit Timing Characteristics (See Figure 2)Parameter Sym Min Typl MaxMaster clock frequency DSX-1 MCLK - 1.544 -E1 MCLK - 2.048 -Master clock tolerance MCLKt - ±100 -Master clock duty cycle MCLKd 40 - 60Crystal frequency DSX-1 fc - 6.176 -E1 fc - 8.192 -Transmit clock frequency DSX-1 TCLK - 1.544 -E1 TCLK - 2.048 -Transmit clock tolerance TCLKt - - ±50Transmit clock duty cycle TCLKd 40 - 60TPOSITNEG to TCLK setup time tSUT 25 - -TCLK to TPOSITNEG Hold time tHT 25 - -UnitsMHzMHzppm%MHzMHzMHzMHzppm%nsns1 Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.6-26

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationRCLKRPOSRNEGRPOSRNEGHOST MODE'/ CLKE: 0, &r--HIWMODEFIGURE 4: SSI78P304A Receive Clock TimingTABLE 3: SSI78P304A Receive Timing CharacteristiCS (See Figure 4)Parameter Sym Min Typ1 Max UnitsReceive clock duty cycle RCLKd 40 - 60 %Receive clock pulse width DSX-1 tpw - 324 - nsCEPT tpw - 244 - nsRPOS / RNEG to RCLK DSX-1 tSUR - 274 - nsrising setup time CEPT tsuR - 194 - nsRCLK rising to RPOS / DSX-1 tHR - 274 - nsRNEG hold time CEPT tHR - 194 - ns1 Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.TABLE 4: SSI78P304A Crystal Specifications (External)IParameter T1 E1Frequency 6.176 MHz 8.192 MHzFrequency Stability ±20 ppm @ 25° C ±20 ppm @ 25° CPullabilityEffective series resistance 400 Maximum±25 ppm from -40° C to + 85° C ±25 ppm from -40° C to + 85° C(Ref 25° C reading)(Ref 25° C reading)CL = 11 pF to 18.7 pF, +~F = 175 to 195 ppm CL = 11 pF to 18.7 pF, +~F = 95 to 115 ppmCL = 18.7 pF to 34 pF, -~F = 175 to 195 ppmCrystal cut AT ATCL = 18.7 pF to 34 pF, -~F = 95 to 115 ppm300 MaximumResonance Parallel ParallelMaximum drive level 2.0mW 2.0mWMode of operation Fundamental FundamentalCrystal holder HC49 (R3W), Co = 7 pF maximum HC49 (R3W), Co = 7 pF maximumC M= 17 pF typicalC M= 17 pF typical6-27

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter Attenuation~~~------------------------~ISCLK501/500 r FVW 1 AO 1 A1 1 A2 iA3 1 A4 1 ASI AS IADDRESS I COMMAND BYTEDATA INPUT I OUTPUT BYTEDO 1 01 1 02 1 03 i 04 1 05 1 OS 107!~=~IRNiI~1FVW.1 : READANi. 0 : WRITEx = ~ON'T CAREINPUTDATABYTECLEAR INTERRUPTSSET LOOPBACKS OR RESETNOTE' Output Datar----.--t----,-----,---f---,---+-----, Byte same as InputData Byte shown atleft, except for Brts 05through 07 shown in'--_--'-__'---_--'---_--'--_--1.__-'-_---'--__--' Table 9 above.FIGURE 5: SSI78P304A Serial Interface Data StructureTABLE 5: SSI78P304A Serial Data Output Bits (See Figure 5)Bit 05 Bit 06 Bit 07 Status0 0 0 Reset has occurred, or no program input.0 0 1 TAOS active0 1 0 Local Loopback active0 1 1 TAOS and Local Loopback active1 0 0 Remote Loopback active1 0 1 DPM has changed state since last Clear DPM occurred1 1 0 LOS has changed state since last Clear LOS occurred1 1 1 LOS and DPM have both changed state since last Clear DPM and Clear LOSoccurred6-28

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationSCLKSDIFIGURE 6: SSI78P304A Serial Data Input Timing DiagramSCLKSDOCLKE = 1SDOCLKE=O __---JIFigure 7: SSI 78P304A Serial Data Output Timing Diagram6-29

SSI78P304ALQw-Power T1/E1 Integrated Shon HaulTransceiver with Receiver Jitter AttenuationTABLE 6: SSI78P304A Serial 1/0 Timing Characteristics (See Figures 6 and 7)Parameter Sym Min Typl Max Units Test ConditionsRise/Fall time - any digital output tRF - - 100 ns Load 1.6 rnA, 50pFSOl to SCLK setup time tDC 50 - - nsSCLK to SOl hold time tCDH 50 - - nsSCLK low time tCl 240 - - nsSCLK high time tCH 240 - - nsSCLK rise and fall time tR , tF - - 50 nsCS to SCLK setup time tcc 50 - - nsSCLK to CS hold time tCCH 50 - - nsCS inactive time tcwH 250 - - nsSCLK to SOO valid tCDv - - 200 nsSCLK falling edge or CS rising tCDZ - 100 - nsedge to SOO high Z1 Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.6-30

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationAPPLICATION INFORMATIONTABLE 7: E1/CEPT Output Combinations1.544 MHz T1INTERFACE APPLICATIONSFigure 8 is a typical 1.544 MHz T1 application. The SSI78P304A is shown in the Host mode with the 2180A T1 /ESF Framer providing the digital interface with the hostcontroller. Both devices are controlled through the serialinterface. The power supply inputs are tied to acommonbus with appropriate decoupling capacitors installed(1.0 JlF on the transmit side, 68 JlF and 0.1 JlF on thereceive side.)EC001001000000750 Coax1:1, Rt = 10Q1 :2, Rt = 14.3Q1:1, Rt = OQ1 :2, Rt = 9.37Q1200 TWP1:1, Rt = 001 :2, Rt = 1501 :1.26, Rt = 001 :2, Rt = 8.70TO HOST CONTROLLERSDIjNf2180AT1 ESFFRAMERTNEGSPSMCLKTCLKTPOSTNEGMODE78P304ATRANSCEIVERCLKESCLKCsSDOSDIv+ ISCLKRPOSRNEGTNTRNEGRPOSRGND~[JRCLK1.544 MHzRCLKXTALINRV+RRINGXTALOUTRTIPDPMMRINGLOSMTIPniPTAINGOVTGNDTV+1.0~FV+INOTEI11 THE SSI78P304A IS COMPATIBLE WITH A WIDE VARIETY OF DIGITAL FRAMING AND SIGNALING DEVICES, INCLUDING THELXP2180A. LXP2181. DS2180A. MT8976, AND RB070.FIGURE 8: Typical SSI 78P304A 1.544 MHz T1 Application (Host Mode)6-31

SSI78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter Attenuation2.048 MHZ E1/CEPT INTERFACE APPLICATIONSFigure 9 is a 2.048 MHz E1/CEPT coax applicationusing EC code 000 and 150 Rt resistors in line with thetransmit transformer to provide high return loss. Whenhigh return loss is not a critical factor, a 1:1 or 1 :1.26transformer without in-line resistors provides maximumpower savings. Table 7 lists transformer ratios and Rtvalues with associated 2.048 MHz EC codes for both750 coax and 1200 TWP. The SSI78P304A is shownin Hardware mode with the 2181A E1/CRC4 Framer.The hard-wired control lines for TAOS, LLOOP andRLOOP are individually controllable, and the LLOOPand RLOOP lines are also tied to a single control fortheReset function. As in the T1 application Figure 8, thisconfiguration is illustrated with a crystal in place toenable the SSI 78P304A Jitter Attenuation Loop, and asingle power supply bus.LXP2181AE1/CRC4FRAMERINOTEI112.048 MHz CLOCK78P304ATRANSCEIVERMCLKTAOSV+TCLKTCLKLLOOPTPOSTNEGRNEGRPOSRCLKTPOSTNEGMODERNEGRPOSRCLKXTALINRLOOPEC3EC2EC1RGNDRV+RRINGI NOTE 11 I The 78P304A is compatiblewith a wide variety of framingand signaling devices,including the LXP21 ~lA,DS2181A, MT8979, ANDR8070.I NOTEI21 Various transformerratios and associatedRt values are listed inTable 8.XTALOUTDPMLOSTTIPTGNDRTIPMRINGMTIPTRINGTV+1.0 IJ.FV+FIGURE 9: SSI78P304A 2.048 MHz E1 Application (Hardware Mode)6-32

551 78P304ALow-Power T1/E1 Integrated Short HaulTransceiver with Receiver Jitter AttenuationPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.c..C/) c..MCLK CLKEITAOS 0 0« -I-It:: 0TCLK CJ C/) ~-ISCLKlLLOOP ~ UJ ~UJ 0 a:-I-I~ -IZ c.. ()() -I ()TPOS CS/RLOOP f- f- f- :2 () C/)TNEG SDO/EC3 4 3 2 1 28 27 26MODESDI/EC2MODE 25 SDO/EC3RNEGINT/EC1RNEG 24 SDI/EC2RPOS 23 fNT/EC1RPOSRGNDRCLK 22 RGNDRCLKRV+XTALIN 21 RV+XTALINRRINGXTALOUT 20 RRINGXTALOUTRTIPDPM 19 RTIPDPMMRING12 13 14 15 16 17 18LOSMTIPC/) c.. 0 + CJ c.. CJTTIP TRING 0 Z > z F zTGNDTV+I~-I ~ CJ f- a: :2 a:f- f- :228-Pin DIPORDERING INFORMATION28-Pin PLCCIPART DESCRIPTION ORDER NO. PKG.MARKSSI 78P304A 28-Pin DIP 78P304A-IP 78P304A-IPSSI 78P304A 28-Pin PLCC 78P304A-IH 78P304A-IHNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-69141293 - rev. 6-33 ©1991 Silicon Systems, Inc.

Notes:6-34

DESCRIPTIONThe SSI 78P7200 is a line interface transceiver Ieintended for DS-3 (44.736 Mbitls) and E3 (34.368Mbitls) applications. The receiver has a very widedynamic range and is designed to accept HDB3 orB3ZS-encoded Alternate-Mark Inversion (AMI) inputs;it provides clock, positive data, negative data, and lowlevelsignal detector logical outputs. An on-chip equalizerimproves the intersymbol interference tolerance on thereceive path. The transmitter converts clock and datainput signals into AMI pulses of the appropriate shapefor transmission. A line buildout (LBO) equalizer maybe selected to shape the outgoing pulses for shorterline lengths. The SSI 78P7200 requires a single 5 voltsupply and is available in DIP and surface mountpackages.The 78P7200 works in either rate of DS-3 or E3 bysimple external components modification.FEATURESSSI78P7200E3/0S-3 Line Interfacewith Receive Eiualizer'4Gm,m@jE·ZiUNovember 1994• Single chip transmit and receive Interface forE3 (34.368 Mbit/s) or 05-3 (44.736 Mbit/s)applications• On-chip Receive Equalizer• Unique clock recovery circuit, requires nocrystals, tuned components or external clock• Selectable transmit line buildout (LBO) toaccommodate shorter line lengths• Compliant with ANSI 11.102 - 1987,TR-TSY-000499, CCITT G.703 and G.823• Low-level input signal indication• Available in DIP or surface mount packages• -40°C to +85°C operating range• Pin-compatible with 551 78P236, 78P2361 and78P2362BLOCK DIAGRAMLlN+PIN DIAGRAMCPDI~CLF1NCRLlN-LOWSIGDVCCRCLK NCR RPOSRFORGNDRVCCTGNDLOUT+NCTLOUT-LBOOPT1TPOSRNEGRCLKDGNDNCDLF2LF1OPT2TYCCTCLKTNEGOPT2 LBO OPT128-Pin DIP1194 - rev.6-35CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI78P7200E3/0S-3 Line Interfacewith Receive EqualizerFUNCTIONAL DESCRIPTIONThe SSI 78P7200 is a single chip line interface ICdesigned to work with a 44.736 Mbitls OS-3 or 34.368Mbitls E3 signal. The receiver recovers clock, positivedata and negative data from an Alternate Mark Inversion(AMI) signal. The input signal should be B3ZS or HOB3coded.The transmitter accepts CMOS level logical clock,positive data and negative data and converts them tothe AMI signal to drive a 750 coaxial cable.Programmable internal Line Buildout (LBO) circuitryeliminates the need for external LBO networks for OS-3 applications. When the option pins are properlyselected, the shape of the transmitted signal throughany cable length of 0 to 450 feet complies with thepublished templates of ANSI T1.1 02-1987, CCITTG.703 and TR-TSY-000499. The SSI 78P7200 isdesigned to work with a B3ZS or HOB3 coded signal.The B3ZS or HOB3 encoding and decoding functionsare normally included in the framer ICs or can easilybe implemented in a PAL.RECEIVERThe receiver input is normally transformer-coupled tothe AMI signal. The inputs to the IC are internallyreferenced to RVCC. Since the input impedance of theSSI78P7200 is high, the AMI line must be terminatedin 750. The input signal to the SSI 78P7200 must belimited to a maximum of three consecutive zeros usinga coding scheme such as B3ZS or HOB3.The AMI signal first enters a fixed equalizer which isdesigned to overcome the intersymbol interferencecaused by long cable lengths and crosstalk. This fixedequalizer is optimized for OS-3 application and itseffect should be compensated by an external filtercircuit similar to Fig. 1, for all square shaped signalssuch as OS3-high or 34 Mbit/s E3. The signal is theninput to a variable gain differential amplifier whoseoutput is maintained at a constant voltage levelregardless of the input voltage level. The gain of thisamplifier is adjusted by detecting the peak of the signaland comparing it to a fixed reference.The output of the variable gain amplifier is compared toa threshold value which is a fixed percentage of thesignal peak. In this way, even though the input signalamplitude may fall below the minimum value that canbe regulated by the variable gain circuit, the properdetection threshold is maintained.Outputs of the data comparators are connected to theclock recovery circuits. The clock recovery systememploys a unique phase locked loop which has anauxiliary frequency-sensitive acquisition loop which isactive only when cycle-slipping occurs between thereceived signal rate and the internal oscillator.This system permits the loop to independently lock tothe frequency and phase of the incoming data streamwithout the need for high preciSion and/or adjustableoscillator or tuned circuits.The response characteristic for the phase locked loopis established by external filter components, RLF1,RLF2 and CLF1. The values of these components arespecified such that the bandwidth of the phase lockedloop is greater than 200 kHz.The jitter tolerance of the SSI 78P7200 exceeds therequirements of TR-TSY -000499 for Category IIequipment for OS-3 rate and exceeds the requirementsof cCln G.823 for E3 rate. The jitter transfer functionis maximally flat so the IC doesn't add any significantjitter to the system.Figure 2 shows the recovered clock (RCLK), positivedata (RPOS) and negative data (RNEG) signals timing.The data is valid on the rising edge of the clock. Theminimum setup and hold times allow easy interface toframer circuits. These signals are CMOS-level outputs.Should the input Signal fall below a minimum value,the LOWSIG pin goes active low. A time delay isprovided before this output is active so that transientinterruptions do not cause false indications. This signalshould be used as one of many indications to the cabledisconnect; the framer device should count the numberof zeros to declare the loss of signal. The RPOS andRNEG signals generate random data following asilence period. The framer device should ignore RPOSand RNEG data if the LOWSIG pin is active low.6-36

SSI78P7200E3/DS-3 Line Interfacewith Receive EqualizerTRANSMITIERThe transmitter accepts unipolar CMOS level logicalclock (RCLK), positive data (RPOS) and negative data(RNEG) signals and generates high current drive pulseson the LOUT + and LOUT- pins. When properlyconnected to a center tapped transformer, an AMIpulse is generated which can drive a 75Q coaxialcable.Figure 3 shows the timing for the transmitter logicsignals. The output pulse width is internally set and isnot sensitive to input clock (TCLK) pulse width.When a recommended transformer is used and optionpins are properly set, the transmitted pulse shape atthe end of a 75Q terminated cable of 0 to 450 feet willfit the template for OSX3 pulse published in ANSIT1.102-1987, BELLCORE TR-TSY -000499 andCCITT G.703 documents for RFO = 5.23 kQ.For34 MbiVs E3 application, when RFO = 6.81 kQ, thetransmitted pulse for a short cable matches therequirements of CCITT G.703 when both LBO andOPT1 pins are set LOW.The SSI 78P7200 incorporates a selectable LineBuildout (LBO) equalizer in the transmitter path. ForOS-3 applications, the LBO pin should be set HIGH ifthe cable is shorter than 225 feet and set LOW forlonger cable lengths. For E3 application, LBO pinshould be set LOW regardless of cable length.The OPT1 pin is set HIGH for normal OS-3 operation.Setting the OPT1 pin to LOW increases the transmitterpower. The OPT1 pin should be set LOW for E3applications.The OPT2 pin should be set HIGH for normal operation.Setting the OPT2 pin to LOW disables the transmitterdrivers and reduces the power consumption of thecircuit by approximately 125 mW.I6-37

E3 Suggested Input circuitLtJo~.'nt:75 O.47~H IOUN+RTR"= , •• :"'.OS-3 Input circuitDLlN+RTR[[1010 LlN- I RFO1:1Note: Only one of the two input circuits is needed(J)~RVccDb>- .+5Vb>- en~ I I I1:2RLF2OPT2Note: NC pins should be tied to the ground pinindicated by the trailing letter.FIGURE 1: Functional Diagram

SSI78P7200E3/0S-3 Line Interfacewith Receive EqualizerPIN DESCRIPTIONRECEIVERNAMETYPEDESCRIPTIONLlN+, LlN-IRPOS 0RNEG 0RCLK 0LOWSIG 0Differential inputs, transformer-coupled from line.Unipolar receiver output, active as result of positive pulse at inputs.Unipolar receiver output, active as result of negative pulse at inputs.Clock pulses recovered from line data.Low Signal logic output indicating that input signal is less than thresholdvalue.TRANSMITTERTPOSTNEGTCLKLOUT+ 0LOUT- 0LBOOPT1OPT2IIIIIIEXTERNAL COMPONENT CONNECTIONUnipolar transmitter data input, active high.Unipolar transmitter data input, active high.Transmitter clock input, active high.Output to transformer for positive data pulses.Output to transformer for negative data pulses.Transmitter line buildoutcontrol. Set low for E3 or OS-3 cable of 225' or longer.Transmit option 1. Selects faster output pulse transition time and higheramplitude when low. Set high for normal DS-3 and set low for E3.Transmit option 2. Disables output driver and reduces output bias currentwhen 10w.Set high for normal transmit operation.RFO I Resistor connected to RGND to provide basic center frequency of receiverphase locked loop oscillator.LF1, LF2 - Resistor-capacitor loop filter network to establish bandwidth of phase lockedloop.CPO - Capacitor to RVcc that is connected to peak detector node to reduce signaldependentripple on that node.IPOWERTVcc - 5V power supply for transmit circuits.RVcc5V power supply for receive circuits.DVcc - 5V power supply for receive logic circuits.TGND - Ground return for transmit circuits.RGND - Ground return for receive circuits.DGND - Ground return for receive logic circuits.NCR - No connect, Tie to Receiver Ground (RGND).NCT - No connect, Tie to Transmitter Ground (TGND).NCO - No connect, Tie to Digital Ground.6-39

SSI78P7200E3/DS·3 Line Interfacewith Receive EqualizerELECTRICAL SPECIFICATIONS(TA = -40°C to 85°C, Vcc = 5V ±5%, unless otherwise noted.) Currents flowing into the chip are positive.Current maximums are currents with the largest absolute value. Operation above absolute maximumratings may permanently damage the device.ABSOLUTE MAXIMUM RATINGSPARAMETERPositive 5V supply: TVcc, RVcc, DVccRATINGStorage Temperature -65 to 150°CSoldering Temperature (10 sec.) 260°CAmbient Operating Temperature, TA6V-40 to +85°CPin Ratings: LOUT +, LOUT- Vcc -2 to Vcc +2VLlN+, LlN-, TPOS, TNEG, TCLK,LBO, RFO, LF2, LF1,OPT1, OPT2 PinsRPOS, RNEG, RCLK, LOWSIG PinsSUPPLY CURRENTS AND POWER-0.3 to Vcc +0.3V-0.3 to Vcc +0.3Vor +12 mAPARAMETER CONDITIONS MIN NOM MAX UNITSupply Current ICC Outputs Unloaded, 150 182 mAnormal operation,transmit and receiveall 1's patternPower Dissipation P Outputs unloaded,TA= 85°C 0.93 WEXTERNAL COMPONENTS (Common to DS3/E3, Nominal value.)Loop filter resistor RLF1 1 % tolerance 6.04 knLoop filter resistor RLF2 1% 100 knLoop filter capacitor CLF1 5% 0.22 IlFPeak detector capacitor CPO 10% 0.022 IlFEXTERNAL COMPONENTS (Dependent on speed, Nominal Value.) DS-3 E3Loop center frequency resistor RFO 1 % tolerance 5.23 6.81 kOTransmit termination capacitor CTT 5% 10 3 pFTransmit termination resistor RTT 1% 301 604 nReceive termination resistor RTR 1% 75 422 nReceive Transformer T1 3% 1 :1 1 :2Turns Ratio6-40

SSI78P7200E3/0S-3 Line Interfacewith Receive EqualizerDIGITAL INPUTS AND OUTPUTS(CMOS-compatible pins: LOWSIG, RPOS, RNEG, RCLK, TPOS, TNEG, TCLK, LBO, OPT1.) Currentsflowing into the chip are positive. Current maximums are currents with the largest absolute value.PARAMETER CONDITIONS MIN NOM MAX UNITInput low voltage VIL -0.3 1.5 VInput high voltage VIH 3.5 Vee +0.3 VInput low current ilL VIL = 1.5V -5 5 ~Input high current IIH VIH = 3.5V -5 5 ~Output low voltage VOL IOL = 0.1 mA 0.4 VOutput high voltage VOH IOH = -0.1 rnA 4 VOPT2 CHARACTERISTICSInput low voltage VIL ilL = 0.4 rnAInput high voltageVIHRECEIVERAll of the measurements for the receiver are made with the following conditions unless otherwise stated:1. The input signal is transformer coupled as shown in Figure 1.2. RFO = 5.23 kg for OS-3 and 6.81 kg for E3.3. UI (Unit Interval) defined as 22.35 ns for OS-3 and 29.1 ns for E3.Input signal voltage VIN Input AC-CoupledCPO = 0.0221lF ±0.045 ±1.2 VCPO not used ±0.090 ±1.2 VInput Resistance RIN Input at device's common 15 20 30 kgmode voltageReceive data detection VOTH Relative to peak 50 0/0thresholdamplitude for 22.37/17.18 MHzsinusoidal inputReceive data low signal VLOW Relative to peak ±20 ±80 mVthresholdamplitude for 22.37/17.18 MHzsinusoidal inputReceive data low signal TLOW Relative to peakdelayamplitude for 22.37/17.18 MHzsinusoidal inputCPO = 0.0221lF 500 IlSCPO not used 0.5 3 IlSVIN(max) = ±250 mVReceive clock period TRCF OS-3 22.35 nsE3 29.1 nsReceive clock pulse width TRC OS-3 12.24 nsE3 14.55 nsI6-41

SSI78P7200E3/0S-3 Line Interfacewith Receive EqualizerRECEIVER (continued)PARAMETERCONDITIONSReceive clock positive TRCPT CL = 15 pFtransition timeReceive clock negative TRCNTtransition timePositive or negativeTRDPReceive data pulse width TRDNReceive data set-up timeTRDPSTRDNSReceive data hold time TRDPHTRDNHReceive input jitter tolerancehigh frequency (Note 3)Receive input jitter tolerancelow frequency (Note 3)CL = 15 pF60 - 300 kHzVIN (min) = ±45 mV10 - 800 kHzVIN (min) = ±45 mV10 - 800 kHzVIN (min) = ±90 mV10 Hz to 2.3 kHz100 Hz to 10 kHzClock Recovery Phase KD All 1's data patternDetector GainClock Recovery PhaseLocked Oscillator GainKOKD = 0.418/RFODS-3E3DS-3E3DS-3E3DS-3E3E3DS-3E3DS-3E3MIN NOM MAX UNIT4.5 6 ns4.5 6 ns22.35 ns29.15 11.18 13.7 ns5 14.555 11.18 13.7 ns5 14.550.3 UIPP0.15 UIPP0.20 UIPP10 UIPP10 UIPP72 80 88 ~Rad6212 14.5 17 Mrad/sec. -VoltTRANSMITTERAll of the measurements for the transmitter are made with the following conditions unless otherwise stated:1. Transmit pulse characteristics are obtained using a line transformer which has the characteristics,similar to pulse engineering PE-65969, Mini circuit T4-1, Valor PT5045.2. The circuit is connected as in Figure 1.Transmit clock repetition TICF DS-3 22.35 nsE3 29.1Transmit clock pulse width TIC DS-3 11.18 nsE3 14.55Transmit clock negative TICNT 4.5 6 nstransition timeTransmn clock positive TICPT 4.5 6 nstransition timeTransmit data set-up timeTIPDS DS-3 3.5 11.18 nsTINDS E3 3.5 14.556-42

SSI78P7200E3/DS-3 Line Interfacewith Receive EqualizerTRANSMITTER (continued)PARAMETER CONDITIONS MIN NOMTransmit data hold time TTPOH OS-3 3.5 11.18TTNOH E3 3.5 14.55Transmit positive line TTPL Measured at OS-3 10.62 11.18pulse widthtransformer,LBO = Low E3 14.5Transmit negative line TTNL Measured at DS-3 10.62 11.18pulse widthtransformer,Transmit line pulsewaveshapeLBO = Low E3 14.5See Note 1 for OS-3See Note 2 for E3Note1:Characteristics are in accordance with ANSI T1.102 - 1987, Table 5 and Figure 8.Note 2:Characteristics are in accordance with CCITT G.703 - 1988 Figure 17.MAX UNITns12 ns12 nsnsRECEIVEUNEINPUT (REF)----'TRCFRECCLOCKREC POS ooT ___ --./________________{+TRDNS++TRDNH+)C. _________REC NEG OUT .-+---TRDN----,IFIGURE 2: Receive WaveformsTRANSMITCLOCK INTRANSMITPOSINTRANSMITNEG IN____.../_________________ ~fTTNDS-_O_5~_P_=....JjI_TTPLiTRANSMITLINE OUTPUT_______~_L----------O.5-V-N=t~ ftTTNDH_}~ _________VN'------'-I_TTNL_IFIGURE 3: Transmit Waveforms6-43

SSI78P7200E3/DS-3 Line Interfacewith Receive EqualizerPACKAGE PIN DESIGNATIONS(Top View)•LlN+CPONCRLOWSIGLlN-OVCCNCRRPOSRFO RNEGRGNORCLKRVecDGNOTGNONCOCAUTION: Use handling procedures necessaryfor a static sensitive component.I!

Section 7LAN PRODUCTSI7

7-0

551 78Q902Ethernet Twisted-Pair MediaAttachment UnitDESCRIPTIONThe 551 78Q902 twisted-pair Media Attachment Unit(TP-MAU) is designed to allow Ethernet connections touse the existing twisted-pair wiring plant through anEthernet Attachment Unit Interface (AUI). The 551780902 provides the electrical interface between theAUI and the twisted-pair wire.551 780902 functions include level-shifted data passthroughfrom one transmission media to another, collisiondetection, Signal Quality Error (SOE) testing andautomatic correction of polarity reversal on the twistedpair input. It also includes LED drivers for transmit,receive, jabber, collision, reversed polarity detect andlink functions.The 551780902 is an advanced CMOS device andrequires only a single 5-volt power supply.APPLICATIONS• Computer/workstation interface boards• LAN repeater• External 1 OBase-T converterFEATURES••••••••December 1992Meets or exceeds IEEE 802.3 standards for AUIand 10Base-T interfaceDirect interface to AUI and RJ45 connectorsAutomatic AUIIRJ45 selectionInternal predistortion generationInternal common mode voltage generationJabber functionSelectable link test, SeE test disableTwisted-pair receive polarity reverse detectionand selectable polarity correction• LED driver for transmit, receive, jabber,collision, link and reversed polarity Indicatorsor for flashing status Indicator• Single +5V supply, CMOS technology• Available in 28-pin DIP or PLCCBLOCK DIAGRAMPIN DIAGRAMDODO PNDIPDINl IMDMD 'v1CIPCINSQEClK IClKO-J AUITXMIT IPULSE.. RECEIVER I;;; SHAPING1 1IWATCHDOG I POLARITY E::-I LOOPBACKI ~ TIMER DETECT1 J 4I AUI RCVR L -- TP -DRIVER -- RECEIVER --LINKINTEGRITY SQUELCH l:=-MODE II SELECTI COLLISION ~ COLLISIONDRIVER IDETECTORLEDDRIVEROSC~SQETEST..~....TPOPTPONPRCTPIPTPINlEDP/SlEDJlEDTlEDRlEDClEDlDONDOPlEDJlEDlPRCClKOClKIGND1CINCIPMDODINDIPLI28-Pin DIPLEDClEDRlEDTlEDP/STPOPGND2VCC2TPONVCC1RBIASMD1SQETPIPTPINI1292 - rev. 7-1CAUTION:Use handling procedures necessaryfor a static sensitive component.

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitFUNCTIONAL DESCRIPTIONThe 551 780902 Media Attachment Unit (MAU) interfacesthe Attachment Unit Interface (AUI) to theunshielded twisted pair cables, transferring data inboth directions between the two. The AUI side of theinterface comprises three circuits: Oata Output (00),Oata Input (01) and Collision Interface (CI). The twistedpair network side of the interface comprises two circuits:Twisted Pair Input (TPI) and Twisted Pair Output(TPO). In addition to the five basic circuits, the 551780902 contains an internal crystal oscillator, separatepower and ground pins for analog and digitalcircuits, various logic controls and six LEO drivers forstatus indications.Functions are defined from the AUI side of the interface.The 551780902 Transmit function refers to datatransmitted by the Oata Terminal Equipment (OTE)through the AUI and MAU to the twisted pair network.The 551 780902 Receive function refers to data receivedby the OTE through the MAU and AUI from thetwisted pair network. In addition to basic transmit andreceive functions, the 551 780902 performs all requiredMAU functions defined by the IEEE 802.31 OBase-T specification such as collision detection, linkintegrity testing, 5ignal Ouality Error (50E), jabbercontrol and loopback.TRAN5MIT FUNCTIONThe 551 780902 transfers Manchester encoded datafrom the AUI port of the OTE (the 00 circuit) to thetwisted pair network (the TPO circuit). The outputsignal on TPON and TPOP is pre-distorted to meet the10 Base-T jitter template, and filtered to meet FCCrequirements. The output waveform (after the transmitfilter) is shown in Figure 1 . If the differential inputs at the00 circuit fall below 75% of the threshold level for 8 bittimes (typical), the 551 780902 transmit function willenter the idle state. Ouring idle periods, the 551780902 transmits link integrity test pulses on the TPOcircuit.RECEIVE FUNCTIONThe 551 780902 receive function transfers serial datafrom the twisted pair network (the TPI circuit) to theOTE (overthe 01 circuit of the AUI). An internal squelchfunction discriminates noise from link test pulses andvalid data streams. Only valid data streams activate thereceive function. If the differential inputs at the TPIcircuit fall below 75% of the threshold level(unsquelched) for 8 bit times (typical), the 551780902receive function will enter the idle state. The TPIthreshold can be reduced by approximately 3 dB toallow for longer loops in low-noise environments. Thereduced threshold is selected when M01 = 0 andMOO = 1.DIFFERENTIAL INPUT MODEIn the differential input mode, the transmit interfaceconsists of TXP and TXN, PE, POC, and the TransmitEnable input (TEN). Transmission starts when PE ishigh and TEN is low, and ends when either PE or TENgoes inactive. Predistortion control is provided by thePOC input.POLARITY REVERSE FUNCTIONThe 551 780902 polarity reverse function uses bothlink pulses and end-of-frame data to determine polarityof the received signal. A reversed polarity condition isdetected when eight opposite receive link pulses aredetected without receipt of a link pulse with the expectedpolarity. Reversed polarity is also detected iffour frames are received with a reversed start-of-idle.Whenever polarity is reversed, these two counters arereset to zero. If the 551780902 enters the link fail stateand no data or link pulses are received within 96 to128 ms, the polarity is reset to the default non-flippedcondition. (If Link Integrity is disabled, polarity detectionis based only on received data pulses.)~ n [\ nV U V UFIGURE 1: 78Q902 TPO Output Waveform7-2

551 78Q902Ethernet Twisted-Pair MediaAttachment UnitCOLLISION DETECTION FUNCTIONThe collision detection function operates on the twistedpair side of the interface. A collision is defined as thesimultaneous presence of valid signals on both the TPIcircuit and the TPO circuit. The SSI 780902 reportscollisions to the AUI by sending a 10 MHz signal overthe CI circuit. The collision report signal is output nomore than 9 bit times (BT) after the chip detects acollision. If the TPI circuit becomes active while there isactivity on the TPO circuit, the TPI data is passed to theOTE overthe 01 circuit, disabling the loopback. Figure2 is a state diagram of the SSI 780902 collisiondetection function (referto IEEE 802.31 OBase-T specification).LOOPBACK FUNCTIONThe SSI 780902 loopback function operates in conjunctionwith the transmit function. Data transmitted bythe OTE is internally looped backwithinthe SSI780902fromthe OOpinstothe 01 pins and returnedtothe OTE.The loopback function is disabled when a data collisionoccurs, clearing the 01 circuitforthe TPI data. Loopbackis also disabled during link fail and jabber states.SQE TEST FUNCTIONFigure 3 is a state diagram of the SOE Test function.The SOE test function is enabled when the SOE pin istied high. When enabled, the SOE test sequence istransmitted to the controller after every successfultransmission on the10Base-T network. When a successfultransmission is completed, the SSI 780902transmits the SOE signal to the AUI over the CI circuitfor 1 0 BT ± 5 BT. The SOE function can be disabled forhub applications by tying the SOE pin to ground.JABBER CONTROL FUNCTIONFigure 4 is a state diagram of the SSI 780902 Jabbercontrol function. The SSI 780902 on-chip watchdogtimer prevents the OTE from locking into a continoustransmit mode. When a transmission exceeds the timelimit, the Watchdog timer disables the transmit andloopback functions, and sends the SOE signal to theOTE over the CI circuit. Once the SSI 780902 is in thejabber state, the DO circuit must remain idle for a periodof 491 to 525 ms before it will exit the jabber state.DO = Active·TPI = Idle·XMIT = EnabledIDLETPI = ActiveIOUTPUTTPO = DODI= DODO = Idle +XMIT = DisabledDO= Active·TPI = Active·XMIT = Enabled r--------,DO = Active·TPI = Active·XMIT = EnabledL.....-___ ---I~ COLLISION ~------'INPUTDI = TPITPI = IdleDO = Active·TPI = IdleDO = IdleFIGURE 2: Collision Detection Function7-3

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitLINK INTEGRITY TEST FUNCTIONFigure 5 is a state diagram of the SSI 780902 linkIntegrity Test Function. The link Integrity Test is usedto determine the status of the receive side twisted paircable. The link integrity test is enabled when the LI pinis tied high. When enabled, the receiver recognizes linkintegrity pulses which are transmitted in the absence ofreceive traffic. If no serial data stream or link integritypulses are detected within 50 - 150 ms, the chip entersa link fail state and disables the transmit and loopbackfunctions. The SSI 780902 ignores any link integritypulse with intervals less than 2 - 7 ms. The SSI 780902will remain in the link fail state until it detects either aserial data packet or two or more link integrity pulses.1Power On,-OUTPUT IDLETEST MODEThe SSI 780902 Test mode is selected when a 2 to2.5 MHz clock is input on the MOO mode select pin.Test mode sets the internal counter chains to run at1024 times their normal speed. The maximum transmittime, unjab time, link Integrity timing and LED timingare reduced by a factor of 1024. During test operation,10 MHzand20 MHz signals areoutputonthe PRC andSOE pins, respectively. When Test mode is selected,the SOE function cannot be disabled. I n Test mode thePRC function can be disabled by the LI pin. Jabbercanbe disabled by setting MD1 = O.,P ower 0 n•NO OUTPUT+ DO = ActiveOUTPUT DETECTEDt 00= IdleSOE WAIT TESTStart_SOE_Test_Waie Timer.. I t SOE Test W ait_Timer_Done·XMIT = Disable XMIT= Enabl eSOE TESTStart_SOE_ Tese TimerCI = SOESOE_ Test_ Timer_Done J, DO = ActiveNONJABBER OUTPUTStarcXMIT _Max_Timer.. DO = Idlel, DO = Active'XMIT _Max_ Timer_D one-JAB ~XMIT = DisableLPBK = DisableCI = SQE.. 00= IdleUNJAB WAITStart_Unjab_ TimerXMIT = DisableLPBK = DisableCI = SQEIUnjab Timer DoneIDO = Active'Unjab_ Timer_NoCDoneFIGURE 3: SaE Test FunctionFIGURE 4: Jabber Control Function7-4

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitPower OniIDLE TESTStart_Link_Loss_ TimerStart_Lin~ Test_Min_ Timer TPI = Active +(Link_Test_Rcvd = True* Link_Test_Min_Timer_Done)Link_Loss_ Timer_Done I 1-. ___________---'• TPI = Idle• Link_TesCRcvd = False,LINK TEST FAIL RESETTPI = ActiveLink_Count = 0XMIT = DisableRCVR = DisableLPBK = DisableLink_ Test_Rcvd = False• TPI = IdleLINK TEST FAIL WAITXMIT = DisableRCVR = DisableLPBK = DisableLink_Count = Link_Count + 1TPI = Active ILink_ Test_Rcvd = Idle* TPI = IdleLINK TEST FAIL, , ,LINK TEST FAIL EXTENDStart_Link_ Test_Min_ TimerStart_Link_ TesCMax_ TimerXMIT = DisableRCVR = DisableLPBK = DisableTPI = Active+ Link_Count = LC_Max JLink_ Test_Min_ Timer_Done* Link_ Test_Rcvd = TrueIXMIT = DisableRCVR = DisableLPBK = DisableL..-_________ ....I1 TPI = Idle'DO = Idle(TPI = Idle * Link_ Test_Max_ Timer_Done) +(Link_ Test_Min_ Timer_Not_Done* Link_TesCRcvd = True)FIGURE 5: Link Integrity Test Function7-5

551 78Q902Ethernet Twisted-Pair MediaAttachment UnitTABLE 1: Mode Select OptionsMD1 MOO MODE0 0 Base-T compliant MAU0 1 Reduced squelch level1 0 Half current AUI driver1 1 DO, DI & CI ports disabled1 Clock Test mode, jabber on0 Clock Test mode, jabber disabledPIN DESCRIPTIONNAME TYPE DESCRIPTIONDON/DOP I Data Out Negative/Data Out Positive: Differential input pair connected to theAUI transceiver DO circuitLEDJ I/O Jabber LED Driver: Open drain driver for the Jabber indicator LED. Outputgoes active 1 when watchdog timer begins jab, and stays active until end of theunjab wait period (491 - 525 ms). When tied to ground, causes LEDP/S to actas a multi-function blinking status indicator.LEDL 0 Link LED Driver: Open drain driver for the Link indicator LED. Output is activeexcept during Link Failor when Link Integrity Test is disabled.----PRC I/O Polarity Reverse Correction: The SSI780902 automatically corrects reversedpolarity at TPI when PRC is tied high. In Test mode, this pin is a 10 MHz output.CLKO/CLKI - Crystal Oscillator: The SSI 780902 requires either a 20 MHz crystal (orceramic resonator) connected across these pins, or a 20 MHz clock applied atCLKI.--_..__..GND1 - Ground #1.CIN/CIP 0 Collision Negative/Collision Positive: Differential driver output pair tied to thecollision presence pair of the Ethernet transceiver AUI cable. The collisionpresence signal is a 10 MHz square wave. This output is activated when acollision is detected on the network, during self-test by the SOE sequence, orafter the watchdog timer has expired to indicate the transmit wire pair has beendisabled.MDO I Mode Select 0: Selects operating modes in conjunction with MD1. See Table1 above for mode select options.DIN/DIP 0 Data In Negative/Data In Positive: Differential driver pair connected to the AUItransceiver DI circuit.1 LED drivers pull low when active.7-6

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitPIN DESCRIPTION (continued)NAME TYPE DESCRIPTIONLI I Link Integrity Test Enable: Link integrity testing is enabled when this pin is tiedhigh. With link test enabled, the SSI 780902 sends the link integrity signal inthe absence of transmit traffic. It also recognizes received link test pulses,indicating the receive wire pair is present in the absence of transmit traffic.TPIN/TPIP I Twisted Pair Receive Inputs: Differential receive inputs from the twisted pairinput filter.SOE I/O Signal Ouality Error Test Enable: SOE is enabled when this pin is tie high.When enabled, the SSI 780902 sends the signal quality error test sequenceto the CI of the AUI cable after every successful transmission to the media. InTest mode, SOE becomes a 20 MHz output.MD1 I Mode Select 1: Selects operating modes in conjunction with MOO, (see Table1). MD1 clock input between 2.0 and 2'.5 MHz enables Test mode.RBIAS - Resistor Bias Control: Bias control pin for the operating circuit. Bias set fromexternal resistor to ground. External resistor value = 12.4 kn (±1 %).VCC1 I Power Supply 1: +5V power supply.TPONITPOP 0 Twisted Pair Transmit Outputs: Transmit drivers to the twisted-pair output filter.The output is Manchester encoded and pre-distorted to meet the 1 OBase-Ttemplate.--VCC2 I Power Supply 2: +5V power supply.GND2 - Ground #2.LEDP/S 0 Polarity/Status LED Driver: Open drain LED driver. In normal mode,LEDP/S is active when reversed polarity is detected. If LEDJ is tied to ground,the output LEDP/S indicates multiple status conditions as shown in Figure 6.On solid = Normal, 1 Blink = Link Down, 2 Blinks = Jabber, 5 Blinks = PolarityReversedLEDT 0 Transmit LED Driver: Open drain driverforthe Transmit indicator LED. Outputis active during transmit.LEDR 0 Receive LED Driver: Open drain driver for the Receive indicator LED. Outputis active during receive.LEDC 0 Collision LED Driver: Open drain driverforthe Collision indicator LED. Outputis active when a collision occurs.I7-7

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may damage the device.PARAMETERRATINGSupply Voltage, Vcc-0.3 to 6Operating Temperature, Topa to +70Storage Temperature, TST -65 to +150UNITV-----------~°C°CRECOMMENDED OPERATING CONDITIONSPARAMETER CONDITIONS MINSupply Voltage 1 , Vcc 4.75Operating Temperature, Top1Maximum voltage differential between VCC1 and VCC2 must not exceed O.3V.aNOM MAX UNIT5.0 5.25 V- 70 °CSWITCHING CHARACTERISTICS (Ta = a to 70°C, Vcc = 5V ±5%)PARAMETER CONDITIONS MINJabber TimingMaximum transmit time 2 98.5Unjab time 2 491Time from Jabber toCSO on CIP/CIN 3Link Integrity TimingTime link loss 2 65Time between Link 9Integrity Pulses 2Interval for valid receive 4.1Link Integrity Pulses 2COllision TimingSimultaneous TPIITPO to CSOstate on CIN/CIP00 loopback to TPI on 01 3 300CSO state delay after TPIIOO idle 3 -CSO high pulse width 40CSO low pulse width 40CSO frequency -aaNOM1 MAX UNIT131--_...ms- 525 ms- 900 ns_.._-- ------------- 66 ms~-.--t-- 11 ms- - ---- 65 ms------~~-'----.-------- 900 ns-----900 ns- 900 ns-------- 60 ns---- _._._--60----ns10 - MHz1 Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to productiontesting.2 Switcl:ling times reduced by a factor of 1024 during Test mode.3 Parameter is guaranteed by design; not subject to production testing.7-8

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitSWITCHING CHARACTERISTICS (Ta = 0 to 70°C, Vcc = SV ±S%) (continued)PARAMETER CONDITIONS MIN NOM1 MAX UNITSQE TimingSOE signal duration SOO - 1S00 nsDelay after last positive transition 0.6 - 1.6 ~sof DO------LED TimingLEDC, LEDT, LEDR on time 2 100 - - msLEDP/S on time 2 (See Figure 6) - 164 - msLEDP/S period 2 (See Figure 6) - 328 - ms--GeneralReceive start-up delay 0 - 500 nsTransmit start-up delay 0 - 200 nsLoopback start-up delay 0 - SOO ns1 Typical figures are at 2S °C and are for design aid only; not guaranteed and not subject to productiontesting.2 Switching times reduced by a factor of 1024 during Test mode.1/0 ELECTRICAL CHARACTERISTICS (Ta = 0 to 70°C, Vcc = SV ±S%)PARAMETER CONDITIONS MIN NOM1 MAX UNITInput low voltage 2 VIL - - 0.8 VInput high voltage 2 VIH 2.0 - - VOutput low voltage VOL RLOAD = 2 kQ - - 0.13 V(Open drain LED DriverJ)Supply current Icc Line Idle - 60 69.3 rnA(Vcc1 = Vcc2 = S.2SV) Line Active, - 125 140 rnAtransmitting all ones-- --Input leakage current 4 ILL Input between VCC and GND - ±1 ±10 ~ITristate leakage ITS Output between VCC - ±1 ±10 ~currentandGND1 Typical figures are at 2SoC and are for desing aid only; not guaranteed and not subject to productiontesting.2 MOO, MD1, SOE, PRC and LI pins. MD1 clock (test mode) must be CMOS level input.3 LED Drivers can sink up to 10 rnA of drive current.4 Not including TPIN, TPIP, DOP or DON.7-9

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitLink FailJabberPolarityReverse1.9685NOTE: LEDP/S status indications are shown in order of priority, i.e., Link Fail indicationsupersedes Jabber indication which supersedes Polarity Reverse (when PRC = 1). Reversedpolarity conditions supersede Link Fail conditions when PRC = 0 (Polarity CorrectionDisabled). At the LEDL indicator, reversed polarity condition reported as Link Fail whenPRC = O. This allows the user to distinguish between actual link failure and apparent linkfailure due to polarity reversal.FIGURE 6: LEDP/S Status Indication TimingAUI ELECTRICAL CHARACTERISTICS (Ta = 0 to 70°C, Vcc = SV ±S%)PARAMETER CONDITIONS MIN NOM1 MAXInput low current IlL - - -700Input high current IIH - ---SOO-1--Differential output voltage VOD ±SSO - ±1200Differential squelch VDS - 220mVthresholdReceive input impedance Rz Between DOP and DON - 20 - kn1 Typical figures are at 2SoC and are for design aid only; not guaranteed and not subject to productiontesting.UNITf1Af1AmA7-10

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitTRANSMIT CHARACTERISTICS (Ta = 0 to 70°C, Vee = 5V ±5%)PARAMETER CONDITIONS MIN NOM1 MAX UNITTransmit output impedance ZOUT - 5 - QPeak differential output Voo load = 2000 at TPOP ±4.5 - ±5.2 Vvoltageand TPONTransmit timing jitter addition 2 After Tx filter, 0 line length - - ±8 nsTransmit timing jitter addition 2 After Tx filter, line model as - - ±3.5 nsshown in IEEE 802.3standard for 1 OBase-TRECEIVE CHARACTERISTICS (Ta = 0 to 70°C, Vcc= 5V ±5%)Receive input impedance ZIN Between TPIP/TPIN - 20 - kQDifferential squelch Vos - 420 - mVthresholdReduced squelch VOSR - 300 - mVthresholdReceive timing jitte~ - - 1.5 ns1 Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to productiontesting.2 Parameter is guaranteed by design; not subject to production testing.APPLICATION INFORMATIONEXTERNAL MAUFigure 7 shows the 551 780902 in a typical externalMAU application, interfacing between an AUI and theRJ45 connectors of the twisted pair network. A 20 MHzcrystal (or ceramic resonator) connected across ClKIand ClKO provides the required clock signal. Transmitand receive filters are required in the TPO and TPIcircuits. Details of the transmit and receive filters areshown in Figures 8 and 9, respectively. (Differentialfilters are also recommended.)INTERNAL MAUFigure 10 shows an internal MAU application whichtakes advantage of the 551 780902's unique AUII10Base-T switching feature to select either the D­connector (AUI) or the RJ45 connector (10Base-T).No termination resistors are used on the 551 780902side of the AUI interface to prevent impedance mismatchwith the drop cable. The half current drive modeis used to maintain the same voltage levels in theabsence oftermination resistors. This application usescapacitive coupling instead of transformer coupling.MD1 is tied high so MDO functions as the mode controlswitch.When MDO is low, the half current drive mode isselected. When MDO is high, the 551 780902 iseffectively removed from the circuit. The 902 AUI ports(DO, DI and CI) are disabled isolating the 551 780902from the AUI. The 551 780902 DI and CI ports go toa high impedance state and the DO port is ignored.To implement an auto-select function, lEDl can betied to MDO. This activates the 902/AUI interface whenthe TP link is active (data or link integrity pulses) anddisables it when the link is inactive.I7-11

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitAUI~C178n.CLKIDOPDONCLKO~C2TPOPTPONTPIPTo/FromDIPData 78n. NTerminal TPIN0Equipment DIN 0)"LEDJCIP CO LEDC78n. I'-CIN LEDTLEDRLEDL+5~ VCC1 LEDP/SVCC2RBIASPRCMOOSQEMD1LIGND1GND212.4 kn±l%0.1 F1.0 FTantalum: RJ45Twisted PairTo/FromNetworkill Typically, resistors on the AUI side of the transformer are already present in the terminal.If termination resistors are present in the terminal, the shaded resistors are not required ...&. A 20 MHz (±1 %) crystal or ceramic resonator may be used at CLKI/CLKO.£ Suitable integrated filter/transformers include TDK Corporation HIM 3000, Pulse EngineeringPE65421, FilMag 78Z1120B and Valor PT3877.FIGURE 7: SSI 78Q902 External MAU Application Diagram7-12

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitT I I TTTFIGURE 8: Transmit Filter DiagramFIGURE 9: Receive Filter DiagramD-ConnectorTo/FromController20 MHzENCODER!D t-:L- C1 C2 -DECODERCLKI80238391 DOP7991ActivateMAU&IIIIDONDIPNCLKOTPOPTPONTPIPTPINDIN0mLEDJ0CIP COLEDCCINPRCVCC1VCC2LISQEMD1MOO.......LEDTLEDRLEDLLEDPRBIASGND1GND21 f!FTantalum0.1 f!FI 12.4kO±1%!... ______________ J& Connect LEDL to MDO to implement auto-select feature.Twisted PairRJ45 To/FromNetworkIFIGURE 10: SSI78Q9021nternai MAU Application Diagram7-13

SSI78Q902Ethernet Twisted-Pair MediaAttachment UnitPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.DONDOPlEDJlEDlPRCClKOClKIlEDClEDRlEDTlEDP/STPOPGND2VCC2LEDlPRCClKO""")0w....J4~()a.. z a:: I- a..0 0 0 00 0 w w w W0 0 ....J ....J ....J ....J3 2 28 27 2625 TPOP24 GND223 VCC2GND1TPONClKI22 TPONCINVCC1GND121 VCC1CIPMDODINDIPLIRBIASMD1SQETPIPTPINCINCIP1200::!13 14 15 16 17 18z a.. ::J z a.. w0 0 a: a: al- I- (f)20 RBIAS19 MD128-Pin DIP28-Pin PLCCORDERING INFORMATIONPART DESCRIPTION881780902 28-Pin DIP881 780902 28-Pin PLCCORDER NO.780902-CP780902-CHPKG.MARK780902-CP780902-CHNo r~sponsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or otherrights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems.Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned toverify that the data sheet is current before placing orders.Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914©1991 Silicon Systems, Inc. 7-14 1292 - rev.

5S178Q83733V, 5V PCMCIAEthernet ComboDESCRIPTIONThe SSI7808373 is a highly integrated Ethernet IC foruse in PCMCIA (Personal Computer Memory CardInternational Association) applications and canoperate with a power supply of 3.3V or 5V. It containsa Media Access Controller (MAC), a 10 MbitlsManchester encoder/decoder (ENDEC), a 10Base-Ttransceiver, a memory-card bus interface (PCMCIA),and an Attachment Unit Interface (AUI). This level ofintegration allows the user to implement a PCMCIAcard for 10Base-T using only the SSI 7808373,external memory, and some passive components. Theinternal bus interface circuit allows connection to aPCMCIA 2.1 bus without other external components.The PCMCIA bus-decoding logic can be bypassed forconnection to other bus types. The SSI 7808373connects to twisted-pair media via line transformersthrough the on-chip transceiver circuit. Connection toother media such as coaxial cable is made through theAUI port to an external transceiver, such as the SSI7808330 Ethernet Coax Transceiver.The SSI 7808373 has a sophisticated powermanagement capability with three different operatingmodes allowing the user to maximize power savings,making it ideal for use in PCMCIA applications. Duringnormal operation, the IC monitors its own actions andshuts down the circuits that are not being used,resulting inthe lowest possible operating power. It alsohas a standby mode which leaves only the oscillatorrunning, and a full shutdown mode which also turns offthe oscillator.An intelligent Buffer Manager is controlled by the hostread, host write, receive and transmit pointers, and theSSI 7808373 manages the pointers internally withoutany host intervention. The device interleaves access tothe buffer memory so that accesses from the host andfrom the network media seem to operate concurrently.Big and little endian byte orderings make for simple businterface to all standard microprocessors.The SSI 7808373 is available in both a 1 OO-Iead OFPand thin OFP (TOFP) packages, and can operate witha power supply of 3.3 volts or 5 volts.FEATURESJanuary 1995Single-chip solution for 10Base-T/PCMCIAdesignsOperation at 3.3V or 5VPin-compatible with SSI 7808370Integrated 10Base-T transceiver:Programmable/automatic selection oftwisted pair (RJ45) or AUI portReceive polarity detection/correction ontwisted-pair inputsManchester Encoder/Decoder circuitAUI port for connection to 10Base2/Stransceiver or AUI cableIntegrated bus interface compliant withPCMCIA release 2.1 specificationBus interface can be bypassed for non­PCMCIA applicationsProtocol Controller compliant with IEEE 802.3and Ethernet 2.0Advanced Buffer Manager architecture:Automatic management of all pointersAllows "simultaneous" access to data inbuffer memory by both the network and hostHigh-speed received packet skipConfigurable Buffer Memory for designflexibility: 7Two-bank transmit buffer in 2, 4, 8, or 16Kbyte sizesRing-structure receive buffer from 4 to 62KbytesSoftware-configurable system bus structure:Compatible with major microprocessors8- or 16-bit wide data path communicationswith hostsPower management options:Intelligent power mode automaticallyshuts off unused circuitryStandby mode reduces power while not inoperationFull shutdown mode offers maximumpower savingsAvailable in 100-lead QFP and TOFP packages0195 - rev 7-15

SSI78Q83733V, 5V PCMCIAEthernet ComboFUNCTIONAL DESCRIPTIONThe 78Q8373 consists of six major blocks as shown inFigure 1.• Buffer Manager (and SRAM Interface)• Data Link Controller• HosVPCMCIA Interface• Manchester ENDEC• Twisted Pair Transceiver• Power ManagementBUFFER MANAGERThe Buffer Manager manages all accesses to thebuffer memory through the SRAM interface. The buffermemory is connected directly to the Data Link Controller(DLC), thus eliminating the need for a localmicroprocessor. The Buffer Manager also keeps trackof all buffer memory pOinters automatically, simplifyingthe software driver task. Together with intelligentarbitration, this makes the 8373 a high performanceLAN controller.The buffer memory is divided into two portions: transmitmemory portion and receive memory portion. Thetransmit memory portion can be partitioned into 2K, 4K,8K or 16 Kbyte buffer sizes. There is only one transmitbank if a 2 KB transmit buffer size is selected. If thetransmit buffer size is greater than 2 KB, then thetransmit buffer is configured into two banks of equalsize. With the two bank configuration, one transmitbank may be tied up during transmission but the hostcan still continue to load data packets into the secondtransmit bank to be transmitted later. The receivebuffer has a ring architecture which can be configuredfrom 4K to 62 KB depending on the buffer memoryconfiguration which has a range of 8K to 64 KB.A central arbitrator inside the Buffer Manager prioritizesand services requests for access to the buffer memoryfrom 4 sources: the Transmitter, the Receiver, HostRead and Host Write. If necessary, the 8373 will asserta 'not ready' handshake to the host while servicing theTransmitter andlor Receiver. The 8373 arbitrationmechanism provides packet management byinterleaving packet data accesses to the buffer memorysuch that the operations appear to be simultaneous.For instance, in the situation where 2 transmit banksare configured, the host can load the first transmit bankand initiate a transmission. Wh ile the first transmit bank7-16is being transmitted, the host can continue to loadpackets in the second transmit bank. At this stage, the8373 can potentially be receiving data from the mediu mand loading it into the receive buffer (if the 8373 is in aloop back mode or if self-reception occurs).DATA LINK CONTROLLERThe Data Link Controller (DLC) implements the ISOIANSI/IEEE 8802-3 CSMA/CD protocol. It consists of aTransmitter, a Receiverand CRC logic (which is sharedby both transmit and receive operations). Automaticgeneration and stripping of the 64-bit preamble and the32-bit CRC code are provided on-chip.HOST/PCMCIA INTERFACEThe Host Interface (HIF) provides connection to thehost system. It consists of the various registers, DMAcircuits and ready logic. Both word and byte interfacesare supported as well as big endian and little end iandata ordering. Host access to the buffer memory isthrough BMR8 (and BMR9).Reading from BMR8 willread a byte or word from the receive buffer and writingto BM R8 will write a byte or word to the transmit buffer.The ready logic is capable of delaying host access tothe buffer memory with a time-out mechanism. Bothsingle and burst DMA transfer modes are supported.The PCMCIA interface circuitry builds on top of the8373 generic host interface and is only active if theMODE pin is left unconnected (internally pulled-up).The 8373 can thus connect directly to a PCMCIArelease 2.1 compliant bus. It also supports decoding forthe external CIS memory (both ROM and Flash types).The 8373 pinout has been defined to minimize crisscros~ingconnections to the PCMCIA connector. Thisallows for a cost effective 2-layer PCB design.MANCHESTER ENDECThis block implements Manchester encoding anddecoding. Serial NRZ data from the DLC is convertedto Manchester encoded data and sent to either thetwisted-pair transceiver block or to the Attachment UnitInterface (AUI) driver, depending on which block isactive. The decoder section performs three functions:clock recovery, carrier detection and Manchesterdecoding. The recovered receive clock will be low atthe end of reception and during idle to save power.Jitter of up to ±18 ns can be tolerated by the decoder.This block also translates a 10 MHz collision signal toa logic-level Signal before sending it to the DLC blockif the AUI port is selected.

551 78Q83733V, 5V PCMCIAEthernet ComboTWISTED PAIR TRANSCEIVERThe on-chip Twisted Pair module consists of a numberoffunctions.lt has a smart squelch circuitry to determinevalid data present on the differential receive inputsTPIP/TPIN. Its transmit and pre-distortion driversconnect to the twisted pair network via the summingresistors and transformer/filter. The link detector/generator circuitry checks the integrity of the cableconnecting the two twisted pair MAUs. Collision, jabberand SQE are also incorporated.POWER MANAGEMENTOne very useful and important feature that the 8373offers is intelligent power management. It supportsthree different power saving modes: Intelligent, Standby,and Full Shutdown. All modes are configurable throughregisters. In the Intelligent mode, clocks are active onlywhen they are needed. For example, when nottransmitting, the clock supplied to the transmitter circuitin the OLC block is not active while host read frombuffer memory may be active. In Standby mode, theoscillator clock is disconnected from the rest of thecircuits, so that only the oscillator circuits draw power.Full Shutdown turns off the OSCillator, resulting inmaximum power savings. Note that this mode is notavailable when using an external clock source.78Q8373SRAMInterfacef-----10BaseTTransceiverHost! Buffer Data Link ManchesterPCMCIA Manager Controller ENDECInterfacePowerManagementAUIPortIPCMCIABusTransmissionMediumFIGURE 1: System Diagram7-17

551 78Q83733V, 5V PCMCIAEthernet ComboPin Assignment Table - PCMCIA Bus Mode - 100-Pln TQFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE1 D1 104 26 OE I 51 RA42 D8 104U 27 WE I 52 RA53 DO 104 28 INPACK 04 53 RA64 AO I 29 REG I 54 GND5 A1 I 30 ROMG 04 55 VDD6 A2 I 31 FCE 04 56 RA77 A3 I 32 XPD 04 57 RA128 RESET SI 33 XRST 04 58 RA149 VDD P 34 GND P 59 RWE10 GNO P 35 ROO 104U 60 RA1311 10WR I 36 R01 104U 61 RA812 lORD I 37 RD2 104U 62 RA913 CE2 I 38 R03 104U 63 RA1114 015 104U 39 R04 104U 64 ROE15 CE1 I 40 R05 104U 65 RA1516 D14 104U 41 R06 104U 66 OSCI17 07 104 42 R07 104U 67 OSCO18 GND P 43 GNO P 68 VOO19 D13 104U 44 RCSO 04 69 GND20 06 104 45 RCS1 04 70 GND21 D12 104U 46 RA10 04 71 TPON22 05 104 47 RAO 04 72 TPOP23 011 104U 48 RA1 04 73 TPON24 04 104 49 RA2 04 74 TPOP25 03 104 50 RA3 04 75 VODlegend:PIN# PIN NAME TYPE PIN# PIN NAME TYPE04 76 DON AO04 77 DOP AO04 78 AGND PP 79 REXT RP 80 AVDD P04 81 TPIN AI04 82 TPIP AI04 83 MODE TI04 84 DIN AI04 85 DIP AI04 86 CIN AI04 87 CIP AI04 88 GNO P04 89 SPKRIN SI04 90 SPKR 08CI 91 CCRA I0 92 RRST 04P 93 lEOlT 0016P 94 CB 04P 95 10lS16 04AO 96 IREO 08AO 97 WAIT 04AO 98 010 104UAO 99 02 104P 100 09 104UI: Input (TTL level)04,08: Output with 10l = 4 or 8 rnA0016: Output Open Drain with 10l = 16 rnA104, 104U: Input (TTL level) and Output with 10l = 4 rnA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level inputSI: Schmitt trigger inputTI: Three-state input. May be connected to low, high, or left open.AI: Analog inputAO: Analog outputP: PowerR: Resistor to ground0: Output7-18

SSI78Q83733V, 5V PCMCIAEthernet ComboPin Assignment Table - PCMCIA Bus Mode -100-Pln QFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN#1 D10 104U 26 D11 104U 512 D2 104 27 D4 104 523 D9 104U 28 D3 104 534 D1 104 29 OE I 545 D8 104U 30 WE I 556 DO 104 31 INPACK 04 567 AO I 32 REG I 578 Ai I 33 ROMG 04 589 A2 I 34 FCE 04 5910 A3 I 35 XPD 04 6011 RESET SI 36 XRST 04 6112 VDD P 37 GND P 6213 GND P 38 RDO 104U 6314 10WR I 39 RD1 104U 6415 lORD I 40 RD2 104U 6516 CE2 I 41 RD3 104U 6617 015 104U 42 RD4 104U 6718 CE1 I 43 RD5 104U 6819 D14 104U 44 RD6 104U 6920 D7 104 45 RD7 104U 7021 GND P 46 GND P 7122 D13 104U 47 RCSO 04 7223 D6 104 48 RCS1 04 7324 D12 104U 49 RA10 04 7425 D5 104 50 RAO 04 75Legend:PIN NAME TYPERA1 04RA2 04RA3 04RA4 04RA5 04RA6 04GND PVDD PRA7 04RA12 04RA14 04RWE 04RA13 04RA8 04RA9 04RA11 04ROE 04RA15 04OSCI CIOSCO 0VDD PGND PGND PTPDN AOTPDP AOPIN# PIN NAME TYPE76 TPON AO77 TPOP AO78 VDD P79 DON AO80 DOP AO81 AGND P82 REXT R83 AVDD P84 TPIN AI85 TPIP AI86 MODE TI87 DIN AI88 DIP AI89 CIN AI90 CIP AI91 GND P92 SPKRIN SI93 SPKR 0894 CCRA I95 RRST 0496 LEDLT OD1697 CB 0498 101816 0499 IREO 08100 WAIT 04II: Input (TTL level)04, 08: Output with 10L = 4 or 8 mAOD16: Output Open Drain with 10L = 16 mA104, 104U: Input (TTL level) and Output with 10L = 4 mA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level inputSI: Schmitt trigger inputTI: Three-state input. May be connected to low, high, or left open.AI: Analog inputAO: Analog outputP: PowerR: Resistor to ground0: Output 7-19

551 78Q83733V, 5V PCMCIAEthernet ComboPin Assignment Table - Generic Bus Mode -100-Pln TQFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE1 HD1 104 26 RD8 104U 51 RA42 HD8 104U 27 RD9 104U 52 RA53 HDO 104 28 RD10 104U 53 RA64 HAO I 29 RD11 104U 54 GND5 HA1 I 30 RD12 104U 55 VDD6 HA2 I 31 RD13 104U 56 RA77 HA3 I 32 RD14 104U 57 RA128 RESET SI 33 RD15 104U 58 RA149 VDD P 34 GND P 59 RWE10 GND P 35 ROO I04U 60 RA1311 WR I 36 RD1 I04U 61 RA812 RD I 37 RD2 104U 62 RA913 SHE I 38 RD3 104U 63 RA1114 HD15 104U 39 RD4 104U 64 ROE15 CS I 40 RD5 104U 65 RA1516 HD14 104U 41 RD6 104U 66 OSCI17 HD7 104 42 RD7 104U 67 OSCO18 GND P "43 GND 104U 68 VDD19 HD13 104U 44 RCSO P 69 GND20 HD6 104 45 RCS1 04 70 GND21 HD12 104U 46 RA10 04 71 TPDN22 HD5 104 47 RAO 04 72 TPDP23 HD11 104U 48 RA1 04 73 TPON24 HD4 104 49 RA2 04 74 TPOP25 HD3 104 50 RA3 04 75 VDDLegend:PIN# PIN NAME TYPE PIN# PIN NAME TYPE04 76 DON AO04 77 DOP AO04 78 AGND PP 79 REXT RP 80 AVDD P04 81 TPIN AI04 82 TPIP AI04 83 MODE TI04 84 DIN AI04 85 DIP AI04 86 CIN AI04 87 CIP AI04 88 GND P04 89 DMACK SI04 90 DMREQ 08CI 91 EOP I0 92 RRST 04P 93 LEDLT 0016P 94 CS 04P 95 HWORD 04AO 96 INT 08AO 97 READY 04AO 98 HD10 104UAO 99 HD2 104P 100 HOg 104UI: I nput (TTL level)04,08: Output with IOL = 4 or 8 rnA0016: Output Open Drain with 10L = 16 rnA104, 104U: Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level inputSI: Schmitt trigger inputTI: Three-state input. May be connected to low, high, or left open.AI: Analog inputAO: Analog outputP: PowerR: Resistor to ground0: Output7-20

SSI78Q83733V, 5V PCMCIAEthernet ComboPin Assignment Table - Generic Bus Mode -100-Pin QFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN#1 HD10 104U 26 HD11 104U 512 HD2 104 27 HD4 104 523 HD9 104U 28 HD3 104 534 HD1 104 29 RD8 104U 545 HD8 104U 30 RD9 104U 556 HDO 104 31 RD10 104U 567 HAO I 32 RD11 104U 578 HA1 I 33 RD12 104U 589 HA2 I 34 RD13 104U 5910 HA3 I 35 RD14 104U 6011 RESET SI 36 RD15 104U 6112 VDD P 37 GND P 6213 GND P 38 ROO 104U 6314 WR I 39 RD1 104U 6415 RD I 40 RD2 104U 6516 BHE I 41 RD3 104U 6617 HD15 104U 42 RD4 104U 6718 CS I 43 RD5 104U 6819 HD14 104U 44 RD6 104U 6920 HD7 104 45 RD7 104U 7021 GND P 46 GND P 7122 HD13 104U 47 RCSO 04 7223 HD6 104 48 RCS1 04 7324 HD12 104U 49 RA10 04 7425 HD5 104 50 RAO 04 75Legend:PIN NAME TYPERA1 04RA2 04RA3 04RA4 04RA5 04RA6 04GND PVDDPRA7 04RA12 04RA14 04RWE 04RA13 04RA8 04RA9 04RA11 04ROE 04RA15 04OSCI CIOSCO 0VDD PGNDGNDTPDNTPDPPPAOAOPIN# PIN NAME TYPE76 TPON AO77 TPOP AO78 VDD P79 DON AO80 DOP AO81 AGND P82 REXT R83 AVDD P84 TPIN AI85 TPIP AI86 MODE TI87 DIN AI88 DIP AI89 CIN AI90 CIP AI91 GND P92 DMACK SI93 DMREQ 0894 EOP I95 RRST 0496 LEDLT 001697 CB 0498 HWORD 0499 INT 08100 READY 04II: Input (TTL level)04, 08: Output with 10L = 4 or 8 rnA0016: Output Open Drain with 10L = 16 mA104, 104U: Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level inputSI: Schmitt trigger inputTI: Three-state input. May be connected to low, high, or left open.AI: Analog inputAO: Analog outputP: PowerR: Resistor to ground0: Output7-21

SSI78Q83733V, 5V PCMCIAEthernet ComboPIN DESCRIPTIONHOST BUS INTERFACE· PCMCIA BUS MODENAME TYPE DESCRIPTIONRESET I HARDWARE RESET. Active high. A minimum pulse length of 800 ns isrequired. This pin resets the 8373's internal pointers and registers to theirappropriate states. It also clears the CI (Configuration Index) in the CCR (CardConfiguration Register), thus placing the 8373 in an unconfigured (MemoryonlyInterface) state. The 8373 remains in the unconfigured state until the CIhas been written with a non-zero value.IOWR I liD WRITE. The IOWR pin is an active low input that enables a write operationby the host to the 8373 internal registers as selected by the host address inputsA[0:3]. The REG and at least one of CE1 or CE2 must be also active for theliD write to take place. The 8373 will not respond to the IOWR signal until it hasbeen configured for liD operation by the host.lORD I 1/0 READ. The lORD pin is an active low input that enables a read operationby the host from the 8373 internal registers as selected by the host addressinputs A[0:3]. The REG and at least one of CE1 or CE2 must be also active forthe liD read to take place. The 8373 will not"respond to the lORD signal untilit has been configured for liD operation by the host.CE1, CE2 I CH I P ENABL E. Active low input signals acting as chip select for the 8373. CE 1enables even-numbered address bytes and CE2 enables odd-numberedaddress bytes. When the 8373 is programmed to be in byte mode (DLCR6HBVTE bit is a "1"), CE2 is a don't care and only lower databus 0[0:7] is usedfor data transfer. Combinations of CE1, CE2, AO and HBVTE bit (DLCR6

SSI78Q83733V, 5V PCMCIAEthernet ComboHOST BUS INTERFACE· PCMCIA BUS MODE (continued)NAME TYPE DESCRIPTIONWE I WRITE ENABLE. An active low input signal used to write data to the internalCCR (Card Configuration Registers) and to the external Attribute (Flash)Memory (through the activation of FCE). This WE should also connect to thewrite enable of the external Flash Memory.REG I ATTRIBUTE MEMORY SELECT. When this signal is active (low), it signifiesaccess from or to the Attribute Memory (OE or WE active) or the I/O space(lORD or 10WR active). Attribute Memory is generally used to record cardcapacity and other configuration and attribute information. This includes thestandardized CCRs (Card Configuration Registers) which are located internallyin the 8373. When Attribute Memory is accessed, only data signals 0[0 :7]are valid and signals 0[8:15) are ignored.A[0:3) I ADDRESS BUS. Selects the set of 8373 internal registers including the CCR(Card Configuration Registers) for read or write operations.0[0:15) I/O DATA BUS. A bi-directional, tri-state bus. The combinations of CE1 , CE2 andAO control the portion of the bus that is being utilized. A[0:3) and RBNK1,0(DLCR7

SSI78Q83733V, 5V PCMCIAEthernet ComboPIN DESCRIPTION (continued)PCMCIA APPLICATION PINSNAME TYPE DESCRIPTIONROMG 0 ROM ENABLE. Active low. This signal will be activated when an attributememory read is performed on the external CIS memory.FeE 0 FLASH MEMORY CHIP ENABLE. Active low. The flash memory WE (WriteEnable) and OE (Output Enable) come from PCMCIA pins WE and OE .XPD 0 EXTERNAL POWER DOWN. Active low. When the 8373 enters power downmode, this pin will be low. It can be used to control power down of externaldevices residing on the same card.XRST 0 EXTERNAL RESET. Active high. This pin is a reflection of CCRO registerbit. This allows a software controlled hardware reset of the 8373 and the restof the devices residing on the same card.SPKRIN I SPEAKER IN. This pin is qualified with the AUDIO bit, CCR1 to producethe inverted SPKR output.7-24

SSI78Q83733V, 5V PCMCIAEthernet ComboHOST BUS INTERFACE· GENERIC BUS MODENAME TYPE DESCRIPTIONRESET I HARDWARE RESET. Active high. A minimum pulse length of 800 ns isrequired. This pin resets the 8373's internal pOinters and registers to theirappropriate states. Note: the 8373 must be reset after power on before usage.READY 0 READY. This output is asserted to indicate to the host that the 8373 is readyto complete the requested read or write operation. It will also be used if thedevice is unable to respond to read or write requests within 2.4 IlS. In thesesituations, the 8373 will also assert INT and the host read error status bit(DLCR1

SSI78Q83733V, 5V PCMCIAEthernet ComboPIN DESCRIPTION (continued)HOST BUS INTERFACE· GENERIC BUS MODENAME TYPE DESCRIPTIONDMACK I DMA ACKNOWLEDGE. An active low signal issued by the Host DMAcontroller when it is ready to pe~orm data transfers between the Host and the8373's buffer memory via BMR8.HA[0:3] I HOST ADDRESS. Selects the set of internal registers to be accessible by the8373 for read or write operations.HD[0:15] I/O HOST DATA BUS. A bi-directional, tri-state bus for data, command and statustransfers between the Host and the 8373 with the direction being controlled byRD and WR. The combinations of HBYTE, BHE and HAO control the portionof the bus that is being utilized. HA[0:3] and RBNK (DLCR7

SSI78Q83733V, 5V PCMCIAEthernet ComboNETWORK TWISTED-PAIR MEDIUM INTERFACENAME TYPE DESCRIPTIONTPON, TPOP 0 TWISTED-PAIR OUTPUT NEGATIVE and POSITIVE. Driver outputs totwisted-pair medium. Must be summed together with TPDN and TPDP byexternal resistors in a pre-equalization network to produce twisted-pair transmitsignal.TPDN, TPDP 0 TWISTED-PAIR DELAYED NEGATIVE and POSITIVE. Delayed (50 ns)driver outputs to twisted-pair medium. Must be summed together with TPONand TPOP by external resistors in a pre-equalization network to producetwisted-pair transmit signal.TPIN, TPIP I TWISTED-PAIR INPUT NEGATIVE and POSITIVE. Inputs from twisted-pairmedium.DEVICE POWERVDD P POWER SUPPLY. A +5V DC (±5%) or +3.3 VDC (±0.3V) supply is required.GND P SYSTEM GROUND.AVDD P ANALOG VDD. The analog VDD pin required by the internal AUI and twistedpaircircuits is to be connected to a different VDD path from the digital VDD.A +5V DC (±5%) or +3.3 VDC (±0.3V) supply is required.AGND P ANALOG GROUND. The analog ground required by the internal encoder/decoder is to be connected to a separate GND path from the digital GND.CRYSTAL OSCILLATOROSCI I OSCILLATOR IN. Connection for one side of the 20 MHz crystal or an inputfor an external 20 MHz clock source.OSCO 0 OSCILLATOR OUT. Connection for other side of the 20 MHz crystal. Leftunconnected if an external clock is used.MISCELLANEOUSCB 0 CONTROL BIT. A complement of the internal register bit, DLCR4 , whichis used to activate any external hardware.RRST 0 REMOTE RESET. This pin follows the RMTRST register bit (DLCR1

SSI78Q83733V, 5V PCMCIAEthernet ComboELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation beyond the maximum ratings may damage the device.PARAMETERSupply voltage, VddInput voltage, YinOutput voltage, VoutStorage temperature, TstgLead temperature (max 10 sec soldering), TIRATING-0.5 to 6.0V-0.5 to Vdd + 0.5V-0.5 to Vdd + 0.5V-55 to 150°C250°C maxDC CHARACTERISTICS (Ta = 0 to 70°C, Vdd = 5V ±5%, 5V Values)PARAMETER CONDITIONS MIN NOMLow level input voltage Vii TTL inputsosel pinSchmitt inputsHigh level input voltage Vih TTL inputs 2.2ascI pin 3.8Schmitt inputs 3.5Pull down current (RESET pin )Ipd 13Low level output voltage Vol Rated 101 0High level output voltage Voh Rated loh 2.4Low level output current 101 Pin types 04, Vdd = 5V 4104,104U(with Vol = OAV) Pin type 08 Vdd = 5V 8Pin type 0016 Vdd = 5V 16High level output current loh Pin types 04, Vdd = 5V -4104,104U(with Voh = 2AV) Pin type 08 Vdd = 5V -8Leakage current (input/output) II -10Supply current Idd Fullyactive(1)IdlePower down supplycurrent Ipwrdn Osc. onOsc. offMAXUNIT0.8 V1.6 V1.1 VVVV50 JJA0.4 VVdd VmAmAmAmAmA10 JJA40 mA30 mA10 mA100 JJANote: (1) Fully active means 3 "simultaneous" operations: transmitting, receiving (through twisted-pair port)and either host write or read.7-28

SSI78Q83733V, 5V PCMCIAEthernet ComboDC CHARACTERISTICS (Ta = 0 to 70°C, Vdd = 3.3V ±0.3V, 3V Values)PARAMETER CONDITIONS MINLow level input voltage Vii TIL inputsOSCI pinSchmitt inputsHigh level input voltage Vih TIL inputs 2OSCI pin 2.1Schmitt inputs 2.4Pull down current (RESET pin) Ipd 5Low level output voltage Vol Rated 101 0High level output voltage Voh Rated loh 2.4Low level output current 101 Pin types 04, Vdd = 3.3V 2.4104,104U(with Vol = O.4V) Pin type 08 Vdd = 3.3V 4.9Pin type 0016 Vdd = 3.3V 9.8High level output current loh Pin types 04, Vdd = 3.3V -1.5104,104U(with Voh = 2.4V) Pin type 08 Vdd = 3.3V -3Leakage current (input/output) II -10Supply current Idd Fully active(1)IdlePower down supplycurrent Ipwrdn Osc. onNOM MAX UNIT0.8 V0.7 V0.4 VVVV28 ~0.4 VVddVrnArnArnArnArnA10 ~28 rnA20 rnA6 rnAOsc. off100 ~Note: (1) Fully active means 3 "simultaneous" operations: transmitting, receiving (through twisted-pair port)and either host write or read.I7-29

SSI78Q83733V, 5V PCMCIAEthernet ComboELECTRICAL SPECIFICATIONS (continued)AUI CHARACTERISTICS(VDD = 5V ± 5%, 3.3 ± 0.3V, Vss = OV, Ta = O°C to +70°C)PARAMETERLow Output Voltage for DOP, DONVaol RI = 780CONDITIONSRext = 20 kOHigh Output Voltage for DOP, DON Rext = 20 kQVaoh RI = 780DOP, DON Output CurrentlaoRext = 20 kODIP, DIN, CIP, CIN Open Circuit Vdd = 5V ± 5%Input Voltage (bias) Valb Vdd = 3.3 ± 0.3VDIP, DIN, CIP, CIN Diff SquelchThresholdVasqDOP, DON Diff Idle Output RI = 780VadiDOP, DON Diff Peak Output Rext = 20 kOVadv RI = 780DOP, DON Output ResistanceRaoMIN NOM MAX UNITVdd-1.5 Vdd-0.75 VVdd-0.55 Vdd V8 14 mA2.45 3.33 V2.13 2.88-300 -120 mV-40 40 mV620 1100 mV75 07-30

SSI78Q83733V, 5V PCMCIAEthernet ComboTWISTED PAIR(VDD = 5V ± 5%, Ta = O°C to +70°C)PARAMETERTPIP, TPIN Diff Input ResistanceRtiTPIP, TPIN Open Circuit InputVoltage (bias)VtibCONDITIONSTPIP, TPIN Diff Input VoltageRange Vtiv VDD = 5VTPIP, TPIN Positive Squelched Note 1ThresholdVtpsTPIP, TPIN Negative Squelched Note 1ThresholdVtnsTPIP, TPIN Positive Unsquelched Note 2ThresholdVtpuTPIP, TPIN Negative Unsquelched Note 2ThresholdVtnuTPIP, TPIN Positive Squelched Note 1Threshold Long Distance Mode VltpsTPIP, TPIN Negative Squelched Note 1Threshold Long Distance Mode VltnsTPIP, TPIN Positive Unsquelched Note 2Threshold Long Distance Mode VltpuTPIP, TPIN Negative Unsquelched Note 2Threshold Long Distance Mode VltnuTPOP, TPON High Output VoltageVtohTPOP, TPON Low Output VoltageVtolTPDP, TPDN High VoltageVtdhTPDP, TPDN Low VoltageTPDP, TPDN Output ResistanceVtdlRtdTPOP, TPON Output ResistanceRto1= 32 mA1= 32 mA1= 16 mA1= 16 mAMIN32.45-3.1300-585120-300Vddtp-0.44VsstpVddtp-0.44VsstpNOM MAX UNITkQ3.33 V3.1 V585 mV-300 mV180 mV-180 mV300 mV-120 mV100 mV-100 mVVddtpVsstp+0.44VddtpVsstp+0.44VVVV27 n13.5 nINote 1: Sine wave at 2 MHz, 5 MHz and 7 MHzNote 2: Sine wave: 5 MHz::; f::; 10 MHz7-31

SSI78Q83733V, 5V PCMCIAEthernet ComboELECTRICAL SPECIFICATIONS (continued)TWISTED PAIR(VOO = 3.3 ± 0.3V, Ta = O°C to +70°C)PARAMETERTPIP, TPIN Oiff Input ResistanceRtiTPIP, TPIN Open Circuit InputVoltage (bias)VtibCONDITIONSTPIP, TPIN Oiff Input VoltageRange Vtiv VOO = 3.3VTPIP, TPIN Positive Squelched Note 1ThresholdVtpsTPIP, TPIN Negative Squelched Note 1ThresholdVtnsTPIP, TPIN Positive Unsquelched Note 2ThresholdVtpuTPIP, TPIN Negative Unsquelched Note 2ThresholdVtnuTPIP, TPIN Positive Squelched Note 1Threshold Long Distance Mode VltpsTPIP, TPIN Negative Squelched Note 1Threshold Long Distance Mode VltnsTPIP, TPIN Positive Unsquelched Note 2Threshold Long Distance Mode VltpuTPIP, TPIN Negative Unsquelched Note 2Threshold Long Distance Mode VltnuTPOP, TPON High Output VoltageVtohTPOP, TPON Low Output VoltageVtolTPOP, TPON High VoltageTPOP, TPON Low VoltageVtdhVtdlTPDP, TPDN Output Resistance RtdTPOP, TPON Output Resistance Rto1= 50 rnA1= 50 rnA1= 25 mA1= 25 rnANote 1: Sine wave at 2 MHz, 5 MHz and 7 MHzNote 2: Sine wave: 5 MHz ~ f ~ 10 MHzMIN NOM MAX UNIT3 kQ2.13 2.88 V-2.2 2.2 V210 410 rnV-410 -210 rnV130 rnV-130 rnV90 210 rnV-210 -90 mV70 rnV-70 rnVVddTP VddTP V-0.3VSSTP VSSTP V+0.3VddTP VddTP V-0.3VSSTP VSSTP V+0.312 Q6 Q7-32

1SSI78Q83733V, 5V PCMCIAEthernet ComboTRANSFORMER RATIO:5V OPERATIONRX1 :1TX1 :13.3V OPERATIONRXTX1 :1.4 (step down)1 :1.4 (step down)CCRA,A[O:3]OE ---t-...., f4-----t3----.-j ,----+-----CCRA=O:FCE ----+-------.AOMG _~_bt,1ICCRA = 1:0[0:7] ----+---(J(FROM 8370) 1'--------+---'1i -IFIGURE 2: Attribute Memory Read Cycle (PCMCIA mode)7-33

SSI78Q83733V, 5V PCMCIAEthernet ComboUnless otherwise stated, the following conditions apply to the remaining timing tables:Ta = O°C to +70°C, Vdd = 5 ± 5%, Vdd = 3.3V ± O.3VTABLE 1: Attribute Memory Read Cycle (PCMCIA mode) (Refer to Figure 2)PARAMETER CONDITIONS MIN NOMCCRA, A[O:3] Valid to OE low; t1 0REG, CE1 low to OE lowOE high to CCRA, A[O:3] invalid; t2 0OE high to REG, CE1 highOE low pulse width t3 Vdd = 5V 30Vdd = 3.3V 35MAXUNITnsnsnsnsOE low to 0[0:7] validt4OE high to 0[0:7] invalid t5 10(data hold)OE low to FCE low t6 Vdd = 5VVdd = 3.3VOE high to FCE high t7 Vdd = 5VVdd = 3.3VOE low to ROMG low t8 Vdd = 5VVdd = 3.3VOE high to ROMG high t9 Vdd = 5VVdd = 3.3V45 nsns25 ns35 ns25 ns35 ns25 ns35 ns25 ns35 nsTABLE 2: Attribute Memory Write Cycle (PCMCIA MODE) (Refer to Figure 3)PARAMETER CONDITIONS MIN NOMCCRA, A[O:3] Valid to WE low; t1 0REG, CE1 low to WE lowWE high to CCRA, A[0:3] invalid; t2 0WE high to REG, CE1 highWE low pulse width t3 Vdd = 5V 30Vdd = 3.3V 350[0:7] valid to WE high t4 15(data setup)WE high to 0[0:7] invalid t5 10(data hold)MAXUNITnsnsnsnsnsnsWE low to FCE low ts Vdd = 5VVdd = 3.3VWE high to FCE high t7 Vdd = 5VVdd = 3.3V25 ns35 ns25 ns35 ns7-34

i551 78Q83733V, 5V PCMCIAEthernet ComboCCRA,A[0:3]~v~I\\;-------~1\I'-t1-~1\-~ '\_---- --_.-//I'-t2-//CCRA =0:FeE--\1\t6 I--\1\t3J------....- ---Ir-t71-I(logic high)CCRA= 1"0[0:7](TO 8370)4t5-FIGURE 3: Attribute Memory Write Cycle (PCMCIA mode)I7-35

551 78Q83733V, 5V PCMCIAEthernet ComboA[0:3]\1 \1/\ /\\ V\ /.t1·~t2·\ V\ /t3\ 1\ jWAIT (a)WAIT (b)0[0:15](FROM 8370)--+t6f+- -. t7 ~\ Vi\ /- r-ts-~t4 f4-T,1f\-/-+- t9 f+-(logic high)18- I-t10 --FIGURE 4: I/O Read Cycle (PCMCIA mode)7-36

SSI78Q83733V, 5V PCMCIAEthernet ComboTABLE 3: 1/0 Read Cycle (PCMCIA mode) (Refer to Figure 4)PARAMETERA[0:3] valid to lORD LOW; t1REG, CE1, CE2 low to lORD lowlORD high to A[0:3] invalid; t2lORD high to REG, CE1, CE2 highCONDITIONSlORD low pulse width t3 Vdd = 5VVdd = 3.3VlORD low to WAIT low t4 Port busy (a) Vdd = 5VlORD low to WAIT high(1) t5 Port busy (a)Vdd = 3.3VlORD low to INPACK low t6 Vdd = 5VVdd = 3.3VlORD high to INPACK high t7 Vdd = 5VVdd = 3.3VlORD low to 0[0:15] valid t8 Register access (b) Vdd = 5VWAIT high to 0[0:15] valid t9 Port busy (a)lORD high to 0[0:15] invalid t 10(data hold)Vdd = 3.3VTABLE 4: 1/0 Write Cycle (PCMCIA mode) (Refer to Figure 5)MIN003035010NOM MAX UNITnsnsnsns35 ns50 ns350 ns25 ns35 ns25 ns35 ns50 ns70 ns5 nsnsA[0:3] valid to IOWR LOW; t1REG, CE1, CE2 low to IOWR lowIOWR high to A[0:3] invalid; t2IOWR high to REG, CE1, CE2 highIOWR low pulse width t3 Vdd = 5VVdd = 3.3VIOWR low to WAIT low t4 Port busy (a) Vdd = 5VIOWR low to WAIT high(1) t5 Port busy (a)D[0:15] valid to IOWR high(data setup)IOWR high to D[0:15] invalid(data hold)tst7Vdd = 3.3V0030351510nsnsnsns35 ns50 ns350 nsNote: (1) Maximum of 350 ns may occur if system makes contiguous system read cycles at less than 100 nsintervals, and both the transmitter and receiver are active in "Ioopback" reception (if the transmitterand receiver are idle, the max value becomes 250 ns). 2.4 f.1s max for host read error.(a) For Buffer Memory Port when port is busy.(b) For register or port is not busy.7-37nsnsI

SSI78Q83733V, 5V PCMCIAEthernet ComboA[0:3]INPACK------~----------------~----------(logic high)WAIT (a) ----+-WAIT(~------~----------------_+---------­(logic high)0[0:15] -------I-----C(to 8370)FIGURE 5: 1/0 Write Cycle (PCMCIA mode)7-38

~SSI78Q83733V, 5V PCMCIAEthernet ComboHA[0:3]csRDREADY(a)READY(b)READY(c)READY(d)HD[0:1S](from 8370)---,.vr.-t1~~1\--ts~~t41\~ t 6 ---..~8\\/~t2~It3•/V~t7~J(logic high)f4--t9~J1I4-t11~13 --""Ir---...-t 12 __...t 10FIGURE 6: Read Cycle, Generic Bus Mode (Refer to Table 9)I7-39

SSI78Q83733V, 5V PCMCIAEthernet ComboTABLE 5: Read Cycle, Generic Bus Mode (Refer to Figure 6)MIN NOM MAX UNITt 13PARAMETERCONDITIONS(data hold)CS low to RD low;0 nsHA[0:3] valid to RD lowt1RD high to CS high;0 nsRD high to HA[0:3] invalid t2RD low pulse width t3 Vdd = 5V 30 nsVdd = 3.3V 35 nsRD low to READY low t4 (a) Vdd = 5V 0 35 nsVdd = 3.3V45 nsRD low to READY high (1) ts (a)350 nsRD low to READY low (1) ts (b)0 350 nsRD high to READY high t7 (b)0 25 nsRD low to READY low ts (d) Vdd = 5V 0 30 nsVdd = 3.3V40 nsRD high to READY high t9 (d)0 28 nsRD low to HD[0:15] valid t 10 Register access Vdd = 5V45 nsVdd = 3.3V60 nsREADY high to HD[0:15] validt 11 Port access5 nsREADY low to HD[0:15] valid t12 Port access5 nsRD high to HD[0:15] invalid10 nsNote: (1) Maximum of 350 ns may occur if system makes contiguous system read cycles at less than100 ns intervals, and both the transmitter and receiver are active in "Ioopback" reception (if thetransmitter and receiver are idle, the max value becomes 250 ns). 2.411.5 max for host read error.(a) For Buffer Memory Port when port is busy and RDYSEL = 1.(b) For Buffer Memory Port when port is busy and RDYSEL = o.(c) For register or port is not busy and RDYSEL = 1.(d) For register or port is not busy and RDYSEL = o.7-40

551 78Q83733V, 5V PCMCIAEthernet ComboHA[0:3) ~----1cs~t1-"~~t2-"\WRt3READY(a)READY(b)I~ t4ts~t7~READY(c)f4---t6~(logic high)READY(d)HD[0:15)(to 8370)'\m~t9~.. ..t10 -t11..~FIGURE 7: Write Cycle, Generic Bus Mode (Refer to Table 10)I7-41

SSI78Q83733V, 5V PCMCIAEthernet ComboTABLE 6: Write Cycle, Generic Bus Mode (Refer to Figure 7)PARAMETERCS low to WR low;HA[O :3] valid to WR low t,WR high to CS high;WR high to HA[0:3] invalidt2CONDITIONSWR low pulse width t3 Vdd = 5VVdd = 3.3VWR low to READY low t4 (a) Vdd = 5VWR low to READY high (') ts (a)WR low to READY low (1) ts (b)WR high to READY high t7 (b)Vdd = 3.3VWR low to READY low ta (d) Vdd = 5VWR high to READY high t9 (d)HD[0:15] valid to WR high(data setup)t,oWR high to HD[0:15] invalid(data hold) t"Vdd = 3.3VMIN NOM MAX UNIT0 ns0 ns30 ns35 ns0 35 ns45 ns350 ns0 350 ns28 ns0 30 ns40 ns0 25 ns15 ns10 nsNote:(1) Maximum of 350 ns may occur if system makes contiguous system read cycles at less than100 ns intervals, and both the transmitter and receiver are active on "Ioopback" reception (if thetransmitter and receiver are idle, the max value becomes 250 ns). 2.4lls max for host write error.(a) For Buffer Memory Port when port is busy and RDYSEL = 1.(b) For Buffer Memory Port when port is busy and RDYSEL = O.(c) For register or port is not busy and RDYSEL = 1.(d) For register or port is not busy and RDYSEL = O.7-42

SSI78Q83733V, 5V PCMCIAEthernet ComboDMREQDMACK-----------.IRD or WR -------~EOP--------------------~FIGURE 8: Single-Cycle DMA TimingTABLE 7: Single-Cycle DMA Timing (Refer to Figure 8)PARAMETER CONDITIONS MINDMACK low to DMREO low t1 Vdd = 5V 0Vdd = 3.3VDMACK high to DMREO high t2 Vdd = 5V 0Vdd = 3.3VDMACK low to RD or WR low t3 0RD or WR high to DMACK high t4 0RD or WR low to Eap low t5 0Eap high to DMACK high t6 0Eap low pulse width t7 10NOM MAX UNIT25 ns30 ns25 ns30 nsnsnsnsnsnsINote: (1) An asserted Eap terminates any further DMREO after DMACK returns high.(2) The DMA cycle uses DMACK as the chip select. DMACK overrides CS and HA[0:3] if they are bothasserted at the same time, forcing selection of the Buffer Memory Port as in a DMA cycle.(3) For READY timing and HD[0:15] timing, see Figure 6, t 4-t 13, and Figure 7, t 4-t 11.7-43

SSI78Q83733V, 5V PCMCIAEthernet ComboDMREQ ---.I---~----------~f~----'DMACK----~\~ __________ ~~------+_------------~IRDorWR--------~\~ ____ ~TABLE 8: Burst DMA TimingFIGURE 9: Burst DMA TimingPARAMETER CONDITIONS MINRD or WR low to DMREQ low SV t13.3V t1RD or WR high to DMACK high t2 0NOM MAX UNIT30 ns40 nsnsNote: (1) DMREQ goes low during the next-to-Iast transfer of the burst. DMACK should not go high until afterthe RD or WR pulse of the last transfer cycle goes high(2) The DMA cycle uses DMACK as the chip select. DMACK overrides CS and HA[O :3] if they are bothasserted at the same time, forCing selection of the Buffer Memory Port as in a DMA cycle.(3) For READY timing and HD[0:1S] timing, see Figure 6, t 4-t 13, and Figure 7, t 4-t 11.7-44

551 78Q83733V, 5V PCMCIAEthernet ComboDMREO~DMACK ~'----______ ----\'r--____ ----.JIRDorWR --~14--~ BURST INTERRUPTEDFIGURE 10: Burst DMA Interrupted by DMACKNote: Burst can be interrupted by DMACK high-going pulse during the burst. Bu rst will resume when DMACK retu rnslow.DMREO_____ ~/~----------~0'RDorWR -----------~\~ ____ ~EOP --------------------------', .--------,. JIFIGURE 11: Burst DMA Terminated by EOPTABLE 9: Burst DMA Terminated by EOPPARAMETER CONDITIONS MIN NOM MAX UNITEOP low to DMREQ low t1 Vdd = 5V 4 28 nsVdd = 3.3V 35 nsEOP high to DMACK high t2 3 nsRD or WR low to EOP low t3 0 nsNote: EOP can be asserted during any transfer of the burst to terminate the process following that transfer.7-45

SSI-78Q83733V, 5V PCMCIAEthernet ComboRESETCSlCE1FIGURE 12: RESET TimingTABLE 10: RESET TimingPARAMETERRESET pulse widtht1RESET low to first CS/CE1 low t2CONDITIONS MIN NOM MAX UNIT500 ns800 nsCs/CE1 \WA/IOWR ~RD/IORD/ \tt1~~FIGURE 13: Skip Packet TimingTABLE 11: Skip Packet TimingPARAMETERWriting Skip Packet high tonext Buffer Memory Port read t1CONDITIONS MIN NOM MAX UNIT200 ns7-46

SSI78Q83733V, 5V PCMCIAEthernet ComboRA[O:15]RCSO,1/ROE/J... ~t 1... t2 ..~t3~t9 t7 ..RD[O:15] ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) «((((((((\t5..t4~...~Jt6/____ t8~»»»)FIGURE 14: SRAM Read TimingTABLE 12: SRAM Read TimingPARAMETERCONDITIONSRead cycle t1 RAMSP = 1RAMSP = 0Address access time t2 RAMSP = 1Address valid to RCSO,1 lowRCSO,1 high to address invalid t4t3RAMSP = 0Chip select access time t5 RAMSP = 1RAMSP = 0ROE high to RCSO,1 high t6Output enable access time t7 RAMSP = 1Data hold timeAddress valid to ROE lowt8t9RAMSP = 0MIN95145000NOM MAX UNITnsns75 ns125 ns8 nsns75 ns125 ns8 ns50 ns100 nsns30 nsNote: Use SRAM with address access time of 75 ns or less for RAMSP = 1 and 125 ns or less for RAMSP = O.RAMSP is DLCR6 .I7-47

SSI78Q83733V, 5V PCMCIAEthernet Combot1RA[O:15]J..~t2RCSO,1/ 1\RWERD[O:15]J~t6'\\'\\\\\\\\~~~~~~~~~1111111111111111111t3t4t7'10'\• ~5•---.. ...--r-ts-~..• ~ 8tg1+-111-.JI\\\\\\\JIIIIIIFIGURE 15: SRAM Write TimingTABLE 13: SRAM Write TimingPARAMETERCONDITIONSWrite Cycle t1 RAMSP = 1Address Valid to RCSO,1 low t2RAMSP= 0Address Valid to RWE high t3 RAMSP = 1RAMSP = 0RCSO,1 low to RWE high t4 RAMSP = 1RAMSP = 0RCSO,1 high to Address Invalid tsRCSO,1 low to RWE lowRWE Pulse Width t7 RAMSP = 1RAMSP = 0RWE high to RCSO,1 highRWE high to Address InvalidData Setup Time t 10 RAMSP = 1Data Hold Timet6tatgt11RAMSP = 0MIN NOM MAX UNIT95 ns145 ns8 ns70 ns120 ns70 ns120 ns0 ns0 ns70 ns120 ns0 ns10 ns40 ns90 ns20 nsNote: Use SRAM with address access time of 75 ns or less for RAMSP = 1 and 125 ns or less for RAMSP = O.RAMSP is DLCR6 .7-48

551 78Q83733V, 5V PCMCIAEthernet ComboSPKRINIII\\\L--------\II\ /- t1 - - t2 f-----FIGURE 16: Speaker TimingTABLE 14: Speaker Timing (Refer to Figure 16)PARAMETERCONDITIONSSPKRVdd = 5Vhigh to low propagation delay t1 Vdd = 3.3VSPKRVdd = 5Vlow to high propagation delay t2 Vdd = 3.3VMINNOM MAX UNIT25 ns30 ns25 ns30 ns----"-1 --t1--,r--__ _\'---_~{.L'_,_ ___ ~,IIJIFIGURE 17: Interrupt Timing (Generic Bus Mode)TABLE 15: Interrupt Timing (Generic Bus Mode)PARAMETER CONDITIONS MIN NOM MAX UNITINT t1 Vdd = 5V 7 40 nssignal cleaning delay Vdd = 3.3V 50 ns7-49

SSI78Q83733V, 5V PCMCIAEthernet ComboiOWALevel Interrupt:rnEQ~JIIIf\F'1lPulse Interrupt:lREQf-o- 12IFIGURE 18: Interrupt Timing (PCMCIA Mode)TABLE 16: Interrupt Timing (PCMCIA Mode)PARAMETERIREOsignal clearing delayIREO low pulse widtht1t2CONDITIONS MIN NOM MAX UNITlevel interrupt Vdd = 5V 7 40 nsVdd = 3.3V 50 nspulse interrupt 750 800 nsOOPIDON(Last Bit = 0)(VOO)DOPDON (VOO)OOPIDON -U(Last Bit = 1)oo~--------~~IIrIIIIII I I1~1 0 I I U ~~,--------~I~~. --·t1---1 I'--------' I II I II I Io~ h 1} { I I\'-_____ ,LJ LJ.-----·t1----to ...... I~~,~'j-! !FIGURE 19: Transmit Timing (AUI)TABLE 17: Transmit Timing (AUI)PARAMETER CONDITIONS MIN NOM MAX UNITDOP/DONend-of-packet delimiter t1 200 nsDOP/DONline voltage transition t2 8 f..lS7-50

551 78Q83733V, 5V PCMCIAEthernet ComboTPOPTPONTPDPTPDNo\J °L}==114'-----_Jl-n~_-o~ LFt2=\~_Jl---.JnL----TX±(Last bit = 0)TX±(Last bit = 1)FIGURE 20: Transmit Timing (TP)TABLE 18: Transmit Timing (TP)PARAMETERCONDITIONS MIN NOM MAX UNITTPOP/TPONend-of-packet delimiterTPDP/TPDNend-of-packet delimiterTPOP to TPDP and TPON toTPDN delayt1t2t3250 ns200 ns50 nsI7-51

SSI78Q83733V, 5V PCMCIAEthernet ComboTPOP---~ '\--t1--1' ~I.......----.------,/\'------TPON ________ ~--------------------------------::::-----~~--------------r--\--~r--\'-------TX +1. ____ ~~--------t3-------+-I-~'------(AfterSummation)Transmitted Link PulseTPI PIN ___ ---'{rr·====~\====~t_4 ------1Received Link Pulse\'------FIGURE 21: Link Test TimingTABLE 19: Link Test TimingPARAMETER CONDITIONS MIN NOM MAXTPOP link pulse width t1 150TPDP/TPDN link pulse width t2 100Duration between transmitted t3 9 11link pulsesDuration between receivedlink pulses t4 4.1 65UNITnsnsmsms7-52

SSI78Q83733V, 5V PCMCIAEthernet ComboLEDLT~~F'1--1-- .Link Down linkUp Transmit Link UpFIGURE 22: LED Timing (TP)TABLE 20: LED TimingPARAMETER CONDITIONS MIN NOM MAX UNITTransmit blink-off timing t1 TP selected 100 msLEDLTFIGURE 23: LED Timing (AUI)TABLE 21: LED TimingPARAMETER CONDITIONS MIN NOM MAX UNITTransmit blink-on timing t1 AU I selected 100 msIFIGURE 24: Oscillator Duty CycleTABLE 22: OSCI Duty CyclePARAMETER CONDITIONS MIN NOM MAX UNITOscillator duty cycle t1 40 50 60 %7-53

SSI78Q83733V, 5V PCMCIAEthernet ComboDIGITAL OUTPUT, I/O LOADI~OPFlDOP/DON OUTPUT LOADDOPDONREXTi~~}78QTTL INPUT WAVEFORM3:Test Point. 1.4V k --Vih = 2.0V- - - - - Vii = O.BVTTL OUTPUT WAVEFORM3:Testpoint=1.4V k- -Voh = 2AV- - - - - Vol = OAVDIP/DIN, CIP/CIN AND TPIPITPININPUT WAVEFORM3: k-_ Vih =4.5VTest Point = 3.5V- .- - - - Vii = 2.5VDOP/DON OUTPUT WAVEFORM3 E-- V O h =4.3VTest Point = 4.0V ~ - - - - Vol = 3.7VTPOPITPON OUTPUT WAVEFORM3 C-- VOh =4.0V.lest Point = 2.5V -, - - - - Vol = 1.0VFIGURE 25: Test Conditions7-54

SSI78Q83733V, 5V PCMCIAEthernet ComboPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.HD10HD2HD9HD1HD8HDOHADHA1HA29HA310RESET11VDD12GND13WR 14RD 15SHE 16HD15 17CS 18HD1419HD7 20GND 21HD13 22HD6 23HD1224HD5 25HD11 26HD4 27HD328RD8 29RD9 30cryN(")(") "

SSI78Q83733V, 5V PCMCIAEthernet ComboPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.010D2D901DeDOADA1f1.2.1>:3RESETVOOGNOIOWRiORl5CE2015CE1014D7GNO013D6012OS011D4D3OEWE242526272829•~~d';~SU;;g8l~IX>18~C1i~~oo8079~ ~z;; P.I ~ C; ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t:t~ ~ fB787776757473727170696867666564636261605958575655545352OOPDONVDOTPOPTPONTPOPTPONGNOGNOVDDOSCOOSCIRA15ROERA11RA9RASRA13RWERA14RA12RA7VDDGNDRA6RASRA4RA3RA2RA1100-Lead QFPPCMCIA Bus Mode7-56

551 78Q83733V, 5V PCMCIAEthernet ComboPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.HD1HOBHOOHAOHA1HA2HA3RESETVDDGND 10WR 11AD 12SHE 13HD15 14cs 15HD14 16HD7 17GND 18HD13 19H06 20HD12 21H05 22HD11 23H04 24H03 258813l!;;~~

SSI78Q83733V, 5V PCMCIAEthernet ComboPACKAGE PIN DESIGNATIONS(Top View)CAUTION: Use handling procedures necessaryfor a static sensitive component.01OSDONJAlfI.2/J3RESETVDOGNOIOWAlORDGE2015GET01407GNO013D6D12OS011D4D32 •6710 6611 6512 6413 63W ~15 61~ ~17 5918 5819 57~ 58~ ~~ 64~ ~~ ~~ ~~~~~~M~~~~~~~~~~~~~~~~~~~7574737271706968VDDTPOPTPONTPDPTPDNGNDGNDVDDOSCOOSCIRA15ROERA11RA9RAeRA13RiNERA14RA12RA7VDDGNDRA6RA5RM100-Lead TQFPPCMCIA Bus ModeORDERING INFORMATIONPART DESCRIPTIONORDER NUMBERPACKAGE MARK551 7808373 - PCMCIA Ethernet Combo1 DO-lead OFP 7808373-CG1DD-lead7808373TOFP78Q8373-CGT7808373-CG78Q8373-CGTPreliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations andare not guaranteed. Small quantities are available, and Silicon Systems should be consulted for cl,Jrrent information.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any.time without notice. Accordingly. the reader is cautioned to verify that the data sheetis current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-69140195 - rev 7-58 ©1994 Silicon Systems, Inc.

551 78Q8392Ethernet Coaxial TransceiverDESCRIPTIONThe 551 7808392 Ethernet Transceiver is a highspeed, bipolar coax line transmitter/receiver. The deviceincludes analog transmit and receive buffers, a 10 MHzon-board oscillator, timing logic for jabber and heartbeatfunctions, output drivers and bandgap reference, inaddition to a current reference and collision detector.This transceiver provides the interface between thesingle-ended coaxial cable signals and the Manchesterencodeddifferential logic signals. Primary functionalblocks include the receiver, transmitter, collisiondetection and jabber timer. This IC may be used ineither internal or external MAU environments.The 5517808392 is available in 16-pin plastic DIP and28-pin PLCC packages.FEATURESDecember 1994• Compliant with Ethernet II, IEEE 802.310Base5 and 10Base2 (Cheapernet)• Integrates all transceiver functions exceptsignal and power isolation• Innovative design minimizes external componentscount and power consumption• Jabber timer function integrated on chip• Externally selectable CEO heartbeat allowsoperation with IEEE 802.3 compatible repeaters• Squelch circuitry at all inputs rejects noiseSSI 78Q8392 CONNECTION DIAGRAMPIN DIAGRAM5100±5%x4-9VCD+VEECD- 2 15 TXOCOLLISIOUSIGNALTODTEDATATUDTE'--+_--r-+-LJ~---~VEEVEECDSTXO LJ------KJ----,RXI L.I------.GNDRX+ 3 14 RXIVEE 4 13 VEEVEE 5 12 RR-RX- 6 11 RR+TX+ 7 10 GNDITX+HBE16-Pin DIPDATAFROMJDTERR-COAX'-----~-D TX-RR+CAUTION: Use handling procedures necessaryfor a static sensitive component.1294 - rev.7-59

SSI78Q8392Ethernet Coaxial TransceiverFUNCTIONAL DESCRIPTIONThe SSI 7808392 incorporates six basic functions ofthe Ethernet Transceiver, including receiving,transmitting, collision signaling, collision detection,jabber timing, and the heartbeat function. Refer toFigure 1 for a general system block diagram.RECEIVER FUNCTIONSThe receiver senses signals through the RXI input,which minimizes reflections on the transmission mediausing a low capacitance, high resistance input bufferamplifier. The CDS ground input attaches directly tothe input buffer from the coaxial shield to eliminateground loop noise.In addition to the input buffer, the receiver data pathconsists of an equalizer, data slicer, receiver squelchcircuitry, and an output line driver.The equalizer improves the jitter margin; the data slicerrestores equalized received signals to fast transitionsignals with binary levels to drive the receiver linedriver; and the receiver line driver drives the AU I cablethrough an isolation transformer that connects to theAUI interface.Noise on the transmission media is rejected by thereceiver squelch circuitry, which determines valid datavia two criteria: DC level and pulse width. The DCvoltage level is detected and compared to a set level inthe receiver comparator circuit. The pulse width mustbe greater than 20 ns and repeat at valid data rates. Itis detected using a pulse detector operating like aretriggerable one-shot that resets at approximately twosignal bit times. The pulse width detector disablesthe receiver line driver at the end of a transmission(Figure 3).TRANSMITTER FUNCTIONSThe transmitter data path consists of a transmit inputbuffer, pulse-shaping network (ramp generator),transmit squelch circuitry, a transmit driver, andtransmit output line driver.The self-biasing transmit input buffer receives datathrough an isolation transformer and translates the AUIdifferential analog Signal to digital Signals suitable fordriving the pulse shaping network. The pulse shapingnetwork gives equal rise and fall times to the transmitdriver, which uses a high impedance current sourceoutputto drive the transmission media. The capacitanceof the transmit driver is isolated from the transmissionmedia by an external diode with a low capacitancenode. The shield of the transmission media serves asthe ground return for the transmitter function.A transmit squelch circuit, which consists of a pulsethreshold detector, a pulse width detector, and a pulseduration timer, is used to suppress noise, as well ascrosstalk on the AU I cable. The squelch circu itry disablesthe transmit driver if the signal at TX+ or TX- is smallerthan the pulse threshold. Pulse noise is rejected by apulse width detector that passes only pulses withdurations greater than 20 ns. The pulse duration timerdisables the transmit driver if no pulses are received fortwo-bit periods following valid pulses. At the end of atransmission, the pulse duration timer disables thetransmitter and triggers the blanking timer, used toblock "dribble" bits.COLLISION SIGNALINGWhen collision signaling is enabled, a 1 O-MHz signal issent to the CD± pins through an isolation transformerto the Manchester encoder/decoder. When the functionis disabled, this output goes to a zero differential state.The 10-MHz output from the CD pins indicates acollision on the transmission media, a heartbeat function,or that the transmitter is in jabber mode.COLLISION DETECTIONA collision occurs when two or more transmitterssimultaneously access the transmission media. Acollision is detected by comparing the DC level of thetransmission media to a colliSion threshold. The receivedsignal at RXI is buffered and sent through a low passfilter, then compared in the collision threshold circuit. Ifthe DC level exceeds the collision threshold, the 10-MHz oscillator and CD outputs are enabled.7-60

SSI78Q8392Ethernet Coaxial TransceiverJABBER FUNCTIONWhen valid data is transmitted, the jabber timer isstarted. If there is valid data for more than 20 sec, alatch is set which disables the transmitter and enablesthe 10-MHz output on the CO pins. The latch is resetwithin 0.5 seconds after the valid data is removed fromthe transmitter input (TX±). This action resets thejabber timer and disables the 1 O-MHz oscillator and CDoutput. The TX± inputs must remain inactive during theO.S-second reset period.HEARTBEAT FUNCTIONThe 10-MHz oscillator and CD outputs are enabled forabout 1 Jls at approximately 1.1 Jls after the end of eachtransmissions. The heartbeat signal tells the OTE thatthe circuit is functioning. This is implemented by startingthe heartbeat timer when the valid data signal indicatesthe end of a transmission.DATA MEDIAVEE1!VEE5 VEE13 VEERECEIVER OUTPUTLINE DRIVERIFIGURE 1: SSI 78Q8392 General System Block Diagram7-61

SSI78Q8392Ethernet Coaxial TransceiverPIN DESCRIPTIONNAME TYPE DESCRIPTIONCD+*/CD- 0 Collision Output. Balanced differential line driver outputs from the collisiondetect circuitry. The 10 MHz signal from the internal oscillator is transferred tothese outputs in the event of collision, excessive transmission (jabber), orduring CD Heartbeat condition. These outputs are open emitters; pulldownresistors to VEE are required. When operating into a 78.0 transmission line,these resistors should be 510.0. In Cheapernet applications, where the 78.0drop cable is not used, higher resistor values (up to 1.5k) may be usedto savepower.RX+*/RX- 0 Receive Output. Balanced differential line driver outputs from the Receiver.These outputs also require 510.0 pulldown resistors.TX+*/TX- I Transmit Input. Balanced differential line receiver inputs to the Transmitter.The common mode voltage for these inputs is determined internally and mustnot be externally established. Signals meeting Transmitter squelch requirementsare waveshaped and output at TXO.HBE I Heartbeat Enable. This input enables CD Heartbeat when grounded, disablesit when connected to VEE.RR+/RR- I External Resistor. A fixed 1 k 1 % resistor connected between these pinsestablishes internal operating currents.RXI I Receive Input. Connects directly to the coaxial cable. Signals meetingReceiver squelch requirements are equalized for inter-symbol distortion,amplified, and output at RX+ and RX- pin.TXO 0 Transmit Output. Connects either directly (Cheapernet) or via an isolationdiode (Ethernet) to the coaxial cable.--CDS I Collision Detect Sense. Ground sense connection for the collision detectcircuit. This pin should be connected separately to the shield to avoid grounddrops from altering the receive mode collision threshold.GND - Positive Supply Pin. A 0.1 IlF ceramic de-coupling capacitor must be connectedacross GND and VEE as close to the device as possible.VEE - Negative Supply Pins. These pins should be connected to a large metal framearea on the PC board to handle heat dissipation.*IEEE names for CD± = CI±, RX± = DI±, TX± = DO±7-62

SSI78Q8392Ethernet Coaxial TransceiverELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSAbsolute maximum ratings indicate limits beyond which permanent damage may occu r. Continuous operationat these limits is not recommended; operations should be limited to those conditions specified underrecommended operating characteristics.PARAMETERRATINGSupply Voltage -12VInput Voltage o to -12V~~-~.--Storage Temperature -65 to 150°CSoldering (Reflow or Dip)300°C for 10 secPackage power dissipation 2.5 watts @ 25°CDC OPERATING CHARACTERISTICSO°C < T (ambient) < +70°C, VEE = -9V + 5%--PARAMETER CONDITION MIN NOM MAX UNITIEE1 Supply current out of -60 -85 mAV EE pin - non-transmittingIEE2 Supply current out of -120 -140 rnAV EE pin - transmittingI RX1Receive input bias See Note 3 -2 +25 J.1Acurrent (RXI)I TOeI TACTransmit output dccurrent level (TXO)Transmit output accurrent level (TXO)See Note 4 37 41 45 mA----- --See Notes 4 & 5 ±28 ITOe mAV eDCollision threshold See Note 10 -1.581 -1.52 -1.492 V(Receive mode)V aDDifferential output voltage See Notes 3 & 8 ±550 ±1200 mV(RX±, CD±)--Vae Common mode output See Note 3,7 & 8 -2.5 -2.0 -1.5 Vvoltage (RX±, CD±)V aBDifferential output voltageimbalance (RX±, CD±)--- --See Notes 3,8 & 9 ±40 mVV TSTransmitter squelch -300 -250 -175 mVthreshold (TX±)C xInput capacitance (RXI) 1.2- ------------pFRRXIShunt resistance - See Note 3 1 MQnon-transmitting (RXI)---~c---------R TxaShunt resistance - See Notes 4 & 6 200 kQtransmitting (TXO)I7-63

SSI78Q8392Ethernet Coaxial TransceiverDC OPERATING CHARACTERISTICS (continued)NOTES1. Currents into device pins are positive, currentsout of device pins are negative. If not specified,voltages are referenced to ground.2. All typicals are for VEE = -9V, Ta = 25°C.3. 0 > VEE> -9.5V.4. The voltage on TXO is -4V < V(TXO) < O.OV.5. The AC current measurement is referenced tothe DC current level.6. The shunt resistance does not degrade theITAC current if five transmitters are simultaneouslydriving a 500-terminated coax cable.7. Operating or idle state.8. Test load as shown in Figure 2.9. Device measurement taken in idle state.10. This threshold can be determined by monitoringthe CD± output with a DC level in RX/.GND+¢voeRX+or -eo+510±5%~I""'?tETHERNET50 f.lH±1%XeVR;s: 73Q±1%VEERXorteD-510Q±5%VEErVOSI V:D -VCOMFIGURE 2: Test Load for CD± or RX±7-64

----~ 1---.SSI78Q8392Ethernet Coaxial TransceiverAC OPERATING CHARACTERISTICSO°C < T(ambient) < +70°C, VEE = 9V ± 5%PARAMETERCONDITIONMIN NOM MAX UNITt RoNtRdReceiver startup delay(RXI to RX±)Receiver propagation delay(RXI to RX±)4 5 bits------- 1---15 50 nstRrtRtt RJt TSTDifferential outputs rise time(RX±, CD±)Differential outputs fall time(RX±, CD±)Receiver & cable total jitterTransmitter startup delay(TX±to TXO)4 ns1-------.4 ns--r--2 4 ns- ---1 2 bitst TdTransmitter propagationdelay (TX± to TXO)25 50 nst TrTransmitter rise time -10% to 90% (TXO)tTt Transmitter fall time -90% to 10% (TXO)tTMtTst ToNt Tr and tTt mismatchTransmitter skew (TXO)Transmit turn-on pulsewidth at V TS (TX±)20 25 30 ns--20 25 30 ns-~--0.5 ns±0.5 ns--~--------t--------.~-20 nstTOFFtCONtCOFFtCDtcptHaNTransmit turn-off pulsewidth at V TS (TX±)Collision turn-on delayCollision turn-off delayCollision frequency (CD±)Collision pulse width (CD±)CD Heartbeat delay(TX± to CD±)--~-~ --~250 ns----.~-7 bits'------20 bits8.5 11.5 MHz---~---.-35 70 ns.. __ .- -----t-----------0.6 1.6 IJ,SItHWCD Heartbeat duration(CD±)0.5 1.0 1.5 IJ,StJAtJRJabber activation delay(TX± to TXO and CD±)Jabber reset unjab time(TX± to TXO and CD±)20 75 ms250 500 750 ms-7-65

SSI78Q8392Ethernet Coaxial TransceiverELECTRICAL SPECIFICATIONS (continued)TRANSMIT SPECIFICATIONSThe first bit transmitted from TXO may have data andphase violations. The second through last bit reproducethe TX± signal with less than or equal to specified jitter.There is no logical signal inversion between Tx± andTXO output. A low level from TX+ to TX- results in morecurrent flowing from the coaxial cable into the TXO pin.At the end oftransmission, when the transmitter changesfrom the enabled state to the idle state, no spuriouspulses are generated, i.e., the transition on TXOproceeds monotonically to zero current.RECEIVE SPECIFICATIONSThe first bit sent from RX± may have data and phaseviolations. The second through last bit reproduce thereceived signal with less than or equal to specifiedjitter.There is no logical signal inversion between the RXIinput and the RX± output. A high level at RXI producesa positive differential voltage from RX+ to RX-.RXI ---r-~-l/RX± ------.'01st BIT1FIGURE 3: Receiver TimingTX±------------------~~:NHITXO~------------------~--__\-I r'Tdc::--_...J190%T;=t;10%-I~FIGURE 4: Transmitter Timing7-66

SSI78Q8392Ethernet Coaxial TransceiverINPUT STEPFUNCTIONRXISS178Q8392COLLISIONDETECTORco±OUTPUTRCNETWORKSIMULATES WORST CASECABLE STEP RESPONSERXIVco (MAX)VCO(MIN)co± _______---,FIGURE 5: Collision TimingT~~ _____________________ ___I~ ·1co± __________ --,FIGURE 6: Heartbeat TimingIT~---i 111111111111111111111111---1 -----I~ ~A·I I~TXO_~~~~~~ ________________ ~ __ _...CD±-------tllllllllllllllllllllllllllllllllill r----FIGURE 7: Jabber Timing7-67

SSI78Q8392Ethernet Coaxial TransceiverI ~~K- - - --,INPUT SIGNAL WITH 1 1 RXI30 NSEC RISE AND -~---'FALL TIMES1 fT\ C = 36 pF 1L---.J::----lSSI78Q8392ETRECEIVERRX±OUTPUTRC NETWORK SIMULATESWORST CASE CABLE JITIERI .... I1 1 1Input jitter

551 78Q8392Ethernet Coaxial TransceiverPACKAGE PIN DESIGNATIONS(Top View)CO+ 16 CDSco- 2 15 TXOAX+ 3 14 AXIVEE 4 13 VEEVEE 5 12 AA-AX- 6 11 AA+TX+ 7 10 GNDTX- 8 9 HBE16-Pin DIP+ + rn 0x 6 0 0 x

Notes:7-70

DESCRIPTIONThe SSI 7S0S392L Ethernet Transceiver is a lowpower, BiCMOS coax line transmitter/receiver. Thedevice includes analog transmit and receive buffers, a10 MHz on-board oscillator, timing logic for jabber andheartbeat functions, output drivers and bandgapreference, in addition to a current reference and collisiondetector.This transceiver provides the interface between thesingle-ended coaxial cable signals and the Manchesterencodeddifferential logic signals. Primary functionalblocks include the receiver, transmitter, collisiondetection and jabber timer. This IC may be used ineither internal or external MAU environments.The SSI7S0S392L is available in 16-pin plastic, 24-pinSOL and 2S-pin PLCC packages.SSI 78Q8392LLow Power EthernetCoaxial Transceiverttfikk1h¥ltfft,'""ji['J"December 1994FEATURES• very low power consumption• Compliant with Ethernet II, IEEE S02.310Base5 and 10Base2 (Cheapernet)• Integrates all transceiver functions exceptsignal and power isolation• Innovative design minimizes external componentscount and power consumption• Jabber timer function integrated on chip• Externally selectable CEO heartbeat allowsoperation with IEEE 802.3 compatible repeaters• Squelch circuitry at all inputs rejects noiseSSI78Q8392L CONNECTION DIAGRAMPIN DIAGRAM5100±5%x4COLLISIONUSIGNALTODTEMTATUDTETX+VEEVEEVEECDSTXORXIGNDHBEOATAFROMJOlE RR- COAXco+ 16 COSco- 2 15 lXORX+ 3 14 RXIVEE 4 13 VEEVEE 5 12 RR-RX- 6 11 RR+TX+ 7 10 GNOlX- 8 9 HBE16-Pin DIPTX-RR+-9VICAUTION: Use handling procedures necessaryfor a static sensitive component.1294 7-71

SSI 78Q8392LLow Power EthernetCoaxial TransceiverDATA MEDIAVEE~VEE5 VEE13 VEESLICER>--....----------DRECEIVER OUTPUTLINE DRIVER~ ::+L----,-----J--lJSIGNAL PRESENT_________ IFIGURE 1: SSI 78Q8392L General System Block DiagramAdvance Information: IndiCates a product still in the design cycle, and any specifications are based on design goals only. Do not use forfinal design.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1994 Silicon Systems, Inc. 7-72 1294

DESCRIPTIONThe SSI 7808377 is a highly integrated Ethernet IC for usein Ethemet Network Interlace Cards (NICs) in the ISA/Plugand Play (PnP) environment. It contains a full-duplex MediaAccess Controller (MAC), a 1 0 MbiVs Manchester encoder/decoder (EN DEC) , a 1 OBase Ttransceiver, ISA-bus interlaceand an Attachment Untt Interface (AU I). The only externalcomponents required to build an Ethernet adapter cardwith the 7808377 are buffer memory and a few passivecomponents. In full duplex operation, transmission linethroughput doubles to the theoretical 20 Mbit/s. In thismode, the collision detection, SOE generation andcarrier deference are disabled.The 7808377 has an integrated ISA-bus interface thatphysically connects to the bus without any additionalglue logiC. The 7808377 is defined with "jumperless"configuration in mind. The configuration information isstored in serial EEPROM.The 7808377 fully supports the PnP ISA specification.The PnP logic can also be bypassed through a bit inthe EEPROM. When the PnP logiC is bypassed, the7808377 will power up active after loading thenecessary configuration information from the serialEEPROM.The popular microwire (4-wire) interface is supportedby the 7808377 to connect to serial EEPROM, whichcontains configuration information such as I/O Baseaddress, Boot Device address, IRO selection, MACaddress, etc. Reading of essential configurationinformation like the I/O Base address and Boot Deviceaddress is done automatically by the 7808377. Thedriver software is then responsible to read the rest ofthe information and program the 7808377 registerswith the appropriate values read.The 7808377 allows for a diskless station to boot fromthe installed boot device. It supports 8 memory baseaddresses for the boot device with 16 Kbytes memorysize and 4 memory base addresses with 32 Kbytessize. The boot feature can also be disabled through abit in the serial EEPROM. Both read-only and readwrite(e.g., flash) memory are supported by the7808377. Furthermore, accidental write to the flashcan be prevented through a write protect register bit.The 7808377 only provides a chip select pin to theboot device and the address, data and control Signalsof the boot device connect directly to the appropriateISA bus.551 78Q837710BaseT Ethernet Combofor Plug and Play""milt·UIliiit.h'November 1994FEATURESHighly integrated Ethernet combo with Plugand Play (PnP) interfaceCompliant with plug and play ISA SpecificationVersion 1.0aIncludes complete Ethernet circuitry for10BaseT: Buffer manager, MAC/OLC, ENOEC,10BaseT transceiver, AUI, and powermanagementRegister-compatible with SSI 7808373"Glueless" and "jumperless" connection to ISAbusSupports both PnP and non-Pn P environmentIntegrated 16 mA data bus buffer withstaggering for reduced noise and groundbounceSerial EEPROM support via microwire (4-wire)interfaceBoot device (either read-only or read-writememory) support. 8 Boot device locations with16 or 32 Kbytes size8 interrupt lines selection. Supports edge andlevel-sensitive interrupts. Tri-state implementationallows sharing of interrupts for bothmodesProgrammable full-duplex operation in twistedpairmodeLow power design128-pin OFP with single 5V supplyI11947-73

SSI78Q837710BaseT Ethernet Combo forPlug and PlayBLOCK DIAGRAMISA BUS BUFFER MACINTERFACE MANAGER (DLC)rPnPl~ENDECPOWER MANAGEMENT10BASE-TTRANSCEIVERAUIFILTER,ISOLATIONISOLATIONCOAXTRANSCEIVERTWISTEDPAIRCOAXISA BUSTarget Specification: The farget specification is intended as an initial disclosure of specification goals for the product. The specificationsare based on design goals, subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufactureunless agreed to in writing.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1994 Silicon Systems, Inc. 7-74 1194

5S178Q8378Enhanced PCMCIAEthernet DeviceDESCRIPTIONThe SSI 7808378 is a highly integrated Ethernet ICfor use in PCMCIA (Personal Computer Memory CardInternational Association) applications with Multi­Function card capability, especially Ethernet/Modemcombinations. It contains a full-duplex Media AccessController (MAC), a 10 Mbit/s Manchester encoder/decoder (ENDEC), a 10BaseT transceiver, PCMCIAbus interface and an Attachment Unit Interface (AUI),and can operate from either a 5-volt or 3.3-volt supply.The only external components required to build aPCMCIA Ethernet adapter card with the 7808378 arebuffer memory and a few passive components. In fullduplex operation, transmission line throughput doublesto the theoretical 20 Mbit/s. In this mode, the collisiondetection, SOE generation and carrier deference aredisabled.To allow multi-function operation, two sets of FunctionConfiguration Registers (FCR - formerly called CardConfiguration Registers or CCR) are provided so thateach function can be configured independently of theother. The chip includes the function of mapping anddecoding the I/O range for the ethernet (7808373)registers and the modem port. The 7808378 is alsocapable of handling multiple interrupts from twosources by saving the second interrupt and generatingit later according to the PCMCIA Multifunction spec. Asimple modem interface is provided on-chip toeliminate the need for external glue logic whendesigning an Ethernet/Modem multifunction PCMCIAcard. The 7808378 interfaces directly to a UART.FEATURESDecember 1994Highly integrated PCMCIA EtHernet andmodem port comboPCMCIA Multifunction spec compliant. Builtinmodem port interface to external UARTIncludes all the functional blocks of 78Q8373:Buffer manager, MAC/OLC, ENOEC, 10BaseTtransceiver, AUI, power management and 3.3Vor 5V operationRegister-compatible with SSI78Q8373Interface to parallel EEPROM/Flash memory forPCMCIA CIS (Card Information Structure)Programmable full-duplex operation in twistedpairmode1/0 registers are accessible through normal1/0 cycle as well as common memory cycleLow power design100-Lead TQFPIThe target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.12947-75

551 78Q8378Enhanced PCMCIAEthernet DeviceBLOCK DIAGRAMMulti-FunctionPCMCIAInterfaceSRAMInterfaceBufferManagerMAC(DLC)ENDEC10BaseTTransceiverFILTER,ISOLATIONTWISTEDPAIRPower ManagementAUIISOLATIONCOAXTRANSCEIVERPCMCIA BUSMODEM INTERFACECOAXTarget Specification: The .target specification is intended as an initial disclosure of specification goals for the product. The specificationsare based on design goals, subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufactureunless agreed to in writing.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1994 Silicon Systems, Inc. 7-76 1294

DESCRIPTIONThe SSI 7802250 is a high-speed line transceiverintegrated circuit intended for use in AsynchronousTransfer Mode (ATM) applications. It is used at theinterface to Category 5 Unshielded Twisted-Pair (UTP)cabling and is connected to the line via isolationtransformers. Interface to digital framer circuits isaccomplished via 8-bit parallel CMOS I/O running at19.44 Mbitls.The IC provides full transmit and receive line interfacefunctions with minimum external components required.The receiver provides near-end crosstalk cancellation,adaptive equalization for accurate clock and datarecovery, while the transmitter includes on-chip pulseshaping. The 7802250 is built in a SiCMOS technologyfor highest performance and low power operation.SSI78Q2250155 Mbit/s ATMLine Transceiveri"'~t§e·iijlit!i'[·'"October 1994FEATURES• 155.52 Mbit/s interface for Category 5Unshielded Twisted Pair (UTP) cable••••••••Compliant with ATM PMD Interface Spec for155.52 Mbitls over Twisted Pair CableParallel CMOS logic interface at 19.44 Mbit/sECl interfaces for connection to fiber opticreceive and transmit modulesOn-chip pulse shapingAutomatiC gainAdaptive equalizationPower down modeAdvanced BiCMOS processingICAUTION: Use handling procedures necessaryfor a static sensitive component.The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.10947-77

SSI78Q2250155 Mbit/s ATMLine TransceiverFUNCTIONAL DESCRIPTIONThe transmit section of this IC contains all of thenecessary circuitry to convert 8-bit parallel data into asingle 155.52 MbiVs serial data signal and drive theCategory 5 UTP cable. It generates the 155.52 MHzusing a fixed PLL synthesizer locked to either a local19.44 MHz crystal oscillator (in a hub application), orthe 155.52 MbiVs clock recovered in the receiver (whenused in a host). Data enters the chip via TxDatO-7 andare converted to serial by a parallel-to-serial converter.The single 155.52 Mbitls data line is then converted tothe 1 volt differential signal required at the line interface.Connection to the UTP cable is through a transformer.On the receive side, data signal enters the chip via theUTP interface after it has gone through up to 100meters of cable. The connection to the UTP cable isthrough a transformer. Once on-chip, the signal goesthrough both an automatic gain circuit and an adaptiveequalizer. These circuits look forthe amount dispersionand attenuation caused by the cable and restore thereceived pulses to square waves. The amount of gainand equalization applied to the pulses varies with thedetected attenuation and dispersion and therefore withthe length of the cable. The clock signal is extractedfrom the equalized data signal using a Costas loopPLL. The recovered clock is used to retime the datasignal and finally it is converted to 8-bit parallel data at19.44 Mbitls in a serial to parallel converter.As noted, the transmitter uses either the local crystaloscillator or the recovered clock from the receiver.When the circuit is in a host, the transmit clock is alwaysderived from the local crystal oscillator. When it is in ahub, the transmit clock is derived from the recoveredclock when the receive PLL is locked. When it is' not,the transmit clock PLL switches its input to the crystaloscillator. In this way, the transmitter will still operateat the right frequency even if the receiver is not seeinga correct signal. The receive clock RxClk used to clockout the data from the receive side of the chip is normallyderived from the receive PLL, when it is locked. Whenthe PLL is unlocked, the RxClk is switched to the crystaloscillator so that it will be at the right frequency. Thedata leaving the chip from RxDatO-7 will still be timedby RxClk but will not be valid.The 78Q2250 uses the local crystal oscillator togenerate bias voltages for setting the various timedependent circuits on the chip. These include thecontrolled rise-time for the transmit pulses and thecenter frequencies of the two on-chip voltage-controlledoscillators. This means that the narrow band PLLcircuits won't require frequency discrimination circuitsto aid acquisition. It also means the chip will not requirethe use of the external resistor used in other ICsrequiring preCision timing, nor will it be necessary totrim the part.Target Specification: The target specification is intended as an initial disclosure of specification goal.s f~r the prod~ct. The specificationsare based on design goals, subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufactureunless agreed to in writing.No responsibility is assumed by Silicon Systems for use of this product nor for any i!1fringements of patent~ .and trademarks .~r other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of SIlicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Acco~dingly, the reader is cautioned to verify that the datasheet is current before placing orders. .Silicon Systems, Inc., 14351 Myford Road, Tustin. CA 92680-7022 (714) 573-6000, FAX (714) 573-69141094 7-78 ©1994 Silicon Systems. Inc.

Section 8PROGRAMMABLEELECTRONIC FILTERSI8

8-0

SSI 32F8001/8002Low-Power ProgrammableElectron ic FilterDecember 1994DESCRIPTIONThe 551 32F8001/8002 Programmable ElectronicFilter provides an electronically controlled low-passfilter with a separate differentiated low-pass output. Aseven-pole, low-pass filter is provided along with asingle-pole, single-zero differentiator. Both outputshave matched delays. The delay matching isunaffected by any amou nt of programmed equalizationor bandwidth. This programability combined with lowgroup delay variation make the 551 32F8001/8002idealforuse in constant density recording applications.Pulse slimming equalization is accomplished by a twopole,low-pass with a two-pole, high-pass feedforward section to provide complimentary real axiszeros. A variable attenuator is used to program thezero locations.The 551 32F8001/8002 programmable equalizationand bandwidth characteristics can be controlled byexternal DACs. Fixed characteristics are easilyaccomplished with three external resistors, in additionequalization can be switched in or out by a logic signal.The 551 32F8001 18002 requires only a +5V supply andare available in 16-lead SON and SOL packages.FEATURESIdeal for multi-rate systems applicationsProgrammable filter cutoff frequency (/c = 9to 27 MHz, 32F8001 ; Ic = 6 to 18 MHz, 32F8002)Programmable pulse slimming equalization(0 to 13.5 dB boost at the filter cutofffrequency)Matched normal and differentiated low-passoutputsDifferential filter inputs and outputs±12% cutoff frequency accuracy±2% maximum group delay variation from0.2 Ic to IcTotal harmonic distortion less than 1%No external filter components required+5V only operation16-Lead SON and SOL packagePin compatible with SSI 32F8011BLOCK DIAGRAMPIN DIAGRAMVIN+VIN-VO_NORM+VO_NORM-N/CVO_NORM­VO_DIFF+VO_DIFF­VO_DIFF+VO_DIFF-VO_NORM+VCCVIN-PWRONVPTATN/CIVBPLr~~~~~~~I FP r1--~2f"-;:::::-::-I1----'VFPFBSTVPTATPWRONVIN+IFPVBPVFPFBSTGND16-Lead SOL, SON1294 - rev. 8-1CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI 32F8001/8002Low-Power ProgrammableElectronic FilterFUNCTIONAL DESCRIPTIONThe 551 32F8001/8002 is a high performanceprogrammable electronic filter. It features a 7-pole0.05° equiripple linear phase filter with matched normaland differentiated outputs.CUTOFF FREQUENCY PROGRAMMINGThe 551 32F8001 programmable electronic filter canbe set to a filter cutoff frequency from 9 to 27 M Hz withno boost. The 551 32F8002 can set the cutoff frequencyfrom 6 to 18 MHz with no boost.Cutoff frequency programming can be establishedusing either a current source fed into pin IFP whoseoutput current is proportional to the 551 32F8001 18002output reference voltage VPTAT, or by means of anexternal resistor tied from the output voltage referencepin V PTA no pin VFP. The former method is optimizedusing the 551 3204661 Time Base Generator, sincethe current source into pin IFP is available at the OACF output of the 5513204661. Furthermore, the voltagereference input is supplied to pin VR3 of the5513204661 by the referencevoltagefromthe VPTATpin of the S5132F8001/8002. This reference voltage isinternally generated by a band-gap circuit in conjunctionwith a temperature varying reference to create a voltagewhich is proportional to absolute temperature.The VPTAT voltage will compensate for internaltemperature variation of the Ic and boost circuits.The cutoff frequency, determined by the -3 dB pointrelative to a very low frequency value « 10 kHz), isrelated to the current IVFP injected into pin IFP by thefollowing formulas.Ic (ideal, in MHz)32F8001 = 45.0· IFP = 45.0 • IVFP • 1.8/vPTAT32F8002 = 30.0· IFP = 30.0 • IVFp· 1.8/vPTATwhere IFP and IVFP are in mA, 0.2 < IFP < 0.6 rnA,VPTAT is in volts, and Ta = 25°C.If a current source is used to inject current into pin IFP,pin VFP should be left -open.If the 551 32F8001/8002 cutoff frequency is set usingvoltage VPTATto bias upa resistor tied to pin VFP, thecutoff frequency is related to the resistor value by thefollowing formulas.Ic (ideal, in MHz)32F8001 = 45.0· IFP = 45.0 • 1.8/(3 • Rx)32F8002 = 30.0· IFP = 30.0 • 1.8/(3· Rx)Rx in !illIf pin VFP is used to program cutoff frequency, pin IFPshould be left open.MAGNITUDE EQUALIZATION PROGRAMMINGThe magnitude equalization, measured in dB, is theamount of high frequency peaking at the cutoff frequencyrelative to the original-3 dB point. For example, when12 dB boost is applied, the magnitude response peaksup 9 dB above the DC gain.The amplitude of the input signal at frequencies nearthe cutoff frequency can be increased using this feature.Applying an external voltage to pin VBP which isproportional to reference output voltage VPTAT(provided by the VPTAT pin) will setthe amount ofboost. A fixed amount of boost can be set by anexternal resistor divider network connected from pinVBPto pins VPTATandGND. No boost is applied ifpinFB5T, frequency boost enable, is at a low logic level.The amount of boost FB at the cutoff frequency Fc isrelated to the voltage VBP by the formulaFB (ideal, in dB) = 20 log1o[3.73(VBP/VPTAT)+1],where 0 < VBP < VPT A T.POWER ON I OFFThe 551 32F8001/8002 supports a power down modefor minimal idle mode power dissipation. When PWRONis pulled up to logic 1, the device is in normal operationmode. When PWRON is pulled down to logic 0, or leftopen, the device is in the power down mode.8-2

SSI 32F8001/8002Low-Power ProgrammableElectronic FilterPIN DESCRIPTIONNAMEVIN+, VIN-TYPEVO_NORM+, 0VO_NORM-VO_DIFF+, 0VO_DIFF-IFPIVFPVBPFBSTPWRONVPTAT 0vee 0GNDIIIIIIDESCRIPTIONDifferential Signal Inputs. The input signals must be AC coupled to these pins.Differential Normal Outputs. The output signals must be Ae coupled.Differential Differentiated Outputs. For minimum time skew, these outputsshould be AC coupled.Frequency Program Input. The filter cutoff frequency fc, is set by an externalcurrent IFP, injected into this pin.IFP must be proportional to voltage VPTAT.This current can be set with an external current generator such as a DAC. VFPshould be left open when using this pin.Frequency Program Input. The filter cutoff frequency can be set by programminga current through a resistor from VPTAT to this pin. IFP should be leftopen when using this pin.Frequency Boost Program Input. The high frequency boost is set by anexternal voltage applied to this pin. VBP must be proportional to voltageVPTAT. A fixed amount of boost can be set by an external resistor dividernetwork connected from VBP to VPTAT and GND. No boost is applied if theFBST pin is grounded, or at logic low.Frequency Boost. A high logic level or open enables the frequency boostcircuitry. A low input disables this function.Power On. A high logic level enables the chip. A low level or open pin puts thechip in a low power state.PTAT Reference Voltage. This pin outputs a reference voltage which isproportional to absolute temperature (PTAT). VBP, VFP or IFP must bereferenced to this pin for proper operation.+5 Volt Supply.GroundELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may damage the device.IPARAMETERStorage TemperatureJunction Operating Temperature, TjSupply Voltage, veeVoltage Applied to InputsRATINGS-65°e to +150 o e+130 o e-O.5V to 7V-O.5V to vee8-3

SSI32FS001/S002Low-Power ProgrammableElectronic FilterELECTRICAL SPECIFICATIONS (continued)RECOMMENDED OPERATING CONDITIONSPARAMETERRATINGSSupply voltage vcc 4.50V < VCC < 5.50VAmbient Temperature Ta O°C < Ta < 70°CELECTRICAL CHARACTERISTICSUnless otherwise specified recommended operating conditions apply.Power Supply CharacteristicsPARAMETER CONDITIONS MIN NOMPower Supply Current ICC PWRON~O.BV 0.1Power Supply Current ICC PWRON~2V 46Power Dissipation PD PWRON ~ 2V, VCC = 5V 230PWRON ~ 2V, VCC = 5.5V 275PWRON~O.BV 0.5MAX UNIT0.5 rnA60 mA300 mW330 mW2.5 mWDC CharacteristicsHigh Level Input Voltage VIH TTL input 2Low Level Input Voltage VILHigh Level Input Current IIH VIH = 2.7VLow Level Input Current ilL VIL = O.4V -1.5VO.B V20 ~mAFilter CharacteristicsFilter Cutoff Frequency *fc 32FB001 927 MHz*(f -3 dB)jc= 45 MHZ(IVFP)mAIVFP = 0.2 to 0.6 rnA, Ta = 25°C32FB002 61BMHzjc = 30 MHz (IVFP)rnAIVFP = 0.2 to 0.6 rnA, 1a = 25°CFilter fc Accuracy FCA fC = max. -12VO_NORM Diff Gain AO F = 0.67 fc, FB = 0 dB O.BVO_DIFF Diff Gain AD F = 0.67 fc, FB = 0 dB O.BAOFrequency Boost at fc FB VBP = VPTAT fC = max. 12 13.5fc = min. 11.5 13Frequency Boost Accuracy FBA VBP/vPTAT = 1.0 Ie = max, -1.5+12 %1.2 V/V1.2AO V/V15 dB14.5 dB+1,5 dB8-4

SSI 32FS001/S002Low-Power ProgrammableElectron ic FilterFILTER CHARACTERISTICS (continued)PARAMETER CONDITIONS MIN NOM MAX UNITGroup Delay Variation TGDO jc = max., VBP =0 8001 -500 +500 psWithout BoostVPTATF = 0.2 fe to fe 8002 -750 +750 psjc = min., VBP =0 8001 -1.5 +1.5 nsVPTATF = 0.2 jc to jc 8002 -2.25 +2.25 nsGroup Delay Variation TGDO F = 0.2 jc to jc -2 2 0/0Without Boost (continued) VBP =0VPTATF = jc to 1.75 jc~=OVPTAT-4 +4 0/0Group Delay Variation TGDB jc = max, VBP = VPTAT -500 +500 pswith BoostF = 0.2 jc to jc -750 +750 psjc = min., VBP = VPTAT -1.5 +1.5 nsF = 0.2 to jc -2.25 +2.25 nsF = 0.2 je TO fe, VBP = VPTAT -2.5 +2.5 %F = fe to 1.75 fe, VBP = VPTAT -4 +4 %Filter Input Dynamic Range VIF THO = 1% max, F = 0.67 fe, VBP = OV 1 Vp-p(1000 pF across Rx)THO = 1.7% max, F = 0.67 fe, VBP = OV, 1.5 Vp-pNormal output (1000 pF across Rx)Filter Input Dynamic Range VIF THO = 3.5% max, F = 0.67 fe, VBP = OV, 1.5 vp-pDifferentiated output(1000 pF across Rx)Filter Output Dynamic RangeVOF THD = 1% max, F = 0.67 jc 1 Vp-pRLOAD ~ 1 kQ (1000 pF across Rx)Filter Diff Input Resistance RIN 3 4.3 kQFilter Input Capacitance CIN 3 pFOutput Noise Voltage EOUT BW = 100 MHz, Rs = 50n 8001 3.5 5.4 mVRmsDifferentiated Output jc = max, VBP = OV 8002 3.3 5.2 mVRmsOutput Noise Voltage EOUT BW = 100 MHz, Rs = 50n 8001 2.3 3.45 mVRmsNormal Output jc = max, VBP = OV 8002 2.1 3.15 mVRmsOutput Noise Voltage EOUT BW = 100 MHz, Rs = 50n 8001 7.7 10.75 mVRmsDifferentiated Output fe = max, VBP = VPTAT 8002 4.8 7 mVRmsOutput Noise Voltage EOUT BW = 100 MHz, Rs = 50n 8001 3.8 4.75 mVRmsNormal Output fe = max, VBP = VPTAT 8002 2.6 3.3 mVRmsI8-5

SS132F8001/S002Low-Power ProgrammableElectronic FilterELECTRICAL SPECIFICATIONS (continued)FILTER CONTROL CHARACTERISTICSPARAMETE;RFilter Output Sink Current 10-Filter Output Source Current 10+CONDITIONSFilter Output Resistance RO 10+ = 1.0 mA(Single ended)Reference Voltage VPTAT Tj = 25°CPTAT Voltage InputVFPProgramming Current IVFP Ta = 25°CRangeProgramming VoltageRangeVVBPVoltage at pin IFP V 1FP I vFP = 0 mAPower Up TimePower Down TimeIc = 9 MHzIc = 27 MHzMIN NOM MAX UNIT1 rnA2 rnA60 Q1.8 V2/3 VPTAT V0.2 0.6 mA0 VPTAT V2/3 VPTAT V1.5 f.lS1 f.lS1 f.lS8-6

551 32FS001/S002Low-Power ProgrammableElectron ic Filter10 dB/div _ ,.-I..J........I.-'--'-.L..J...J..--I..--I..-~~W+-_-+~w-\-\UU-l-l® fe = 9 MHz; 0 dB Boost \ :\-- @ fe = 9 MHz; 13 dB Boost \\-'-@ fe = 27 MHz; 0 dB Boost \--@fe=27MHz;13dBBoostl++t+----t---t---+-\++N-H100K 1M 10M 100MFIGURE 1: 32F8001 Normal Low Pass Response10 dB/div............. ~ ,~ V..-fb .,)\ r..~r~~100'" ~ ~ \. It"~ '"~ ...,~~ J. ~~ '~,~l.",ooI .... ~ ~til'" ~~ \V ~tfa" L ... L. 'C ~./ ~ ..."" \ ~./ ,," ® Ie = 9 MHz; 0 dB Boost@ Ie = 9 MHz; 13 dB Boost@ Ie ~= 27 MHz; 0 dB Boost@ Ie = 27 MHz; 13 dB Boost \,\100K 1M 10M 100M\\IFIGURE 2: 32F8001 Differentiated Low Pass Response8-7

SSI32FS001/S002Low-Power ProgrammableElectronic Filterb-~ ~1 ns/div. ® 0 dB Boost@ 13 dB Boostje = 27 MHza-~"' \ \ ,~\\o7.5 MHz/div.75MFIGURE 3: 32F8001 Group Delay Response with Ie = 27 MHz8-8

SSI32FS001/S002Low-Power ProgrammableElectron ic FilterVO_DIFF+N/CVO_NORM­VO_NORM+VCC (+5V)VIN­VIN+VBPFBSTRBP2VO_DIFF-N/CIFPVFP __ -+----1GNDRxRsp,VPTAT = 1.8V (25°C)VVFP = 2/3 (VPT AT)IVFP range: 0.2 mA to 0.6 mA@25°C(9 to 27 MHz no boost 32F8001)(6 to 18 MHz no boost 32F8002)Fixed frequency programming is accomplished as shown in the drawing above.In this case IVFP (programming current) is equivalent to VPTAT. ~3 Rxi.e., fc = 27 MHz thenIVFP = 0.6 mA @25°C Rx = 1 kQFixed boost programming is also accomplished as shown above. In this caseVVBP is set by a voltage divider, where VVBP is a fraction of VPTA T.Le.,boost = 9 dB then,VBP/vPTAT = 0.488 9 dB = 20 log [3.73 (0.488) + 1]RBP2 1-R-= (VPTAT ) =0.953BP1 ---1VBPCx = 1000 pF - Cx is needed for lower THD at lower fc.IFIGURE 4: 32F8001/8002 Applications Setup8-9

SSI32FS001/S002Low-Power ProgrammableElectron ic FilterINPUT1.31703S2 + S 1.68495 + 1.317032.95139 5.37034S2+ S 1.54203 + 2.95139 S2 + S 1.14558 + 5.37034S2 + S 1.68495 + 1.31703Normalized for roc = (21t) Ie = 1AN and AD are adjusted for unity gain (0 dB) at F = 0.67 IeDenormalize the frequency by substituting S ~ (S/21t/e)Eq for Ie = 27 MHz, S = S I [(21t)(27 x 10 6 )]FIGURE 5: 32FS001/S002 Normalized Block DiagramTABLE 1: 32FS001/S002 Frequency Boost Calculations, K = 1.31703 (10 BOOST (dB)/20 - 1)Assuming 13 dB boost forVBPVBPBoost KBoost K ---VBP = VPTAT VPTAT VPTAT1 dB 0.16 0.033 6dB 1.31 0.267VBP _ (10(FB/20»)_12 dB 0.34 0.069 7dB 1.63 0.3323 dB 0.54 0.110 8 dB 1.99 0.405VPTAT= 3.73 4dB 0.77 0.157 9 dB 2.40 0.4885 dB 1.03 0.209 10 dB 2.85 0.58011 dB 3.36 0.68312 dB 3.43 0.79913 dB 4.57 0.929VBPVBP--- Boost --- BoostVPTATVPTAT0.1 2.753 dB 0.6 10.206 dBor, 0.2 4.841 dB 0.7 11.153 dBboost in dB = 20 log [3.37 ( V~~: T ) + 1]0.3 6.523 dB 0.8 12.006 dB0.4 7.391 dB 0.9 12.784 dB0.5 9.142 dB 1.0 13.5 dB8-10

SSI32FS001/S002Low-Power ProgrammableElectron ic FilterTABLE 2: CalculationsTypical change in 1-3 dB point with boostBoost (dB) Gain@/c (dB) Gain@ peak (dB) Ipeak/lc 1-3dB/fc0 -3 0.00 no peak 1.001 -2 0.00 no peak 1.212 -1 0.00 no peak 1.513 0 0.15 0.70 1.804 1 0.99 1.05 2.045 2 2.15 1.23 2.206 3 3.41 1.33 2.337 4 4.68 1.38 2.438 5 5.94 1.43 2.519 6 7.18 1.46 2.5910 7 8.40 1.48 2.6611 8 9.59 1.51 2.7312 9 10.77 1.51 2.8013 10 11.92 1.53 2.8714 11 13.06 1.53 2.93Notes: 1. Ic is the original programmed cutoff frequency with no boost2. 1-3 dB is the new -3 dB value with boost implemented3. Ipeak is the frequency where the amplitude reaches its maximumvalue with boost implementedLe., Ic = 9 MHz when boost = 0 dBif boost is programmed to 5 dB then1-3 dB = 19.8 MHzIpeak = 11.07 MHzI8-11

SSI32FS001/S002Low-Power ProgrammableElectronic FilterPACKAGE PIN DESIGNATIONS(Top View)N/CVO_NORM-VO_NORM+VCCVIN-VIN+VBPFBSTVO_DIFF+VO_DIFF-PWRONVPTATN/CIFPVFPGNDTHERMAL CHARACTERISTICS: Sja16-Lead SON (150 mil)16-Lead SOL (300 mil)16-Lead SON, SOLCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONSSI32F800116-Lead SOL16-Lead SONSSI32F800216-Lead SOL16-Lead SONORDER NO.32F8001-CL32F8001-CN32F8002-CL32F8002-CNPKG.MARK32F8001-CL32F8001-CN32F8002-CL32F8002-CNNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1992 Silicon Systems, Inc.Protected by the following patents:(5,063,309) (710,512) (823,067) 8-121294 - rev.

SSI32F8003Low-Power ProgrammableElectronic FilterOctober 1994DESCRIPTIONThe SSI 32F8003 Programmable Electronic Filterprovides an electronically controlled low-pass filterwith a separate differentiated low-pass output. Aseven-pole, low-pass filter is provided along with asingle-pole, single-zero differentiator. Both outputshave matched delays. The delay matching isunaffected by any amount of programmed equalizationor bandwidth. This programability combined with lowgroup delay variation makes the SSI32F8003 ideal foruse in constant density recording applications. PulseSlimming equalization is accomplished by a two-pole,low-pass with a two-pole, high-pass feed forwardsection to provide complimentary real axis zeros. Avariable attenuator is used to program the zerolocations.The SSI 32F8003 programmable equalization andbandwidth characteristics can be controlled byexternal DACs. Fixed characteristics are easilyaccomplished with three external resistors, in additionequalization can be switched in or out by a logic Signal.The SSI 32F8003 requires only a +5V supply and isavailable in 16-lead SON and SOL packages.FEATURESIdeal for multi-rate systems applicationsProgrammable filter cutoff frequency Ic = 4 to13 MHzProgrammable pulse slimming equalization(0 to 13.5 dB boost at the filter cutoff frequency)Matched normal and differentiated low-passoutputsDifferential filter inputs and outputs±13% cutoff frequency accuracy±2% maximum group delay variation from0.2 Ic to IcTotal harmonic distortion less than 1%No external filter components required+5V only operation16-lead SON and SOL packagePin compatible with S81 32F8011BLOCK DIAGRAMPIN DIAGRAMVIN+VO_NORM+N/CVO_DIFF+VIN- u-......,~'-:--.,..,._-'VO_NORM-VO_NORM-VO_DIFF-VO_DIFF+VO_DIFF-VO_NORM+vccVIN-PWRONVPTATN/CIVIN+IFPVBPUP~~~~----~IFPVFP c;:r---'-'-~~=:JFBSTVPTATPWRONVBPVFPFBSTGND16·Lead SOL, SON1094 - rev. 8-13CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI32F8003Low-Power ProgrammableElectronic FilterFUNCTIONAL DESCRIPTIONThe SSI32FB003 is a high performance programmableelectronic filter. It features a 7-pole 0.05° equiripplelinear phase filterwith matched normal and differentiatedoutputs.CUTOFF FREQUENCY PROGRAMMINGThe SSI 32FB003 programmable electronic filter canbe set to a filter cutoff frequency from 4 to 13 MHz withno boost.Cutoff frequency programming can be establishedusing either a current source fed into pin IFP whoseoutput current is proportional to the SSI 32FB003output reference voltage VPTAT, or by means of anexternal resistor tied from the output voltage referencepin V PTA Tto pin VFP. The former method is optimizedusing the SSI 3204661 Time Base Generator, sincethe current source into pin IFP is available at the OACF output of the SS13204661. Furthermore, the voltagereference input is supplied to pin VR3 of theSSI 3204661 by the referencevoltagefromthe VPTATpin of the SSI 32FB003. This reference voltage isinternally generated by a band-gap circuit in conjunctionwith a temperature varying reference to create a voltagewhich is proportional to absolute temperature.The VPTAT voltage will compensate for internaltemperature variation of the Ic and boost circuits.The cutoff frequency, determined by the -3dB pointrelative to a very low frequency value « 1 a kHz), isrelated to the current IVFP injected into pin IFP by thefollowing formulas.Ic (ideal, in MHz) = 21.67 • IFP = 21.67 • IVFP • 1.B/VPTATwhere IFP and IVFP are in mA, VPTAT is in volts, Ta= 25°C and 0.1B5 :::; IFP :::; 0.6 mA for FB003.If a current source is used to inject current into pin I FP,pin VFP should be left open.If the SSI32FB003 cutoff frequency is set using voltageVPTAT to bias up a resistor tied to pin VFP, the cutofffrequency is relatedtothe resistor value by the followingformulas.Ic (ideal, in MHz) = 21.67 • IFP = 21.67· 1.B/(3 • Rx)Rx in kQIf pin VFP is used to program cutoff frequency, pin IFPshould be left open.MAGNITUDE EQUALIZATION PROGRAMMINGThe magnitude equalization, measured in dB, is theamount of high frequency peaking atthe cutofffrequencyrelative to the original-3 dB point. For example, when12 dB boost is applied, the magnitude resP9nse peaksup 9 dB at Ic above the OC gain.The amplitude of the input signal at frequencies nearthe cutoff frequency can be increased using this feature.Applying an external voltage to pin VBP which isproportional to reference output voltage VPTAT(provided by the VPTAT pin) will set the amount ofboost. A fixed amount of boost can be set by anexternal resistor divider network connected from pinVBPto pins VPTATandGNO. No boost is applied if pinFBST, frequency boost enable, is at a low logic level.The amount of boost FB at the cutoff frequency Ic isrelated to the voltage VBP by the formulaFB (ideal, in dB) = 20 log1o[3.73(VBPIVPTAT)+1],where a < VBP < VPT A T.POWER ON I OFFThe SSI 32FB003 supports a power down mode forminimal idle mode power dissipation. When PWRONis pulled up to TTL logic high, the device is in normaloperation mode. When PWRON is pulled down toTTL logic low, or left open, the device is in the powerdown mode.8-14

SSI32F8003Low-Power ProgrammableElectronic FilterPIN DESCRIPTIONNAMEVIN+, VIN-VO_NORM+,VO_NORM-VO_DIFF+,VO_DIFF-IFPVFPVBPFBSTPWRONVPTATVCCGNDTYPEI°°IIIII°°IDESCRIPTIONDifferential Signal Inputs. The input signals must be AC coupled to these pins.Differential Normal Outputs. The output signals must be AC coupled.Differential Differentiated Outputs. For minimum time skew, these outputsshould be AC coupled.Frequency Program Input. The filter cutoff frequency fc, is set by an externalcurrent IFP, injected into this pin. IFP must be proportional to voltage VPTAT.This current can be set with an external current generator such as a DAC. VFPshould be left open when using this pin.Frequency Program Input. The filter cutoff frequency can be set by programminga current through a resistor from VPTAT to this pin. I FP should be leftopen when using this pin.Frequency Boost Program Input. The high frequency boost is set by anexternal voltage applied to this pin. VBP must be proportional to voltageVPTAT. A fixed amount of boost can be set by an external resistor dividernetwork connected from VBP to VPTAT and GND. No boost is applied if theFBST pin is grounded, or at logic low.Frequency Boost. A high logic level or open enables the frequency boostcircuitry. A low input disables this function.Power On. A high logic level enables the chip. A low level or open pin puts thechip in a low power state.PTAT Reference Voltage. This pin outputs a reference voltage w~ich isproportional to absolute temperature (PTAT). VBP, VFP or IFP must bereferenced to this pin for proper operation.+5 Volt Supply.GroundELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may damage the device.PARAMETERRATINGSStorage Temperature -65°C to + 150°CJunction Operating Temperature, Tj+130°CSupply Voltage, VCC-O.5V to 7VVoltage Applied to Inputs-O.5V to VCCI8-15

SSI32F8003Low-Power ProgrammableElectron ic FilterELECTRICAL SPECIFICATIONS (continued)RECOMMENDED OPERATING CONDITIONSPARAMETERRATINGSSupply voltage vcc 4.50V < VCC < 5.50VAmbient Temperature Ta O°C < Ta < 70°CELECTRICAL CHARACTERISTICSUnless otherwise specified recommended operating conditions apply.Power Supply CharacteristicsPARAMETER CONDITIONS MIN NOMPower Supply Current ICC PWRON $; 0.8V 0.1Power Supply Current ICC PWRON ~ 2.0V 46Power Dissipation PD PWRON ~ 2.0V, VCC = 5.0V 230PWRON ~ 2.0V, VCC = 5.5V 275PWRON $; 0.8V 0.5DC CharacteristicsHigh Level Input Voltage VIH TIL input 2Low Level Input Voltage VILHigh Level Input Current IIH VIH = 2.7VLow Level Input Current ilL VIL = OAV -1.5Filter CharacteristicsFilter Cutoff Frequency *fc421.67 MHz (IVFP)*(f -3d8)fcrnAFilter Ie Accuracy FCA fc = max. -13VO_NORM Diff Gain AO F = 0.67 fc, FB = 0 dB 0.8VO_DIFF Diff Gain AD F = 0.67 fc, FB = 0 dB 0.8AOFrequency Boost at fc FB VBP = VPTAT fc = max. 12 13.5fc = min. 11.5 13Frequency Boost Accuracy FBA VBP/vPTAT = 1.0 le= max. -1.5MAXUNIT0.5 mA60 mA300 mW330 mW2.5 mWV0.8 V20 ~mA13 MHz+13%1.2 V/v1.2AOV/v15 dB14.5 dB1.5 dB8-16

SSI32F8003Low-Power ProgrammableElectron ic FilterFILTER CHARACTERISTICS (continued)PARAMETER CONDITIONS MIN NOM MAX UNITGroup Delay Variation TGDO fc = max, VBP =0 -1 +1 nsWithout Boost (continued)VPTATF = 0.2 fc to fefc = min, VBP =0 -3 +3 nsVPTATF = 0.2 fc to feF = 0.2 fc to fe,F = fc to 1.75 fe~=oVPTAT~=oVPTAT-2 +2 %-3 +3 0/0Group Delay Variation TGDB fe = max, VBP = VPTAT -1 +1 nsWith BoostF = 0.2 fc to fefe = min, VBP = VPTAT -3 +3 nsF = 0.2 to fcF = 0.2 fe TO fe, VBP = VPTAT -2 +2 0/0F = fe to 1.75 fe, VBP = VPTAT -3 +3 %Filter Input Dynamic Range VIF THD = 1% max, F = 0.67 fe, VBP = OV 1 Vp-p(1000 pF across Rx)THD = 1.5% max, F = 0.67 fe, VBP = OV, 1.5 Vp-pNormal output (1000 pF across Rx)Filter Input Dynamic Range VIF THD = 2.0% max, F = 0.67 fe, VBP = OV, 1.5 Vp-pDifferentiated output(1000 pF across Rx)Filter Diff Input Resistance RIN 3 4.3 kOFilter Input Capacitance CIN 7 pFOutput Noise Voltage EOUT BW = 100 MHz, Rs = 500 3 mVrmsDifferentiated Outputfc = max, VBP = OVI8-17

SSI32F8003Low-Power ProgrammableElectronic FilterELECTRICAL SPECIFICATIONS (continued)FILTER CONTROL CHARACTERISTICSPARAMETERCONDITIONSOutput Noise Voltage EOUT BW = 100 MHz, Rs = 50nNormal Outputfe = max, VBP = OVOutput Noise Voltage EOUT BW = 100 MHz, Rs = 50nDifferentiated Outputfe = max, VBP = VPTATOutput Noise Voltage EOUT BW = 100 MHz, Rs = 50nNormal Outputfc = max, VBP = VPTATFilter Output Sink Current 10-Filter Output Source Current 10+Filter Output Resistance RO 10+ = 1.0 mA(Single ended)Reference Voltage VPTAT Tj = 25°CPTAT Voltage InputVFPProgramming Current IVFP Ta = 25°CRangeProgramming VoltageRangeVVBPVoltage at pin IFP V 1FP, vFP= 0 mAPower Up TimePower Down TimefC = minfe = maxMIN NOM MAX UNIT1.8 mVrms4.3 mVrms2.2 mVrms1 mA2 mA60 n1.8 V2/3 VPTAT V0.185 0.6 mA0 VPTAT V2/3 VPTAT V1.5 I...IS1 Ils1 IlS8-18

SSI32F8003Low-Power ProgrammableElectronic FilterN/CVO_NORM­VO_NORM+VCC (+5V)VIN­VIN+VBPFBSTRBP2VO_DIFF+VO_DIFF-N/CR,IFPVFP-----~GNDRBP1VPTAT = 1.8V (25°C)VVFP = 2/3 (VPT A T)IVFP range: 0.185 mA to 0.6 mA@25°CFixed frequency programming is accomplished as shown in the drawing above.In this case IVFP (programming current) is equivalent tOVPTAT 1__ 0-i.e., jc = 13 MHz then 3 RxIVFP = 0.6 mA @25°C Rx = 1 kQFixed boost programming is also accomplished as shown above. In this caseVVBP is set by a voltage divider, where VvBP is a fraction of VPT AT.i.e.,boost = 9 dB then,VBP/vPTAT = 0.488 9 dB = 20 log [3.73 (0.488) + 1]R BP2 1R (VPTAT )=0.953BP1 ---1VBPCx = 1000 pF - Cx is needed for lower THO at lower fc.FIGURE 4: 32F8003 Applications SetupI8-19

SSI32F8003Low-Power ProgrammableElectronic FilterINPUT1.317032.95139 5.37034S2+ S 1.54203 + 2.95139 S2+ S 1.14558 + 5.37034S2+ S 1.68495 + 1.31703Normalized for (J)c = (21t) jc = 1AN and AD are adjusted for unity gain (0 dB) at F = 0.67 jcDenormalize the frequency by substituting S ~ (S/21tjc)Eq for jc = 27 MHz, S = S / [(21t)(27 x 10 6)]FIGURE 5: 32F8003 Normalized Block DiagramTABLE 1: 32F8003 Frequency Boost Calculations, K = 1.31703 (1 oB° OST (dB)/20 - 1)Assuming 13.5 dB boost forVBP = VPTATBoostKVBP---VPTATBoost1 dB 0.16 0.033 6dB 1.31VBP ( 10 (FB/20)) - 1 2dB 0.34 0.069 7dB 1.633 dB 0.54 0.110 8dB 1.99VPTAT 3.734dB 0.77 0.157 9dB 2.405dB 1.03 0.209 10 dB 2.8511 dB 3.3612 dB 3.4313 dB 4.57VBPVBP--- Boost ---VPTATVPTAT0.1 2.753 dB 0.6or, 0.2 4.841 dB 0.7boost in dB =20 log [3.73 (V~~:T ) +1]0.3 6.523 dB 0.80.4 7.391 dB 0.90.5 9.142 dB 1.0KVBP---VPTATBoost0.2670.3320.4050.4880.5800.6830.7990.92910.206 dB11.153 dB12.006 dB12.784 dB13.5 dB8-20

SSI32F8003Low-Power ProgrammableElectronic FilterTABLE 2: CalculationsTypical change in j-3 dB pOint with boostBoost (dB) Gain@fc (dB) Gain@ peak (dB) fpeak/fc f-3dB/fc0 -3 0.00 no peak 1.001 -2 0.00 no peak 1.212 -1 0.00 no peak 1.513 0 0.15 0.70 1.804 1 0.99 1.05 2.045 2 2.15 1.23 2.206 3 3.41 1.33 2.337 4 4.68 1.38 2.438 5 5.94 1.43 2.519 6 7.18 1.46 2.5910 7 8.40 1.48 2.6611 8 9.59 1.51 2.7312 9 10.77 1.51 2.8013 10 11.92 1.53 2.8714 11 13.06 1.53 2.93Notes: 1. jc is the original programmed cutoff frequency with no boost2. j-3 dB is the new -3 dB value with boost implemented3. jpeak is the frequency where the amplitude reaches its maximumvalue with boost implementedLe., jc = 9 MHz when boost = 0 dBif boost is programmed to 5 dB thenj-3 dB = 19.8 MHzjpeak = 11.07 MHzI8-21

SSI32F8003Low-Power ProgrammableElectron ic FilterPACKAGE PIN DESIGNATIONS(Top View)THERMAL CHARACTERISTICS: 9ja16-lead SON (150 mil)N/CVO_DIFF+16-lead SOL (300 mil)100°CIWVO_NORM-VO_DIFF-VO_NORM+PWRONVCCVPTATVIN-N/CVIN+IFPVBPVFPFBSTGND16-Lead SON, SOLCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONSSI32F8003 16-Lead SOL16-Lead SONORDER NUMBER32F8003-CL32F8003-CNPACKAGE MARK32F8003-CL32F8003-CNPreliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations andare not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1993 Silicon Systems, Inc.Protected by the following patents:(5,063,309) (710,512) (823,067) (5,182,477)8-22 1094 - rev.

SSI32F8101Low-Power Programmable FilterJanuary 1995DESCRIPTIONThe 32F8101 is a high performance, low power,digitally programmable low-pass filter for applicationsrequiring variable-frequency filtering. The deviceconsists ofthreefunctional blocks: [1] a 7th-order 0.05°Equiripple Low-Pass filter, [2] two DACs for controllingthe filter cutoff frequency and high-frequency peaking(boost), and [3] a Serial Port for programming the Icand Boost DACs.Cutoff frequency and boost are controlled by the twoon-chip 7 -bit DACs, which are programmed via the 3-line serial interface. Boost is programmable from 0 to14.6 dB nominally at maximum fc, and is implementedusing two symmetrical, real-axis zeroes. Both boostand fc control do not affect the flat group delayresponse.The 32F81 01 device is ideal for variable data rate andvariable frequency shaping applications. It requiresonly a +5V supply and has an idle mode for minimalpower dissipation. The SSI 32F8101 is available in a16-lead SON package.FEATURES• Programmable cutoff frequency - 8.9 to 27 MHz• Programmable boost/equalization of 0 to14.6 dBMatched normal and differentiated outputs±15% Ic accuracy±2% maximum group delay variation• Less than 1.5% total harmonic distortion• Low-Z input switch controlled by LOWZ pin• No external filter components required95 mW nominal power,

SSI32F8101Low-Power Programmable FilterFUNCTIONAL DESCRIPTIONThe SSI 32F8101 programmable filter consists of anelectronically controlled low-pass filter with a separatedifferentiated low-pass output. A seven-pole, low-passfilter is provided along with a single-pole, single-zerodifferentiator. Both outputs have matched delays. Thedelay matching is unaffected by any amount ofprogrammed equalization or bandwidth. Programmableba~dwidth and boosVequalization is provided by internal7-bIt control DACs. High-frequency boost equalizationis accomplished by a two-pole, low-pass with a twopole,high-pass feed forward section to providecomplimentary real axis zeros. A variabl~ attenuator isused to program the zero locations.The filter implements a 0.05 degree equiripple linearphase response. The normalized transfer functions(Le., roc = 2rcfc = 1) are:VnormlVi = 13.65983· [(_KS2 + 1.31703)/D(s)] • ANandVdiffNi = (VnormlVi) • (s/0.86133) • ADWhere D (5)=(S2+ 1.68495s+ 1.31703)(S2+ 1.54203 s+2.95139)(S2+ 1 .4558s+5.37034)(s+0.86133),AN and AD are adjusted for a gain of 1 at fs=(2/3)fc.FILTER OPERATIONNormally AC coupled differential signals are applied tothe VIN± inputs of the filter, although DC coupling canbe implemented. To improve settling time ofthe couplingcapacitors, the VIN± inputs are placed into a Low-Zstate when the [OWZ pin is brought low. Theprogrammable bandwidth and boost/equalizationfeatures are controlled by internal DACs and theregisters programmed through the serial port. Thecurrent reference for both DACs is set using a single13.3 kQ external resistor connected from pin RX toground. The voltage at pin RX is proportional to absolutetemperature (PTAT), hence the current forthe DACs isa PTAT reference current.Bandwidth ControlThe programmable bandwidth is set by the filter cutoffDAC. This DAC has two separate 7-bit registers thatcan program the DAC value as follows:Ie = 0.2133 • DACF - 0.094 (MHz)where DACF = Cutoff Frequency Control Registervalue (deCimal)The filter cutoff set by the internal DAC is the unboosted3 dB frequency. When boost/equalization is added, theactual 3 dB point will move out. Table 1 providesinformation on boost versus 3 dB frequency.INPUT1.31703 2.95139 5.37034S2 + S 1.68495 + 1.31703S2+ S 1.54203 + 2.95139 S2 + S 1.14558 + 5.37034S2+ S 1.68495 + 1.31703Normalized for roc = (2n) fc = 1AN and AD are adjusted for unity gain (0 dB) at F = 0.67 fcDenormalize the frequency by substituting S --+ (S/2nfc)Eq for fc = 27 MHz, S = S / [(2n)(27 x 10 6 )]FIGURE 1: 32F8~01 Normalized Block Diagram8-24

551 32F8101Low-Power Programmable FilterTABLE 1: CalculationsTypical change in f-3 dB point with boostBoost (dB) Gain@jc (dB) Gain@ peak (dB) jpeak/jc j-3 dB/jc K0 -3 no peak no peak 1.00 01 -2 no peak no peak 1.21 0.162 -1 no peak no peak 1.50 0.343 0 0.15 0.70 1.80 0.544 1 0.99 1.05 2.04 0.775 2 2.15 1.23 2.20 1.036 3 3.41 1.33 2.33 1.317 4 4.68 1.38 2.43 1.638 5 5.94 1.43 2.51 1.979 6 7.18 1.46 2.59 2.4010 7 8.40 1.48 2.66 2.8511 8 9.59 1.51 2.73 3.3612 9 10.77 1.51 2.80 3.9313 10 11.92 1.53 2.87 4.5714 11 13.06 1.53 2.93 5.2815 12 14.18 1.56 3.0 6.09Notes: 1. jc is the original programmed cutoff frequency with no boost2. j-3 dB is the new -3 dB value with boost implemented3. jpeak is the frequency where the amplitude reaches its maximumvalue with boost implementedi.e., jc = 9 MHz when boost = 0 dBif boost is programmed to 5 dB thenBOOST (dB)4. K = 1.31703 (10 20 - 1)j-3 dB = 19.8 MHzjpeak = 11.07 MHzI8-25

SSI32F8101Low-Power Programmable FilterBOOST/EQUALIZATION CONTROLThe programmable equalization is also controlled byan internal DAC. The 7 -bit Filter Boost Control Register(FBCR) determines the amount of equalization that willbe added to the 3 dB cutoff frequency, as follows:Boost =20 log [(0.0239· DACB) + 7.6.10- 5 • DACB· DACF) +1.132]where DACB = value in FBCR register.For example, with the DAC set for maximum output(FBCR = 7F hex or 127) atthe maximum cutofffrequency(DACF = 7F hex or 127) there will be 14.6 dB of boostadded at the 3 dB frequency. This will result in + 11 dBof signal boost above the 0 dB baseline.SERIAL INTERFACE OPERATIONThe serial interface is a CMOS bi-directional port forreading and writing programming data from/to theinternal registers of the 32F8101. For data transfersSDEN is brought high, serial data is presented at theSDATA pin, and a serial clock is applied to the SCLKpin.Afterthe SDEN goes high, the first 16 pulses applied tothe SCLK pin will shift the data presented at the SDATApin into an internal shift register on the rising edge ofeach clock. An internal counter prevents more than 16bits from being shifted into the register. The data in theshift register is latched when SDEN goes low. If lessthan 16 clock pulses are provided before SDEN goeslow, the data transfer is aborted.All transfers are shifted into the serial port LSB first. Thefirst byte of the transfer is address and instructioninformation. The LSB of this byte is the R/W bit whichdetermines if the transfer is a read (1) ora write (0). Theremaining seven bits determine the internal register tobe accessed. The second byte contains theprogramming data. At initial power-up, the contents ofthe internal registers will be in an unknown state andthey must be programmed prior to operation. Duringpower down modes, the serial port remains active andregister programming data is retained.SDE~SDAT~ >---FIGURE 2: Serial Port Data Transfer FormatSDEN ~ ~DEN setup1 ....... 1 wrt SCLK risesSCLK1 111 I:-: SCLK periodLoad datainto RegisterL1 1 SDEN hold;1 wrt to SCLK risesSDATA1SDATA setup 1 1 1 SDATA holdwrt SCLK rises :--t-: wrt SCLK risesFIGURE 3: Serial Interface Timing Diagram - Writing Control Register8-26

TABLE 2: Serial Port Register MappingREGISTER NAME~ADDRESS~ ~ D7DATA BITMAPPOWER DOWN CONTROL o 0 0 0 0 1 o 0 - - - -DATA MODE CUTOFF o 0 o 0 0 1 1 0. DAC DAC DACBIT 6 BITS BIT4SERVO MODE CUTOFF o 0 1 0 0 1 1 0 . DAC DAC DACBIT6 BITS BIT 4-FILTER1=DISABLE -O:ENABLEDAC DAC DACBIT3 BIT2 BIT 1DAC DAC DACBIT3 BIT2 BIT 1DODACBIT 0DACBITOFILTER BOOST, DATA 0 0 0 1 0 1 1 0 -DAC DAC DACBIT 6 BITS BIT 4DAC DAC DACBIT3 BIT 2 BIT 1DACBIT 0FILTER BOOST, SERVO o 0 1 1 0 1 1 0 -DAC DAC DACBIT 6 BITS BIT4DAC DAC DACBIT3 BIT2 BIT1DACBITO* These bits are used only for testing. They should be programmed to 0 in actual operation.(l)r\,-...jr­o:eI-Co:eCD""I-c""Ioc.c""IQ)3CJ)3CJ)1»­C"w-I\)CD.".,,(X) ......._::::;'0CD ......""I

SSI32F8101Low-Power Programmable FilterPIN DESCRIPTIONPOWER SUPPLY PINSNAME TYPE DESCRIPTIONVCA - Filter analog power supply pinVCD - Serial port power supply pinAGND - Filter analog ground pinDGND - Serial port digital ground pinINPUT PINSVIN+, VIN- I FILTER SIGNAL INPUTS: The AGC output signals must be AC coupled intothese pins.SG I SERVO GATE: TTL input when high enables servo frequency and boostregisters to the control DACs. When low the data frequency and boostregisters are enabled.LOWZ I LOW_Z CONTROL: TTL input when low reduces the filter input resistance.When high, the input is at high impedance state.OUTPUT PINSVO_DIFF+, 0 DIFFER ENTIAL DIFFERENTIATED OUTPUTS: Filterdifferentated VO _01 FFoutputs.These outputs are normally AC coupled.VO_NORM+, 0 DIFFERENTIAL NORMAL OUTPUTS: Filter normal low pass output signals.VO_NORM- These outputs are normally AC coupled.RX - REFERENCE RESISTOR INPUT: An external 13.3 kn, 1% resistor is connectedfrom this pin to ground to establish a precisePT AT (proportional toabsolute temperature) reference current for the filter.SERIAL PORT PINSSDEN 1/0 SERIAL DATA ENABLE: Serial enable CMOS compatible input. A high levelinput enables the serial port.SOl 1/0 SERIAL DATA: Serial data CMOS compatible input. NRZ programming datafor the internal registers is applied to this input.SCLK 1/0 SERIAL CLOCK: Serial clock CMOS compatible input. The clock applied tothis pin is synchronized with the data applied to SDATA.8-28

551 32F8101Low-Power Programmable FilterELECTRICAL SPECIFICATIONSUnless otherwise specified, the recommended operating conditions are as follows: 4.5V < POSITIVESUPPLY VOLTAGE < 5.5V, O°C < T (ambient) < 70°C, and 25°C < T(junction) < 135°C. Currents flowing intothe chip are positive. Current maximums are currents with the highest absolute value.Rx = 13.3 kn, Cx = 1000 pF from Rx pin to VCA. Input signals are AC-coupled into VIN±.ABSOLUTE MAXIMUM RATINGSOperation beyond the maximum ratings may damage the device.PARAMETERRATINGStorage Temperature -65 to 150°CJunction Operating TemperaturePositive Supply Voltage (Vp)+130°C-0.5 to 7VVoltage Applied to Logic Inputs -0.5V to Vp + 0.5VAll other Pins -0.5V to Vp + 0.5VPOWER SUPPLY CURRENT AND POWER DISSIPATIONPARAMETER CONDITIONS MIN NOM MAX UNITSICC (VCA,D) Output pins open 19 30 rnADACF = 127Boost = 0 dBPWR Power Dissipation Output pins open 95 165 mWDACF = 127Boost = 0 dBSleep Mode Power PWRON = 1 5 mWTTL COMPATIBLE INPUTSI nput low voltage VIL -0.3 0.8 VInput high voltage VIH 2 VPD VInput low current ilL VIL = O.4V -0.4 rnAInput high current IIH VIH = 2.4V 100 (JACMOS COMPATIBLE INPUTSInput low voltage Vp=5V -0.3 1.5 VInput high voltage Vp= 5V 3.5 VCD V+0.3+0.3I8-29

SSI32F8101Low-Power Programmable FilterELECTRICAL SPECIFICATIONS (continued)SERIAL PORTPARAMETERSCLK periodCONDITIONSRead from serial portWrite to serial portSCLK low time TCKL Read from serial portWrite to serial portSCLK high time TCKH Read from serial portEnable to SCLKSCLK to disableData set-up timeData hold timeTSENSTSENHTDSTDHSDATA tri-state delay TSENDLSDATA turnaround timeSDEN low timeTTRNTSLWrite to serial portPROGRAMMABLE FILTER CHARACTERISTICSFilter cutoff rangefc @ -3 dB pointfc = (0.2133 MHz)XDACF - 0.0941, Boost = 0 dB42:

SSI32F8101Low-Power Programmable FilterPROGRAMMABLE FILTER CHARACTERSITICS (continued)PARAMETER CONDITIONS MIN NOM MAX UNITSData mode group delay DACF = 127 -0.5 +0.5 nsvariation, DACS = 0 to 127 f = 0.2 fc to fcDACF = 42 -1.25 +1.25 nsf = 0.2 fc to fcDACF = 127 -0.95 +0.95 nsf=fcto1.75fcDACF = 42 -1.9 +1.9 nsf=fct01.75fcFilter differential output THO = 1.5%, f = 0.67fc 1 Vp-pdynamic rangeboost = 0 dB,normal and differentiated outputsFilter differential input resistance Normal 4 kQLow-Z 200 400 0Filter differential input capacitance 7 pFOutput Noise Voltage: BW = 100 MHz, Rs = 500differentiated output fc = 27 MHz, boost = 0 dB 4.4 6.6 mV Rmsdifferentiated output fc = 27 MHz, DACS = 127 7.7 11.6 mV Rmsnormal output fc = 27 MHz, boost = 0 dB 2.5 3.8 mV Rmsnormal output fc = 27 MHz, DACS = 127 3.7 5.6 mV RmsFilter output sink current 0.5 rnAFilter output offset voltage -200 200 mVFilter output source current 2.0 rnAFilter output resistance single ended 200 0Rx pin voltage Ta = 2rC 600 mVTa = 127°C 800 mVRx resistance 1 % fixed value 13.3 kOI8-31

SSI32F8101Low-Power Programmable FilterSDEN--.J.~------------~11~------------------------~SCLKRIW ADDRO ADDR6r~~~~)~ RIW / ADDRO 00ADDR6/ 00DATA?}-FIGURE 4: Serial Port Timing InformationPACKAGE PIN DESIGNATIONS(Top View)DGND 16VO_NORM- 15VO_NORM+ 14VCA 13VIN- 12VIN+ 11SG 10LOWZ16·Lead SONVO_DIFF+VO_DIFF-AXSCLKVCDSDENSDIAGNDTHERMAL CHARACTERISTICS: 9ja16-lead SON100 0 C/WCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONORDER NUMBERPACKAGE MARKSSI32F810116-Lead SON32F8101-CN32F8101-CNPreliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations andare not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or tradem'arks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-69140195 - rev.8-32©1993 Silicon Systems, Inc.Protected by the following patents:(5,063,309) (710,512) (823,067)

SSI32F8120Low-Power ProgrammableElectronic FilterJanuary 1994DESCRIPTIONThe SSI32F8120 is a continuous time, low pass filterwith programmable bandwidth and high frequencyboost. The lowpassfilterisa2zero!7pole 0.05° phaseequiripple type, featuring excellent group delaycharacteristics. It features 1.5 - 8 MHz programmablebandwidth and 0-10 dB programmable boost. Bothfunctions are controlled by 7-bit command words,which are input via a 3-line serial interface.FEATURESProgrammable filter cutoff frequency (fc =1.5to 8 MHz) with no external componentsProgrammable pulse slimming equalization(0 to 10 dB boost at the filter cutoff frequency)± 10% cutoff frequency accuracyMatched normal and differentiated low-passoutputsDifferential filter inputs and outputsDevice Idle mode+5V only operationNo external filter components requiredSupports constant density recordingBLOCK DIAGRAMPIN DIAGRAMVO_NORM+VO_NORM·VO_OIFF+VO_OIFF-VFPVBPOGNO 16 VO_OIFF+VO_NORM- 2 15 VO_OIFF-VO_NORM+ 3 14 RXVCA 4 13 SCLKVIN- 5 12 veoVIN+ 6 11 SOENVBP 10 SOlVFP 8 9 AGNORXIVCA AGNO VCO DGNO SOEN SOl SCLKCAUTION: Use handling procedures necessaryfor a static sensitive component.0194 - rev. 8-33

SSI32F8120Low-Power ProgrammableElectron ic FilterFUNCTIONAL DESCRIPTIONCUTOFF FREQUENCY PROGRAMMINGThe SSI 32F8120 programmable electronic filter canbe set to afiltercutoff frequency from 1.5 to 8 MHz. Thecutoff frequency can be set by using the serial portthrough pins SDI, SDEN, and SCLK. SDI is the serialdata input for an 8-bit control shift register, SDEN is thecontrol register enable, and SCLK is the control registerclock. The data packet is transmitted MSB (D7) first.The first four bits are the register address, the last fourare the data bits. Registers largerthan four bits must beloaded with two 8-bit data packets. See Table 1.jc is determined by the equation:jc (MHz) = 0.061321 (F _Code) + 0.2122641.5 MHz -:;, jc -:;, 8 MHz21 -:;, F _ Code -:;, 127SLIMMER HIGH FREQUENCY BOOSTPROGRAMMINGThe amplitude of the input signal at frequencies nearthe cutoff frequency can be increased using this feature.By controlling the V-DAC output, the boost can bedetermined. The amount of boost at the cutoff frequencyis related to the V-DAC output by the following formula:S Code[Output of V-DAC = VBP = VREFx~]BOOST (dB) = 20·log [0.01703 (S_Code) +1].TABLE 1ADDRESS BITS USAGE DATA BITSD7 D6 D5 D4 D3 D2 D1X 0 0 0 S-MSB REGISTER X S6 S5X 0 0 1 S-LSB REGISTER S3 S2 S1X 0 1 0 F-MSB REGISTER X F6 F5X 0 1 1 F-LSB REGISTER F3 F2 F1X 1 1 1 P REGISTER X X XDOS4SOF4FOPOX = Don't CareS = 7-bit Boost (Slimming) ControlF = 7-bit Frequency (Bandwidth) ControlP = Power Down Control; PO = 1 for power up; PO = 0 for power downclocks data brt I I~ TC--JSCLKn ~I.-! SDEN setup SDEN hold L.!..-! SDEN fallsI I wit SCLK falls wit SCLK falls I I I prior to SCLK,...--1i--___________________ ----,T2B risesSDENT4~~I~~~~ fallsload datainto registerSDIFIGURE 1: Serial Port Timing Diagram8-34

551 32F8120Low-Power ProgrammableElectronic FilterPIN DESCRIPTIONNAMEVIN+, VIN-TYPEVO_NORM+, 0VO_NORM-SDENSCLKSOlRX -VCAVCDAGNDDGNDVBP 0VFP 0IIIIIIIIDESCRIPTIONDIFFERENTIAL FILTER INPUTS. The input signals must be AC coupled tothese pins.DIFFERENTIAL NORMAL OUTPUTS. The output signals must be ACcoupled to the pulse detector.DIFFERENTIAL DIFFERENTIATED OUTPUTS. Forminimum pulse pairing,these outputs should be AC coupled to the pulse detector.SERIAL DATA ENABLE. A logic HIGH level allows SERIAL CLOCK to clockdata into the control register via the SERIAL OAT A input. A logic LOW levellatches the register data and issues the information to the appropriate circuitry.SERIAL CLOCK. Negative edge triggered clock input for serial register.SERIAL DATA INPUT.REFERENCE CURRENT SET. With an external resistor (Rx = 5 kQ±1%) toground, this pin gives a voltage proportional to the absolute temperature,setting the range for VFP.ANALOG +5 VOLT SUPPLY.DIGITAL +5 VOLT SUPPLY.ANALOG GROUND.DIGITAL GROUND.BOOST PROGRAMMING VOLTAGE. Output of V-DAC which programs theboost.CUTOFF FREQUENCY PROGRAMMING VOL TAGE. Output of I-DAC whichprograms the cutoff frequency.**A minimum load resistance of 150 kQ should be used to avoid affecting the total minimum on-chip resistanceof 1.35 kQ.VO_DIFF+ 0VO_DIFF-_._-I8-35

SSI32F8120Low-Power ProgrammableElectronic FilterELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may damage the device.PARAMETERStorage TemperatureJunction Operating Temperature, TjSupply Voltage, veeVoltage Applied to Inputs*Maximum Power Dissipation, jc = 8 MHz, Vee = 5.5VT1 Lead Temperature (1/16" from case for 1 0 seconds)RATING-65 to + 150°C+130 o e-0.5 to 7V-0.5 to vee v0.5W260°C* Analog input signals of this magnitude shall not cause any change or degradation in filter performance aftersigmi'l has returned to normal operating range.RECOMMENDED OPERATING CONDITIONSSupply voltage, vee 4.5V < vee < 5.5VAmbient Temperature o °e < Ta < 70°CTj Junction Temperature o °e < Tj < 130°C----_._-----ELECTRICAL CHARACTERISTICSUnless otherwise specified recommended operating conditions apply.PARAMETER CONDITIONS MIN NOM MAX UNITIsupply vee = 5.5V, outputs unloaded 55 75 rnAIdle Mode Current 9 13 rnAIdle to Active Mode Recovery Time 50 IlSSerial port program to output 50 Ilsresponse timeDC CharacteristicsVIH High Level Input Voltage TIL input 2.0 V-- -VIL Low Level Input Voltage 0.8 VIIH High Level Input Current VIH = 2.7V---20 J.lAilL Low Level Input Current VIL = O.4V -1.5 rnA8-36

SSI32F8120Low-Power ProgrammableElectronic FilterFilter CharacteristicsPARAMETERIcFCAAOADFBFilter Cutoff FrequencyFilter Ic AccuracyCutoff ResolutionVO_NORM Diff GainVO_DIFF Diff GainFrequency Boost at IcFBA Frequency Boost AccuracyFBA Frequency Boost AccuracyTGDOGroup Delay VariationWithout BoostIc = 1.5 - 8 MHzgdm = group delay magnitudeTGDBBoost ResolutionGroup Delay VariationWith BoostIc = 1.5 - 8 MHzVOF Filter Output Dynamic RangeVOF Filter Output Dynamic RangeVOF Filter Output Dynamic RangeVOF Filter Output Dynamic RangeCONDITIONS MIN NOM MAX UNIT21 ::; F _Code::; 127 1.5 8 MHzF _Code = 127 -10 +10 0/0..--------------------F _Code = 21 -15 +15 0/0- - ----- ---------- - ..---~.--1.5to 8 MHz 100 kHzF = 0.67 Ic 0.7-----------1.1 VNF = 0.67 Ic 0.90 AO 1.2AO VNFB(dB) = 20 log [0.01703 (5_ Code) + 1] 0 10 dBo to 10 dB, Ta < 22°C -1.5 +1.5 dBo to 10 dB, Ta > 22°C -1 +1 dB0.2 Ic -Ic -2% +2% nsgdmgdmIc - 1.75 Ic -3% +3% nsgdmgdm0.2 Ic -Ic -2% +2% nsgdmgdmIC-1.75/c -3% +3% nsgdmgdm1.5to 8 MHz .25 dBTHO = 1.5% max, V8P = 0, VO_NORM 1.5 Vppd1000 pF capacitor across RxF _Code = 127THO = 3.5% max, V8P = 0, VO_OIFF 1.5 Vppd1000 pF capacitor across RxF _Code = 127----~---------~----THO = 1.5% max, VBP = 0, VO_NORM 1.0 Vppd1000 pF capacitor across RxF _Code = 21THO = 2.0% max, VBP = 0, VO_OIFF 1.0 Vppd1000 pF capacitor across RxF_Code = 21I8-37

..SSI32F8120Low-Power ProgrammableElectronic FilterELECTRICAL SPECIFICATIONS (continued)Filter Characteristics (continued)PARAMETERRINCINFilter Diff Input ResistanceFilter Input CapacitanceCONDITIONSEOUT Output Noise Voltage BW = 100 MHz, o dB Boost(VO_NORM) 50n inputIc = 8 MHz 10 dB BoostEOUT Output Noise Voltage BW = 100 MHz, o dB Boost(VO_DIFF) 50n inputIc = 8 MHz 10 dB Boost10- Filter Output Sink Current10+ Filter Output Source CurrentRO Filter Output Resistance Output source current, 10+ = 1 rnA(Single ended)TC Period, SCLKT1 SDEN Setup to SCLK FallsT2A SDEN Hold wrt SCLK FallsT28 SDEN Falls prior to SCLKRisesT3 SDI Setup to SCLK FallsT4 SDI Hold to SCLK FallsPower Supply Rejection RatioCommon Mode Rejection RatioBias: Vin+, Vin- VCC = 5VVO_NORM+,VO_NORM-VO_DIFF+, VO_DIFF-Output offsetNormal and Differentiated100 rnVpp @5 MHz on VCA, VCOYin = 0 VOC + 100 rnVpp @5 MHzVCC = 5VVCC = 5V--MIN3.01.03.010010--10~-~--25NOM MAX UNITkn- -~.-7 pF---1.8 3 mVRms----t-------_..---- ---25ns--".-25ns----- ---_._---~~-40307050dBdB2.5 2.9_..-3.3 V2.8 3.2 3.6 V-.------~--f------2.8 3.2 3.6 V----.--- --~-1502.35 4 mVRms--- - -~ -4.2 6 mVRms5.85 9 mVRms.._-----mA._.-_._- r---~~mA-----r---~--60 Q----... -------TC/2-10TC/4nsnsns~-----' ----.-~------ns+150 mV8-38

SSI32F8120Low-Power ProgrammableElectron ic FilterTABLE 2: CalculationsTypical change in j-3 dB point with boostBoost (dB) Gain@fc (dB) Gain@ peak (dB) fpeak/fc f-3dB/fc K0 -3 0.00 no peak 1.00 01 -2 0.00 no peak 1.21 0.162 -1 0.00 no peak 1.51 0.343 0 0.15 0.70 1.80 0.544 1 0.99 1.05 2.04 0.775 2 2.15 1.23 2.20 1.036 3 3.41 1.33 2.33 1.317 4 4.68 1.38 2.43 1.638 5 5.94 1.43 2.51 1.979 6 7.18 1.46 2.59 2.4010 7 8.40 1.48 2.66 2.85Notes: 1. jc is the original programmed cutoff frequency with no boost2. j-3 dB is the new -3 dB value with boost implemented3. jpeak is the frequency where the amplitude reaches its maximum value withboost implementedLe., jc = 2 MHz when boost = 0 dBif boost is programmed to 5 dB thenf-3 dB = 4.40 MHzjpeak = 2.46 MHzI8-39

SSI32F8120Low-Power ProgrammableElectronic FilterPACKAGE PIN DESIGNATIONS(Top View)THERMAL CHARACTERISTICS: 9ja16-lead SOL 100 0 C/W20-lead SOV 125 0 C/WN/C 20N/CDGND16 VO_DIFF+DGND 2 19VO_DIFF+VO_NORM-15 VO_DIFF-VO_NORM- 3 18VO_DIFF-VO_NORM+3 14 RXVO_NORM+ 4 17RXVCA4 13 SCLKVCA 5 16SCLKVIN-5 12 VCDVIN- 6 15VCDVIN+6 11 SDENVIN+ 7 14SDENVBP7 10 SDIVBP 8 13SDIVFP8 9 AGNDVFP 9 12AGNDN/C 10 11N/C16-Lead SOL20-Lead SOYCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONORDER NUMBERPACKAGE MARKSSI32F812016-Lead SOL20-Lead SOY-------- --32F8120-CL32F8120-CV32F8120-CL__•• '_0'--------- ---...---.. ---~------"-------32F8120-CVNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheetis current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX 714/573-6914Patent No. 5,063,309, Patent Pending 823,067©1993 Silicon Systems, Inc. 8-401294 - rev.

SSt 32F8130/8131Low-Power ProgrammableElectronic FilterDESCRIPTIONThe SS132F8130/8131 Programmable Electronic Filtersare digitally controlled low pass filters with anormal low pass output and a time differentiated lowpass output. The low pass filter is of a 7 -pole / 2-zero0.05° phase equiripple type, with flat group delayresponse beyond the passband.The SS132F8130/8131 bandwidth and boost are controlledby two on-chip 7-bit DACs, which are programmedvia a 3-line serial interface. The SSI32F8130filter bandwidth is programmable from 285 kHz to 2.2MHz. The SSI32F8131 is programmable from 150 kHzto 1.4 MHz. The boost is programmable from 0 to 10dB. Because the boost function is implemented as twozeros on the real axis with opposite sign, the flat groupdelay characteristic is not affected by the boost programming.The SS132F8130/8131 are ideal for multi-rate, equalizationapplications. They require only a +5V supplyand have a power down mode for minimal idle dissipation.The SSI 32F8130/8131 is available in a 16-leadSOL package.FEATURESJanuary 1995• Programmable filter cutoff frequency (55132F8130: Ic = 0.285 to 2.2 MHz, SSI32F8131 : Ic= 0.15 to 1.4 MHz) with no external components,serial data connections to minimize pin count• Power down mode «5 mW)• Programmable pulse slimming equalization(0 to 10 dB boost at the filter cutoff frequency)• Matched normal and differentiated low-passoutputs• Differential filter inputs and outputs• Programming via internal 7-bit DACs• No external filter components required• +5V only operation• Supports constant density recordingBLOCK DIAGRAMPIN DIAGRAMVIN+VIN-AGNDVO_NORM-1615VO_DIFF+VO_DIFF-VO_NORM+14PWRONVCA13SCLKVO_DIFF­VO_DIFF+DGND2VIN-VIN+SDEN/SDEN121110VCDDGND2VFPISDIDGND1PWRON16-Lead SOLVFPSS132F8130: Lead 7 = SDENSSI 32F8131: Lead 7 = SDEN0195 - rev.Ciz~o8-41CAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI 32F8130/8131Low-Power ProgrammableElectronic FilterFUNCTIONAL DESCRIPTIONThe SS132F8130/8131, a high performance programmableelectronic filter, provides a 7-pole I 2-zero 0.05°equiripple linear phase low pass function with matchednormal and time differentiated outputs. The deviceincludes multiple biquads and first-order sections toaccomplish the filter function, two 7-bit OACs for bandwidthand boost controls, a 3-line serial interface, andcomplete bias reference circuits. Only one externalpreciSion 8.25 kQ resistor should be connected from theVFP pin to ground for operation. See Figure 1.SERIAL INTERFACEThe SSI 32F8130/8131 allows easy digital controls offilter bandwidth and magnitude equalization via a 3-lineserial interface. The three pins are SOl, SOEN andSCLK. SOl is the serial data input to an internal8-bit shiftregister. SDEN is the shift register enable. SCLK is theshift register clock. Besides the 8-bit shift register whichaccepts data from the SOl input, there are four 4-bitregisters which hold the filter bandwidth and boostcontrols. Two 4-bit registers are assigned to each controlfunction, because a 7-bit binary control is required foreach function.The S-MSB register, whose address code is XOOO,holds the 3 MSBs of the boost control. The S-LSBregister, whose address code is X001 , holds the 4 LSBsofthe boost control. The F-MSB register, whose addresscode is X01 0, holds the 4 MSBs of the cutoff frequencycontrol. The F-LSB register, whose address code isX011, holds the 4 LSBs of the cutoff frequency control.The serial interface consists of data packets, which arestructured as 4-bit address decode followed by 4-bitdata. Figure 2 shows the serial interface timing tosuccessfully program the SS132F8130/8131.CUTOFF FREQUENCY PROGRAMMINGThe cutoff frequency, fc, is defined as the -3 dBbandwidth with no magnitude equalization applied,and is programmable from 285 kHz to 2.2 MHz for SSI32F8130, and 150 kHz to 1.4 MHz for SSI 32F8131.While the fc is controlled by an on-chip 7-bit OAC, thecutoff frequency resolution is better than 20-kHz step.Let F _Code be the decimal equivalent of the 7-bitcontrol. The cutoff frequency can be determined by thefollowing equations:SSI32F8130 fe (kHz) = 16.73· F _Code + 84SSI32F8131 fe (kHz) = 10.81 • F _Code + 37where 12 ~ F _Code ~ 127.MAGNITUDE EQUALIZATION PROGRAMMINGThe magnitude equalization, measured in dB, is theamount of high frequency peaking atthe cutoff frequencyrelative to the original -3 dB point. For example, when10 dB boost is applied, the magnitude response peaksup 7 dB above the DC gain. This equalization function isalso controlled by an on-chip 7-bit OAC.Let S_Code be the decimal equivalent of the 7-bitcontrol. The magnitude equalization can be determinedby the equation:Boost (dB) = 20· log [0.0145· S_Code + 1]for 32F8130 10Boost (dB) = 20 • log 1 [0.01703· S~Code + 1]for 32F8131 0where 0 ~ S_Code ~ 127.8-42

SSI 32F8130/8131Low-Power ProgrammableElectron ic FilterINPUT+1.31703 2.95139 5.37034s'+ S 1.68495+ 1.31703 s' + S 1.54203 + 2.95139 S '+ S 1.14558 + 5.37034-KS's' + S 1.68495 + 1.31703Normalized for we = (21t) ic = 1AN and AD are adjusted for unity gain (0 dB) at F = 0.67 icDenormalize the frequency by substituting S ~ (S/21t ic)Eq for ic = 2.5 MHz, S = S / [(21t) (2.5 • 10 6 )] = S / (1.57080 • 10 7 )K = 1.31703(10 Boost(dB) -1)20FIGURE 1: Normalized Transfer Function of the SS132F8130/8131clocks data bitIIJ4- TC~SCLKo SOEN setup SOEN hold ~ SOEN fallsI I wrt SCLK falls wrt SCLK falls I I I prior to SCLK...--:.....: _____________________ --,T2B risesSDEN I SOl holdsT31 T4 wrt SCLK falls~~Is~rlf falls 1 .......1 .--~1.----.SDIload datainto registerFIGURE 2: Serial Port Timing RelationshipNote:The serial data enable function of the SSI32F8130 and that of the 8S1 32F8131 are of opposite polarity.TABLE 1: Data Packet FieldsIADDRESS BITS USAGE DATA BITS07 06 05 04 03 02 01 DORO X 0 0 0 8 - MSB REGI8TER X 86 85 84R1 X 0 0 1 S - L8B REGISTER 83 82 S1 80R2 X 0 1 0 F - MSB REGISTER X F6 F5 F4R3 X 0 1 1 F - LSB REGISTER F3 F2 F1 FOX = Don't care bit.8-43

SSI·32F8130/8131Low-Power ProgrammableElectronic FilterPIN DESCRIPTIONNAMEVIN+, VIN-VO_NORM+,VO_NORM-VO_DIFF+VO_DIFF-PWR_ONSDEN (8130)SDEN (8131)SCLKSOlVCADESCRIPTIONDIFFERENTIAL FILTER INPUTS. The input signals must be AC coupled to these pins.DIFFERENTIAL NORMAL OUTPUTS. Theoutput signals must be AC coupled to the load.DIFFERENTIAL DIFFERENTIATED OUTPUTS. These outputs should be AC coupledto the load.POWER ON. A TTL high logic level enables the chip. A low level or open circuit puts thechip into a low power state.SERIAL DATA ENABLE. An active level allows SCLK to clock data into the shift registervia the SOl input. An inactive level latches the register data and issues the information tothe appropriate circuitry. Active level for SSI32F8130 is HIGH, for SSI32F8131 is LOW.SERIAL CLOCK. Negative edge triggered clock input for serial register.SERIAL DATA INPUT.ANALOG +5 VOLT SUPPLY...... ~ -.. -~~--~--VCD DIGITAL +5 VOLT SUPPLY._...AGNDANALOG GROUND.DGND1DGND2VFPDIGITAL GROUND.CUTOFF FREQUENCY PROGRAMMING REFERENCE. A resistor of 8.25 kn should beconnected between this pin and AGND.ELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may permanently damage the device.PARAMETERRATINGStorage Temperature -65 to + 150°CJunction Operating Temperature, TjSupply Voltage, VCCVoltage Applied to Inputs·+130°C-0.5 to 7VT1 Lead Temperature (1/16" from case for 10 seconds) 260°C-0.5 to VCCV* Analog input signals of this magnitude shall not cause any change or degradation in filter performance aftersignal has returned to normal operating range.RECOMMENDED OPERATING CONDITIONSPARAMETERRATINGSupply voltage, VCC 4.50 < VCC < 5.50VAmbient Temperature 0< Ta < 70°CTj Junction Temperature 0< Tj < 130°C8-44

SSI 32F8130/8131Low-Power ProgrammableElectron ic FilterELECTRICAL CHARACTERISTICSUnless otherwise specified recommended operating conditions apply. F _Code = 64, S_Code = O.PARAMETER CONDITIONS MIN NOM MAX UNITIdle Mode Current 1 rnAIsupply 60 70 rnAPower Dissipation PWR_ON $ 0.8V 6 mWPWR_ON ~ 2.0V 303 385 mWIdle to Active Mode Recovery Time 50 115Serial port program to output 50 115response timeDC CharacteristicsVIH High Level Input Voltage TTL input 2 VVIL Low Level Input Voltage 0.8 VIIH High Level Input Current VIH = 2.7V 25 IlAilL Low Level Input Current VIL = O.4V -1.5 rnAFilter CharacteristicsIc Filter Cutoff Frequency 12 < F _Code < 127SSI32F8130 0.285 2.2 MHzSSI32F8131 0.15 1.4 MHzFCA Filter Ic Accuracy over Ic range 32F8130 -12 +12 0/0Cutoff Resolution32F8131 -10 +10 %32F8130 17 kHzResolution= Maxfc------ "-"127 32F8131 11 kHzAO VO_NORM Diff Gain F = 0.67 Ic 32F8130 0.7 1.1 VIV32F8131 0.8 1.2 VIVAD VO_DIFF Diff Gain F = 0.67/c 32F8130 0.8 AO 1.15 AO VIVFB32F8131 1.0 AO 1.2AO VIVFrequency Boost at Ic(32F8130) FB(dB) = 20 log [0.0145· S_Code + 1] 0 9 dB0$ S_Code $ 127(32F8131) FB(dB) = 20 log [0.0173· S_Code + 1] 0 10 dB0$ S_Code $ 127--"FBA Frequency Boost Accuracy S_Code = 127 -1.5 +1.5 dBTGDO Group Delay Variation 0.2 Ic to Ic 32F8130 -2.5 +2.5 %Without Boost 32F8131 -2 +2 %Ic to 1.75 Ic -3 +3 %TGDB Group Delay Variation 0.2 Ic to Ic 32F8130 -2.5 +2.5 0/0With Boost 32F8131 -2 +2 %Ic to 1.75 Ic -3 +3 %Boost Resolution 0.25 dBVOF _N Filter Output Dynamic Range THD = 1% max, Normal Output 1 Vp-pI8-45

551 32F8130/8131Low-Power ProgrammableElectronic FilterELECTRICAL CHARACTERISTICS (continued)Unless otherwise specified recommended operating conditions apply. F _Code = 64, S_Code = O.PARAMETER CONDITIONS MIN NOM MAX UNITFilter Characteristics (continued)VOF _D Filter Output TH D = 1 % max, Differentiated 1 Vp-pDynamic RangeOutput-RIN Filter Diff Input Resistance 3.0 4.0 5.0 kQCIN Filter Input Capacitance 3.0 pFEOUT Output Noise Voltage BW = 100 MHz, o dB Boost 1.2 1.9 mVRms(VO_NORM) 50Q input~--._---- ----fC = Max fc max Boost 1.4 2.0 mVRms- --_ .. -----EOUT Output Noise Voltage BW = 100 MHz, o dB Boost 2.1 2.7 mVRms(VO_DIFF) 50Q input-~----_...fc = Max fc max Boost 2.5 3.4 mVRms._""""------10- Filter Output Sink Current 1.0 mA--- -------r---------10+ Filter Output Source Current 3.0 mARO Filter Output Resistance Output source current, 50 70 Q(Single ended)10+ = 1 mA--- --------r-------T1 SDEN Set-up WRT SCLK Falls 10 TC/2-10 ns--------------- -------------T2A SDEN Hold WRT SCLK "Falls 10 TC/4 ns------------- --"--------T2B SDEN Falls (rises for 8131) 25 nsprior to SCLK rises---- -----------T3 SDI Set-up WRT SCLK Falls 25 ns-- -T4 SDI Hold WRT SCLK Falls 25 ns-"-SCLK Period, TC 100 nsPower Supply Rejection Ratio 100 mVp-p from 10kHz to 30 40 dBVO_NORM10 MHz on VCA, VCD---Power Supply Rejection Ratio 20 30 dBVO_DIFFCommon Mode Rejection Ratio Yin = OVDC + 10 mVp-p from 30 40 dBVO_NORM10 kHz to 10 MHz-"-Common Mode Rejection Ratio 20 30 dBVO_DIFFBias: VO_NORM± VCC = 5V 2.40 2.75 3.10 VVin± 2.20 2.35 2.80 V--VO_DIFF± 2.40 2.75 3.10 V-------------~Normal Output Offset Variation F _Code switched from 12-127 -200 200 mV"-Differentiated Output Offset F _Code switched from 12-127 -200 200 mVVariation8-46

551 32F8130/8131Low-Power ProgrammableElectron ic FilterTABLE 1: Calculations (Typical change in 1-3 dB point with boost)Boost (dB) Gain@fc (dB) Galn@ peak (dB) fpeak/fc f-3dB/fc K0 -3 0.00 no peak 1.00 01 -2 0.00 no peak 1.21 0.162 -1 0.00 no peak 1.51 0.343 0 0.15 0.70 1.80 0.544 1 0.99 1.05 2.04 0.775 2 2.15 1.23 2.20 1.036 3 3.41 1.33 2.33 1.317 4 4.68 1.38 2.43 1.638 5 5.94 1.43 2.51 1.979 6 7.18 1.46 2.59 2.4010 7 8.40 1.48 2.66 2.85Notes: 1. Ic is the original programmed cutoff frequency with no boost2. 1-3 dB is the new -3 dB value with boost implemented3. Ipeak is the frequency where the amplitude reaches its maximum value withboost implementedI.e., Ic = 1 MHz when boost = 0 dBif boost is programmed to 5 dB thenf-3 dB = 2.20 MHzIpeak = 1.23 MHz11.8 .........1.61.41.2(j).2;1.0\>-roQ) 0.8£:)1 je = 250 kHz1\2 je = 700 kHz\3 je= 1.15MHz4 fe = 1.6 MHz5 je = 2.05 MHz6 je= 2.5 MHz~1\ \\ 3I0.60.4r---"'-- --~0.2 "- \. ,~ 5 6~0.0lOOk 200k 300k 400k 500k 700k 1 meg-----2meg 3meg 4meg 5megFrequency (Hz)FIGURE 3: Typical Normal/Differentiated Output Group Delay Response8-47

551 32F8130/8131Low-Power ProgrammableElectronic FilterPACKAGE PIN DESIGNATIONS(Top View)THERMAL CHARACTERISTICS: ejA16-Lead SOL I 100° C/WAGND216 VO_DIFF+15 VO_DIFF-VO_NORM+314 PWRONVO_NORM-VCAVIN-VIN+SDEN/SDENSDI4567813 SCLK12 VCD11 DGND210 VFP9 DGND116-Lead SOLSSI 32F8130: Lead 7 ::: SDENSSI 32F8131: Lead 7 = SO ENCAUTION: Use handling procedures necessaryfor a static sensitive component.ORDERING INFORMATIONPART DESCRIPTIONSSI32F8130 16-Lead SOLSSI32F8131 16-Lead SOLORDER NO.32F8130-CL32F8131-CLPKG.MARK32F8130-CL32F8131-CLNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1991 Silicon Systems, Inc.Patent No. 5,063,309Patent Pending Nos. (516717) (823067) 8-489195 - rev.

~+551 32F8144ProgrammableElectronic FilterJanuary 1994DESCRIPTIONThis custom integrated circuit incorporates a pulseequalizer of variable equalization and variable bandwidthwith a transfer function of a 2 zero/7 pole linearphase filter, as well as variable gain stages controlledby DACs. Equalization, gain and bandwidth changesare user-programmable via three serial lines to amicroprocessor. The equalizer is totally contained andcalibrating. It is realized in a high speed fully differentialmode. A seven pole linear phase equiripple ± 0.05degree filter forms the low-pass function. The cutofffrequency of the low-pass section is programmed via a7-bit serial shift register and can be programmed from7 to 27 MHz. Pulse slimming equalization uses twoprogrammable magnitude, opposite sign zeroes on thereal axis. Pulse slimming boost is from 0 to 9.5 dB atthefilter cutoff frequency using a 7 bit serial shift register.Gain can be programmed from 10 VN to 100 VN fornormal outputs and from 10 VN to 50 VN for differentiatedoutputs.FEATURES• Programmable filter cutoff frequency (7 MHz $;Ic $; 27 MHz) with no external components• ± 10% cutoff frequency accuracy• Programmable pulse slimming equalization(0 to 9.5 dB boost at the filter cutofffrequency)• Matched delay normal and differentiated lowpassoutputs• Differential filter inputs and outputs• Device idle mode (45 mW nom.)• +5V only operation• Supports constant density recording• Input stage gain control with DAC• Relative gain between normal and differentiatedoutputs controlled with serial portBLOCK DIAGRAMPIN DIAGRAMN- L-'.···.·.L . _---.l·L_ .___"VINvoDIFF+LZVONORM+ EXT CAP+ VCAVONORM-EXT CAP-VIN+vo DIFF- VONORM- AGNOVO NORM+YAPVBP~lK.•VO OIFF+ VCO •VO OIFF-SDENVFPRXSOlDGNO20-lead SOL0194 - rev. 8-49VCA vco AGNO OGNOCAUTION: Use handling procedures necessaryfor a static sensitive component.

SSI32F8144ProgrammableElectronic FilterFUNCTIONAL DESCRIPTIONThe SS132F8144, a high performance programmableelectronic filter, provides a low pass equiripple typeseven pole filter with matched normal and differentiatedoutputs with variable gain using DACs.The SSI32F8144 has seven control registers: A, B, S1,S2, F1, F2 and P registers. Register A contains fourbits, B is three bits, and P is one bit. S1, S2, F1, and F2contain seven bits. Register A controls the gain of theinput stage and register B controls the gain betweenthe normal and differentiated outputs. Since the F, Sregisters contain 7 bits, they require two data packetswhich must be loaded sequentially. S1-2 registers arefor high frequency boost. F1-2 registers are for cutofffrequency control. The P register is for power downcommand. The structure and command of each registerare described as follows.Data is loaded serially with MSB first. Each data packetcontains 8 bits. The first four bits (07 - D4) are designatedas address bits with 07 always a "don't care."The last four bits (03 - DO) are the data bits (see Table 1).The registers are loaded by using the serial port throughthe SOl, SDEN and SCLK pins.The SOl pin is the serialbit input. The SDEN pin is the control register enable.The SCLK is the control register clock. The packet istransmitted MSB (07) first.GAIN PROGRAMMINGThe input gain stage is programmed with register A(Register 4, R4). The A_Code programs this gain asfollows:Av(V/v)=100 A_Code151 ~ A Code ~ 15AN/AD = 2.0 B_Code = 6 (B2 = 1, B1 = 1, BO = 0)(B3 is a "don't care")CUTOFF FREQUENCY PROGRAMMINGThe filter cutoff frequency can be set from 7 to 27 MHz.The 7 -bit F _Code programs the cutoff frequency asfollows:F Codejc(MHz)=270---- 33~F _Code::; 127127SLIMMER HIGH FREQUENCY BOOSTPROGRAMMINGThe amplitude of the input signal atfrequencies near thecutoff frequency can be increased using this feature. Bycontrolling the DACS output, the boost can bedetermined. The amount of boost atthe cutoff frequencyis related to the OAtS output by the following formula:BOOST (dB) = 20 o log [0.01563(S_Code) +1].The 7-bit S_Code is loaded into S1 and S2 registers(registers 0 and 1 - RO, R1).POWER-DOWN CONTROLThe DO bit of the P register (register 7, R7) determiesthe power up/down state of the SSI 32F8144. Uponinitial power up, the DO bit of the P register should beinitialized to "1" for normal operation. 03 - 01 are "don'tcare."By programming DO to "0," the SSI32F8144 is switchedinto a power-down state, dissipating minimum idlepower. The filter is switched off. The serial port remainsactive awaiting the next command.This input gain stage is DC coupled to the filter corethrough DC restore circuitry. A large capacitor (1 J..LF) isplaced between pins EXT_CAP+ and EXT_CAP- tonull the input offset to the filter. Register B ( Register 5,R5) controls the relative gain between the normal anddifferentiated outputs. There are three discrete optionswhich are listed as follows:AN/AD = 1.0 B_Code = 3 (B2 = 0, B1 = 1, BO = 1)A_Code = 1AN/AD = 1.5 B_Code = 5 (B2 = 1, B1 = 0, BO = 1)A_Code = 78-50

SSI32F8144ProgrammableElectronic Filterclocks data bitSCLKLoad datainto appropriateregisterCRD HoldwrtCRC risesSDIFIGURE 1: Serial Port Timing RelationshipTABLE 1: Control Register AssignmentADDRESS BITSUSAGEDATA BITS07 06 05040302 01 DORO X 0 00S1 REGISTERXS6 S5 S4R1 X 0 01S2 REGISTERS3S2 S1 SOR2 X 0 10F1 REGISTERXF6 F5 F4R3 X 0 11F2 REGISTERF3F2 F1 FOR4 X 1 00A REGISTERA3A2 A1 AOR5 X 1 01B REGISTERXB2 B1 BOR7 X 1 11P REGISTERXX X POX = Don't CareS = Boost (Slimming) ControlF = Frequency (Bandwidth) ControlA = Gain Setting (0-10)B = Gain of VO_OIFF relative to the gain of Va_NORMP = Sleep Mode Control WO = 1, On Mode; PO = 0, Sleep Mode)SOl is the serial data input for an 8-bit control shift register. The data packet is transmitted Most Significant B~ (07)first. The first four bits are the register address, the last four are the data b~s. Registers larger than four bits mustbe loaded w~h two 8-b~ data packets. These packets should be loaded sequentially.I8-51

SSI32F8144ProgrammableElectron ic FilterPIN DESCRIPTIONNAMEVIN+, VIN-VO_NORM+,VO_NORM-VO_DIFF+VO_DIFF-SO ENDESCRIPTIONDIFFERENTIAL SIGNAL INPUTSDIFFERENTIAL NORMAL OUTPUTSDIFFERENTIAL DIFFERENTIATED OUTPUTSCONTROL REGISTER ENABLE. A logic LOW level allows CONTROL REGISTER CLOCKto clock data into the control registerviathe CONTROL REGISTER DATA input. A logic HIGHlevel latches the register data and issues the information to the appropriate circuitry. This isa TIL input.SCLKCONTROL REGISTER CLOCK. Positive edge triggered clock input for serial register. Thisis a TTL input.SOl CONTROL REGISTER DATA. This is a TTL input (see Figure 1).RXCURRENT SET RESISTOR. This external resistor to groJ,Jnd provides a reference current.(RX = 5 kQ ±1%) A 1000 pF capacitor must be connected in parallel with Rx.----VCAANALOG +5V SUPPLY.---------VCD DIGITAL +5V SUPPL Y.AGNDDGNDVAPVBPVFPEXTCAP+EXT CAP-LZANALOG GROUND.DIGITAL GROUND.---_ ...... ---------- ------~~----~--_ .. - --- --ANALOG TO DIGITAL TEST VOLTAGE. This is an analog voltage that is proportional to thesetting on the digital output on the AID convertor. This is a test pin related to the variable gain.BOOST PROGRAMMING VOLTAGE. A voltage that is related to the boost. A test pin.CUTOFF FREQUENCY PROGRAMMING VOLTAGE. A voltage that is related to the cutofffrequency. A test pin.EXTERNAL CAPACITOR. These pins are available for an external capacitor which is usedin a feedback network to null the input offset. CEXT ~ 0.47/-lF, 1.0 /-IF nominal.LOW 1M PEDANCE. This is a control signal which causes the input impedance of the filter tobe low when this pin is low. The impedance is high if the pin is open or in the high state. Thisis a TIL input.8-52

.-----~-- ---~ --_551 32F8144ProgrammableElectron ic FilterELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGSOperation above maximum ratings may damage the device.PARAMETERStorage TemperatureJunction Operating Temperature, TjSupply Voltage, VCCVoltage Applied to Inputs*Maximum Power Dissipation, fc = 27 MHz, Vcc = 5.5VT1 Lead Temperature (1/16" from case for 10 seconds)RATINGS-65 to + 150°C+130°C-0.5 to 7V-0.5 to VCCV.55W260°C* Analog input signals of this magnitude shall not cause any change or degradation in filter performance aftersignal has returned to normal operating range.RECOMMENDED OPERATING CONDITIONSSupply voltage, VCC 4.50 < VCC < 5.50 V --Ambient Temperature 0< Ta < 70 °CTj Junction Temperature 0< Tj < 130 °C-ELECTRICAL CHARACTERISTICSUnless otherwise specified recommended operating conditions apply.PARAMETER CONDITIONS MIN NOM MAX UNITSIdle Mode Current PO = "0" 11 15 mASupply Current Vcc = 5.5V 85 100 rnAPD Power Dissipation PO = "0"--_.-45 71.5 mWPO = "1" 400 550 mWIdle to Active Mode Recovery Time------ -------- "---50 IlsSerial port program to output 50 Ilsresponse time--_..•-DC Characteristics- ----,------VIH High Level Input Voltage TIL input 2.0 V1---VIL Low Level Input Voltage 0.8 VIIH High Level Input Current VIH = 2.7V 20 !lA--ilL Low Level Input Current VIL = OAV -1.5 mA--------Filter Characteristics-- --- -fc Filter Cutoff Frequency 33:E; F _Code:E; 127 7 27 MHz...I8-53

SSI32F8144ProgrammableElectronic FilterELECTRICAL CHARACTERISTICS (continued)Unless otherwise speci T Ie d recommende d operating conditions apply.PARAMETERCONDITIONSFCA Filter fc Accuracy Over full fc range,33::; F _Code::; 127AOVa_NORM Diff Gain (Note) F=0.67fcAD VO_DIFF Diff Gain (Note) F = 0.67 fc, set with serial portVO_NORM Gain Tolerance Ao = 100VO_DIFF Gain Tolerance Ao =50FB Frequency Boost at fc FS(d8) = 20 log [.01563 (S_Code) +1]FBA Frequency Boost Accuracy o to 9.5 dBTGDO Group Delay Variation 0.2 fc - fCWithout Boostgdm = group delay magnitudefc - 1.75 fcTGDB Group Delay Variation 0.2 fc - fCWith Boostfc - 1.75 fcVOF Filter Output Dynamic- Range Vo_NORM, THO = 1.5%RINCINFilter Diff Input ResistanceFilter Input CapacitanceVo_DIFF, THO = 2.0%Va_NORM, THO = 2.0%Vo_DIFF, THO = 3.0%EOUT Output Noise Voltage BW = 100 MHz, o dB Boost(VO_NORM)50Q inputfc = 27 MHz 9.5 dB BoostEOUT Output Noise Voltage BW = 100 MHz, o dB Boost(VO_DIFF)50n inputIc = 27 MHz 9.5 dB Boost10- Filter Output Sink Current10+ Filter Output Source CurrentRO Filter Output Resistance 10+ = 1 mA(Single ended)SCLK Period, TCSDEN Set-up WRT SCLK Rising EdgeSDEN Hold WRT SCLK Rising EdgeMIN NOM MAX-10 1010 10010 50-15 15-15 150 9.5-1.25 +1.25-2% +2%gdmgdm-3% +3%~dmgdm-2% +2%gdmgdm----3% +3%gdmgdm111.51.53.0 3.5 4.072.5 4.01.03.03.7 104.4 67.8 1430 5010010 255 TC/2-10UNITS0/0VIVVIV0/00/0dBdBnsnsnsnsVppVppVppVppkQpFmVrmsmVrmsmVrmsmVrmsmAmAnnsnsnsNote:The overall gain of VO_DIFF with respect to VIN is 10 to 50 VIV. Additionally, the gain ofVO NORM with respect to VO DIFF will be adjustable and have gain values of 1.0, 1.5 and 2.0.8-54

...SSI32F8144ProgrammableElectronic FilterELECTRICAL CHARACTERISTICS (continued)Unless otherwise specified recommended operating conditions apply.PARAMETERSDEN Rises Prior to SCLK FallsCONDITIONSMIN15NOM MAX UNITS_.nsSOl Set-up WRT SCLK Rising Edge15nsSOl Hold WRT SCLK Rising Edge15nsPower Supply Rejection Ratio100 mVpp in VCA, VCD from100 kHz to 10 MHz4570 dBCommon Mode Rejection RatioDC Bias: VOJ,JORM+, VO_NORM-VO_DIFF+, VO_DIFF-Vin+, Vin-VIN = 0 VDC + 100 mVpp from100 kHz to 10 MHzVCC = 5V, single ended402.052.565 dB--2.55 3.05 V- ~.-.-3.0 3.5 V-Delay mismatch normal anddifferentiated outputs1 nsTABLE 2: CalculationsTypical change in j-3 dB point with boostBoost (dB) Gain@fc (dB) Gain@ peak (dB) fpeak/fca -3 0.00 no peak1 -2 0.00 no peak2 -1 0.00 no peak3 0 0.15 0.704 1 0.99 1.055 2 2.15 1.236 3 3.41 1.337 4 4.68 1.388 5 5.94 1.439 6 7.18 1.4610 7 8.40 1.48f-3dB/fc K1.00 01.21 0.161.51 0.341.80 0.542.04 0.772.20 1.032.33 1.312.43 1.632.51 1.972.59 2.402.66 2.85INotes: 1. jc is the original programmed cutoff frequency with no boost2. j-3 dB is the new -3 dB value with boost implemented3. jpeak is the frequency where the amplitude reaches its maximum value withboost implementede.g., jc = 9 MHz when boost = 0 dBif boost.is programmed to 5 dB thenf-3 dB = 19.8 MHzjpeak = 11.07 MHz8-55

551· 32F8144ProgrammableElectronic FilterINPUT1.31703S2+ S 1.68495 + 1.317032.95139S2+ S 1.54203+ 2.95139S2+ S 1.68495 + 1.31703Normalized for roc = (2n) Ic = 1AN and AD are adjusted for unity gain (0 dB) at F = 0.67 IcDenormalize the frequency by substituting S ~ (S/2njc)Eq for Ic = 27 MHz, S = S / [(2n)(27 x 10 6 )]FIGURE 2: 32F8144 Normalized Block DiagramPACKAGE PIN DESIGNATIONS(Top View)THERMAL CHARACTERISTICS: 8ja20-lead SOL20-Lead SOYEXTCAP+EXT CAP-[ZVONORM-VONORM+VBPVO OIFF+VO OIFF-VFPVCAVIN+VIN-AGNOYAPSCLKVCOSO ENSOlCAUTION: Use handling procedures necessary'for a static sensitive component.RX20-lead SOL, SOYOGNOORDERING INFORMATIONPART DESCRIPTION ORDERING NUMBER PACKAGE MARKSSI32F8144 20-Lead SOL (300 mil) 32F8144 - CL 32F8144 - CLSSI32F8144 20-Lead SOY (220mil) 32F8144 - CV 32F8144 - CVPreliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations andare not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1993 Silicon Systems, Inc.Protected by the following patents: (5,182,477), (5,063,309)Patent Pending: 710, 512 8-560194 - rev.

Section 9APPLICATION NOTES& GLOSSARYI9

9-0

K-SeriesApplication InformationJanuary 1994GENERAL CONSIDERATIONSFigures 1 and 2 show basic circuit diagrams forK-Series modem integrated circuits. K-Series productsare designed to be used in conjunction with a controlprocessor, a UART or RS-232 serial data interfaceand a DAA phone line interface to function as a typicalintelligent modem. The K-Series ICs interface directlywith I ntel8048 and 80C51 microprocessors for controland status monitoring purposes. Two typical DAAarrangements are shown: one for a split ±5 or±12 voltdesign and one for a single 5 volt design. Thesediagrams are for reference only and do not representproduction-ready modem designs.K-Series devices are available with two control interfaceversions: one for a parallel multiplexed address/data interface, and one for a serial interface. Theparallel version is intended for use with 8039/48 or8031/51 microcontrollers from Intel or many othermanufacturers. The serial interface 22-pin version canbe used with other microcontrollers or in applicationswhere only a limited number of port lines are availableor the application does not lend itself to a multiplexedaddress/data interface. The parallel versions may alsobe used in the Serial mode, as explained in the datasheet pin description.In most applications the controller will monitorthe serialdata for commands from the DTE and the receiveddata for break signals from the far end modem. In thisway, commands to the modem are sent over the sameline as the transmitted data. In other applications theRS-232 interface handshake lines are used for modemcontrol.RS232LEVELCONVERTERSCACSCCCDRTSCTSDSRDTRWRALE 551DCDCF os K-SERIESLOWPOWERFAMILYC2300 pFCl390 pFBASSDADODBTXDRXCLKTXCLKUS. U6MC145406JVRlMOVV2S0L20I+5?~22KiFIGURE 1: Basic Box Modem with Dual-Supply Hybrid01949-1

K-SeriesApplication InformationDIRECT ACCESS ARRANGEMENT (DAA)The telephone line interfaces show two examples ofhow the "hybrid" may be implemented. The split supplydesign (Figure 1) is a typical two op-amp hybrid. Thereceive op-amp serves two purposes. It supplies gainto amplify the receive signal to the proper level for themodem's detectors and demodulator, and it removesthe transmitted signal from the receive signal presentat the transformer. This is done by supplying a portionof the transmitted signal to the non-inverting input ofthe receive op-amp at the same amplitude as the signalappearing .at the transformer, making the transmitsignal Common mode.The single-supply hybrid is more complex than thedual-supply version described above, but its use eliminatesthe need for a second power supply. This circuit(Figure 2) uses a bridged drive to allow undistortedSignals to be sent with a single 5 volt supply. BecauseDTMF tones utilize a higher amplitude than data, thesesignals will clip if a Single-ended drive approach isused. The bridged driver uses an extra op-amp (U1 A)to invert the signal coming from the gain setting op-amp(U1 B) before sending it to the other leg of the transformer.Each op-amp then supplies half the drive signalto the transformer. The receive amplifier (U1C) picksoff its signal at the junction of the impedance matchingresistor and the transformer. Because the bottom leg ofthe transformer is being driven in one direction by U1 Aand the resistor is driven in the opposite direction at thesame time by U1 B, the junction of the transformer andresistor remains relatively constant and the receiveSignal is unaffected.C1390pFC30.1 nF@)---11--------------"----RING ~--------------------------------~FIGURE 2: Single 5V Hybrid Version9-2

K-SeriesApplication InformationDESIGN CONSIDERATIONSSilicon Systems 1-chip modem products include allbasic modem functions. This makes these devicesadaptable for use in a variety of applications, and aseasy to control as conventional digital busperipherals. Unlike digital logic circuitry, however, modemdesigns must properly contend with precise frequencytolerances and very low level analog signals, toensure acceptable performance. Using good analogcircuit design practices will generally result in a sounddesign. Following are additional recommendationswhich should be taken into consideration when startingnew designs.CRYSTAL OSCILLATORThe K-Series crystal oscillator requires a Parallel mode(antiresonant) crystal which operates at 11.0592 MHz.It is important that this frequency be maintained towithin ±0.01% accuracy.In order for a Parallel mode crystal to operate correctlyand to specification, it must have a load capacitorconnected to the junction of each of the crystal andinternal inverter connections, terminated to ground.The values of these capacitors depend primarily on thecrystal's characteristics, and to a lesser degree on theinternal inverter circuit. The values used affect theaccuracy and start up characteristics of the oscillator.LAYOUT CONSIDERATIONSGood analog/digital design rules must be used tocontrol system noise in orderto obtain highest performancein modem designs. The more digital circuitrypresent on the PC board, the more this attention tonoise control is needed. The modem should be treatedas a high impedance analog device. A 22 mF electrolyticcapacitor in parallel with a 0.1 mF ceramic capacitorbetween VDD and GND is recommended. Liberaluse of ground planes and larger traces on power andground are also highly favored. High speed digitalcircuits tend to generate a significant amount of EMI(Electro-Magnetic Interference) which must be minimizedin order to meet regulatory agency limitations.To accomplish this, high speed digital devices shouldbe locally bypassed, and the telephone line interfaceand K-Series device should be located close to eachother near the area of the board where the phone lineconnection is accessed. To avoid problems, powersupply and ground traces should be routed separatelyto the analog and digital functions on the board, anddigital signals should not be routed near low level orhigh impedance analog traces. The analog and digitalgrounds should only connect at one point near the K­Series device ground pin to avoid ground loops. The K­Series modem IC's should have both high frequencyand low frequency bypassing as close to the packageas possible.For additional applications information consult the SiliconSystems K-Series Modem Design Manual.ISilicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-69140194 - rev.9-3Protected by the following Patents (4,691,172) (4,777,453)©1989 Silicon Systems, Inc.

Notes:9-4

APPLICATION NOTESetting DTMF Levels for1200 Bitls K-Series ModemsSome applications of the K-series modems without output level adjustment may require setting the DTM F transmitlevel to something other than the normally transmitted level. This level is nominally about 5 dB higher than duringdata transmission. If the data is transmitted at -10dBm, the DTMF levels will be at about -5 dBm, which is adequatein most applications.The simplest way to change the relative levels of DTM Ftones and data is to change the transmit gain during dialing.This can be accomplished as shown below. In this example, it is assumed that the DTMF tones are to betransmitted at a higher level than normal. Closing relay K2 will increase the gain of the transmit op-amp and allowa higher DTMF tone level during dialing. If it is desired to decrease the DTM F level, the relay can be open for dialingand closed for data. The value of the shunt resistor, Rdtmf, will be relatively large compared to the resistor R1,therefore the precision of Rdtmf is not as critical as R1. This means an analog switch or similar device could beused instead of a relay, with the on resistance of the switch not seriously affecting the tolerance of the gain setting.+5VTO CONTROL", ____ t~K2-----. Rdtmi750 pF14.3 kz 1%TXARXAr10kzHOOK~

APPLICATION NOTESSI73K212A High SpeedConnect SequenceORIGINATING MODEM~508-626ms ~DSR ---+l i+== 100 - 200 ms :------~I--~ITOIII IGNORED IORIGINATING MODEM TRANSMITS SCRAMBLED MARKS IN LOW BAND I DATA, 231 - 308 ms I IDCD 1'4 .: CTS: ~:.----- 774 ms ----~.~:W!l%tN\ihlRD CLAMPED TO MARK UNCLAMPEDI@)II\ //® 1 231 -308ms (©ANSWERING MODEM !IIII.-f------_. •.;.I.-t------- 774 ms ----~ANSWERING MODEM TRANSMITS 2225 HzSCRAMBLED MARKS IN HIGH BANDDSR ALREADY ONBOTH DCD & CTS I@)TOTRANSMIT DATA INPUT IS IGNORED WHILE CTS IS OFFRDRECEIVED DATA OUTPUT IS CLAMPED TO MARK WHILE DCD IS OFF9-6

APPLICATION NOTEV.22 & V.22bisConnect SequencesV.22CALLING MODEMCALLING MODEM TRANSMITS SCRAMBLED BINARY ONES IN LOW BANDTDDSRI+--- 456 ±10 ms ~I~ 155±50msIGNOREDDCD:. 270 ±40 ms .1': ., '~,.~----~765 ±10 ms ----~.;:"""I =":-=::O=/A=;rA=)=H=UjRDCLAMPED TO BINARY ONE0;ANSWERING MODEM©:270±40ms ,~..... r------ 765±10 msUNCLAMPLEDRECEIVED DATAUNSCRAMBLED BINARY ONE IN HIGH BAND SCRAMBLED BINARY ONE IN HIGH BAND DATABOTH DCD & CTS ITOTRANSMIT DATA INPUT IS IGNORED WHILE CTS IS OFFRD RECEIVED DATA OUPUT IS CLAMPED TO BINARY ONE WHILE DCD IS OFF UNCLAMPED DATAV.22bisCALLING MODEM~: :.-- 100 ±3 msr---~----------------------------------+'~~~~~+-------------'SCRAMBLED BINARY ONES AT 1200 BITISDATA,:111---- ....600±10ms .'IDATARATE ~ :---J SEiECTOR ,~ 450 ±10 ms ----.:,IIDCDCTSTD TRANSMIT DATA INPUT IS IGNORED F~~tA@rMM$M'tt$9tl---------------------------------------~-~BEGIN 16·WAYDECISIONS ~:RD RECEIVED DATA OUPUT IS CLAMPED TO BINARY ONE IN RECEIVER9-7UNCLAMP I DATA I~: :.--DETECT 32 CONSECUTIVE 81TSOF BINARY ONE AT 2400 81T/S

APPLICATION NOTERemote LoopHandshake SequenceRESPONSEBegin in online stateTRANSMIT UNSCRAMBLEDMARK AT BIT RATERxD is weak pullup (TONE bit D7)Disable CTSForce Transmit Mark (CRl bits D7 & D6)Bypass Scrambler (CRl bit D4)START...... - .. "" I Begin in online stateMonitor Unscrambled Mark (DET bit D4)Validate for 200 msContinue if detect occursWAIT FOR DOTTINGRead Receive Data (DET bit D5)Wait for 250 ms of dotting (1/0) or timeoutof 600 ms occursIf timeout, return to onlineTRANSMIT DOTTING PATTERNDISABLE TERMINALRxD to weak pullup (TONE bit D7)Disable CTS, DSR and DCD; Ignore DTRTRANSMIT SCRAMBLED MARKLOOP DATAEnable Scrambler (DET bit D4)....----------1II{l1Jll1lliif'==v1 Select RDL (CRl bits Dl & DO)If synchronous, select slave modeWAIT FOR LOOPED DATA(CRO bits D5 - D2)Read Received Data (DET bit D5)Wait for 250 ms of MarkFINISH CONNECTIONUnclamp RxD (TONE bit 7)Enable CTSTERMINATIONTERMINATIONPULSE CARRIERDisable Transmit (CRO bit Dl)Wait for 80 msEnable Carrier (CRO bit Dl)Return to onlineDETECT CARRIER1iii""=""i:¥1 Wait for Carrier Loss (DET bit D3)Enable CTS and DSRRemove Data Loop (CRl bits Dl & DO)Wait for Carrier Return (DET bit D3)If no carrier in 200 ms, abort callENABLE TERMINALRemove Data Loop (CRl bits Dl & DO)Unclamp RxD (TONE bit D7)Enable DCD; stop ignoring DTRReturn to online9-8

APPLICATION NOTE551 73K224LRetrain at 2400REQUESTSTARTS WITH BAD DATAREQUEST RETRAINRESPONSERESPOND· RETRAINDeactivate CTSClamp RxD (TONE bit 7)INITIALIZEDETECT S1 RESPONSEDetect S 1 for 60 ms (DET bit 06)Wait 50 ms and Initialize the AdaptiveEqualizer (Pulse CR2 bit DO)DETECT S1 REQUESTDetect S1 for 60 ms (DET bit 06)Wait 50 ms:Deactivate CTSForce S1 transmit at 1200 bitls for100 ms (CRO bit 06, CR1 bitsD7 & D6, CR2 bit D4)Clamp RxD (TONE bit D7)Initialize the Adaptive Equalizer(Pulse CR2 bit DO)SCRAMBLED MARKSCRAMBLED MARKForce Scrambled Mark(CR1 bits 07 & 06)Wait 450 ms from the end of S 1 receiptand begin 16-way decisions (CR2 bit 03)FINISHAfter600msofScrambiedMarkat1200 bitlsTransmit at 2400 bitls (CRO bit 06)Detect 32bits of Mark at 2400 (DET bit D5)Unclamp RxD after 200 ms of Mark at2400 bitls (TONE bit D7)Activate CTSFINISHDetect 32 Marks at 2400 bitls (DET bit D5)Unclamp RxD (TONE bit D7)After600msofScrambiedMarkat 1200 bitlsTransmit Marks at 2400 bitls for 200 ms(CRObit 06)Unclamp TxD (CR1 bits D7 & 06)Activate CTSI9-9

IAPPLICATION NOTESSI 73K212 & 73K222Originate Handshake Sequence(RXDis in tri-state mode, TONE bit D7~ 1)DIAL1 . Go off hook2. Bring out of power down mode (CRO bits 05-02)3. Set OTMF tone (Tone bits 04-00)4. Turn on transmitter (Set CRO bit 01)5. Wait OTMF on time6. Turn off transmitter (Clear CRO bit 01)7. Wait OTMF off time8. Repeat 3-7 for all digitsWAIT FOR CARRIER1 . Start S7 (Wait for carrier) timeout2. Set to Bell 103 originate mode(Set CRO bits 05-00 to 110001)3. Wait for carrier detect bit (DR bit 03) to come on4. Start sliding window counter (Wait throughpossible 2100 Hz answe r tone period)5. Qualify RXO mark* for 150 ms (DR bit 05) todetect answer modem (Carrier detect bit mustalso be on)6. Raise OSR~ FSK1. Wait 100-200 ms2. Raise OCO, start 755-774 ms timer; wait 426-446 ms, send FSK marks(Set CR1 bits 07 & 06to 10, set CRO bit 01)3. At end of 755-774 ms timer period (started in #2 above); raise CTS, unclampRXO & TXO from marking (clear TONE bit 07; clear CR1 bits 07 & 06)--- DPSK1. Wait 456 (V.22) or 508-626 ms (212A), switch to OPSK2. Send scrambled marks (Set CR1 bits 07 & 06 to 10)3. Qualify scrambled marks from answer modem for 150 ms4. Wait for 231-302 ms of scrambled marks, raise OCO5. Enable RXO (Tone bit 07)6. Wait 774ms, raise CTS, enable TXO (Clear CR1 bits 07 & 06)*This may be either answer tone from a Bell modem or unscrambled marks from a V.22 modem9-10

APPLICATION NOTESSI 73K212 & 73K222Answer Handshake Sequence(RXD is in tri-state mode, TONE bit D7=1)If Answer Modem is BELL 212A/1 031. Go off hook at end of ring cycle2.Raise DSR3. Wait 2 seconds4.Send 2225 Hz (Set TONE bit 05,clear bit ~O, set CRO bits 04-00)FSKIIf Answer Modem is CCITT V.221. Go off hook at end of ring cycle2. Wait 2 seconds3. Send 2100 Hz for 3.3 seconds(Set TONEbits 05 &01, CRO bits 04-00)4. Silence for 75 ms(Clear CRO bit 01, TONE bits 05 &00)5.Raise OSR6.Send unscrambled marks at 1200 bitls(Set CR1 bit 04, CRO bit 01)1. When carrier is detected, start sliding window counters for FSK & DPSK.~ 2.Monitor DR bit 05; change modes between FSK and OPSK if DR bit 05 is zero. I--3.Continue until one window counter reaches zero. Proceed in that mode.IDPSKWait for FSK marks for 150 ms1.Raise CTS2.Wait 100-200 ms or "S9" time, raise OCO3.Enable RXO, TXO (Tone bits 07 & 05)4.Send DataWalt for DPSK marks for 270 ms1.Send Scrambled Marks for 770 ms (CR1 07 & 06=10)2.Raise CTS and OCO or wait "S9," raise OCO3. Enable RXO (TONE bit 07)Enable TXO (CR1 bits 06 & 07=00)4.Send DataI9-11

IAPPLICATION NOTESSI 73K224L OriginateHandshake SequenceRef. CCITT Red Book V.22bis Specificationset speed to 600DIALGooffhookTurn chip power on (CRO bits 02)Set OTMF tone (TONE bits 04-00)Turn on transmit (CRO bit 01)Wait required timeTurn off transmit (clear CRO bit 01)Wait required timeRepeat for all tonesClear OTMF bits in tone registerCheck CarrierFor 4 sec. look for valid tone:tone valid when 95 ms of 2225 Hztone valid when 133 ms of SOthen wait 450 msData Pump InitializationTristate recover dataDefault to asyncDefault 1 O-bit asyncReset equalizer (CR2 bit 0)Turn on OSP (CR2 bit 2)Put OSP in CAlLINIT mode(CR2bit5)Reset receive gain bitTurn off guard tonesSet speed to 1200Enable 4-way decisionDisable scramblerNOwhen valid 2225 or SOput OSP in demod modeNOwhile waiting for 100 mssend S1look for S1if receiving S1then turn on scramblersend marksFSKSelect FSK mode(CRO bits OS, 04)Enable OSR and DCOForce transmit marks(CR7 bits 07, 06)Enable transmit (CRO bit 01)Unclamp RXO (TONE bit 07)Wait 765 msUnclamp TXO (CR1 bits 07, 06)Activate CTSEnable receive data2400, found S1Wait for S1 to go awayEnable equalizerWait 450 msSet 16-way decisionsWait 150 msSet speed to 2400Wait 200 ms before enabling CTSQualify 8 baud times of marksEnable optional Sync modeEnable carrier tracking in softwareEnable data mode in transmitterSend dataEnable receive data600/1200, found marksTurn on scramblerTurn on equalizerEnable transmitForce markCheck receiver levelTurn on equalizerWait 765 msEnable optional sync modeStart carrier tracking in softwareEnable data mode in transmitterSend dataEnable receive data9-12

APPLICATION NOTESSI 7,3K224L AnswerHandshake SequenceRef. CCITT Red Book V.22bis SpecificationData Pump InitializationTristate receiver dataDefault to asyncDefault 1 O·bit asyncReset equalizer (CR2 bit 0)Turn on DSP (CR2 bit 2)Put DSP in CALUNIT mode(CR2 bit 5) demodReset receive gain bitTurn off guard tonesSet speed to 1200Enable 4·way decisionDisable scramblerSet default to marksCheck and set guard tonesTurn on transmitterAssert DSRNOTurn on scramblerDelay 350 msTurn on 16·way decisionsBegin looking for 32 consecutive marksWait 150msWhen 32 marks received assert DCDSend QAM marksWait 200 msEnable receive dataEnable optional sync modeStart carrier tracking in softwareEnable data mode in transmitterSend dataset tone bit to 2100 HzNO60011200, found marksTurn off answer toneTurn off transmitterSet default for scrambled marksEnable transmitterEnable equalizer in receiverWait 750 msEnable receive dataEnable optional sync modeStart carrier tracking in softwareEnable data mode in transmitterSend dataFSK'>-----+-------..,.. Disable call init modeSet speed to 300Equalizer should be offDisable scramblerSend marksTurn on transmitterReceive 155 ms of marksCheck receive gain levelWait 450 msAssert DSRStart carrier tracking in softwareEnable data mode in transmitterSend Data9-13I

APPLICATION NOTETroubleshootingthe Modem DesignExcerpt from the Silicon Systems K-Series Modem Design ManualPossible Causes of a Totally Dead SystemIt is always particularly depressing when youpower-up a new design for the first time and absol utelynothing happens. However, this is often the easiesttype of fault to find. We will try to think of a few thingsthat could cause this problem (apart from the obvious,like the plug falling out of the wall socket).The K-Series Modem IC is Stuck in the ResetStateYou will generally get very little cooperation froma K-Series modem IC while it is in the power-downstate. It enters this state when a reset operation isperformed, either by writing to the Reset bit (bit 2) inControl Register 1 or by taking the RESET input pin tologic ONE. Make sure that your firmware is bringingthe part out of this state by writing something otherthan all ZEROs to bits 5 to 2 in Control Register O. Also,make sure that this happens after the RESET pin hasbeen returned to logic ZERO. A capacitor from this pinto VDD can hold the part in the reset state for manyseconds. Attempts to program the part during thistime will not take effect. For products with a DSP,check that the RESET DSP bit (CR2 bit D2) is alsowritten with ONE when appropriate.Crystal Oscillator Falls to StartIf a complete crystal oscillator is used to directlydrive the K-Series modem, any starting problem shouldbe addressed to the manufacturer of that device. If theinternal oscillator is used with a crystal, there may besituations in which it will not start. Check the values ofthe capacitors from XTLl and XTL2 to ground. If theseare too high in value, 40 pF or above, the oscillator maynot start. Such large values are not recommended andshould not be necessary if the crystal is correctlyspecified. Also ensure thatthe circuit board is designedto minimize stray inductance and capacitance in thearea of the oscillator. The crystal and both capacitorsshould be placed as close as possible to the XTL pins ofthe K -Series modem IC and connected by direct traces.The ground connection of the capacitors should be viawide traces to the digital grounding system. It is alsopossible that the oscillator will not start or will be slowto start if the risetime of the power supply voltage isvery long. The starting properties are helped by theasymmetry in the load capacitor values, the capacitorat XTL 1 should be about twice as large as that at XTL2.Clock to Microcontroller Isn't Getting ThroughUsing the K-Series modem ICs on-chip clockoscillator to generate timing for the entire system isvery efficient from the point of view of componentcount and EMI generation. However, note that theCLK output of the modem chip is specified only todrive TTL compatible inputs. Many commonmicrocontrollers require clock inputs that rise closer tothe supply voltage for logic ONE. We have seenapplications which use the CLK pin to drive theseinputs without problem, however, the low-power (5Vsupply) parts may give a lower logic ONE level than isnecessary at elevated temperature. We recommendthat you use a TTL to CMOS level converting bufferbetween the CLK pin and the controller clock input in5V systems. A pull-up resistor to the SV supply is noteffective in increasing the logic high voltage. In somecases capacitive coupling to a CMOS input is also effectiveif the controller clock input is properly biased.Connect Handshake FailsIf your system seems to be working well but cannotget into the situation of exchanging data with anothermodem, it is likely that you have a problem in theconnect handshake. It is better to examine handshakeproblems using a "known good" modem at the remoteend rather than another of your own systems. Thishelps isolate problems if more than one are present.Use a modem from an established and reputablemanufacturer, as discounted generic modems may notconform fully to established specifica tions. Dependingon the modulation mode, there may be many or fewopportunities to fail so we can only offer generalpointers to problems we have encountered in the past.It is very helpful to build extra diagnostic code into thehandshake to diagnose unexpected conditions.9-14

If things never start, check that the initial set-up ofthe chip is correct. The chip must be taken out ofpower-down before it will do anything and in DSPbasedchips the DSP must have been reset after anyprevious call and then taken out of the reset state. (ADSP-based part cannot be used in a non-DSP socketwithout many such changes to the controller code;watch this when upgrading a 73K222 system to use a73K224L.) If in CALLINIT mode the answer tone is notdetected, check that you have selected the desiredanswer tone frequency by programming in the ToneRegister. The selectivity of the answer tone detector isquite high, so verify that your answering modem isgenerating a frequency within the specifications of themodulation standard. You should be able to verify theoperation of your various signal detectors withbreakpoints in the controller code. If these do not fireat the appropriate point, the handshake is likely tohang-up or get out of step with the other modem. Beespecially careful with the S1 detector, if this is failingyou may get connections at 1200 bit/ s which weresupposed to be at 2400 bit/ s. With DSP-based chips inQAM or DPSK modes, make sure that you are enablingthe adaptive equalizer at the appropriate time. Enablingit too early, when the received signal is unsuitable fortraining, and too late, when there is too little time leftbefore the gearshift to 2400 bit/ s, can both give connectproblems. Finally, make sure the crystal oscillatorfrequency is in specification as a gross error here cancause failure of the handshake.Errors Committed Immediately After Handshake,With Later ImprovementWe have seen situations in which a K-Seriesmodemmakes many data errors during the first few seconds ofa connection, butthen shapes up and performs normallythereafter. This is generally due to some problem inequalizer training in a DSP-based chip. The equalizermust be held in the initial state (bit 0 of CR2 = ZERO)up to the point in the handshake when scrambledDPSK binary ONES first appear at the receiver. It mustthen be released promptly (bit 0 of CR2 = ONE) andallowed to adapt so that it is fully trained before thegear shift to 2400 bit/ s and the transition to data modeoccurs. Enabling the equalizer too early will cause it totrain on an unsuitable unscrambled signal. Because itadapts more rapidly immediately after being enabled,it may take a long time to recover from a bad solutionwhen the correct receiver signal arrives. Enabling theequalizer too late reduces the time available for trainingbefore the received data is relied upon to be correct. Ifyou have to put the equalizer back into the initializedstate after a period of training, make sure that EqualizerEnable (bit 0 of CR2) stays at ZERO for at least 2 ms. Itis better to have the Receiver Gain Boost bit dealt withbefore the equalizer is enabled, otherwise transientscaused by changing this bit may upset the equalizersolution.Errors Experienced at High Receive SignalLevelsIf the error rate gets worse at high receive signallevels, you should look for some source of clipping inthe receive path. Injecting a signal of known level at theline coupling transformer and looking at the RXA pinwith an oscilloscope should enable you to isolate anyproblem in the line interface. Look for excessive gain inthe receiver buffer amplifier or other causes of clippingat this point such as badly chosen op-amps for single5V supply operation. If the signal at RXA looks goodand you are using a DSP-based modem chip, it ispossible that the controller is incorrectly inserting the12 dB receiver gain boost even if the Receive Level bitin the Detect Register is set. Note that early data sheetsfor the 73K224L gave this bit the wrong sense, i.e., ONEfor low level. Only set Receive Gain Boost if this bit isZERO.Errors Experienced at Low Receive Signal LevelsThere can be many causes of data errors at lowreceive signal levels, almost all associated with thepresence of some level of interference or noise in thereceive path. If you are performing tests over thetelephone network, make sure that the error rate youare experiencing is not to be expected from thebackground noise level on the line. It is best to use a linesimulator or a direct connection through anattenuatorif looking for system noise problems. The capacitoracross the feedback resistor of the receiver bufferamplifier is important to attenuate out-of-band noiseat the modem chip receiver input.Distortion in the telephone line interface can belocated by injecting low-level signals into the lineterminals and examining the signal at the RXA pinwith a spectrum analyzer. Look for crossover distortionin the receiver buffer amplifier. This can arise from apoorly chosen op-amp type, such as the LM324 whichmakes a transition from class A to class AB operationat low signal levels and is not suitable for thisapplication. We have found LM348 and LM1458 typeop-amps to be free from this problem. It is also possiblefor the line coupling transformer to introduce harmonicdistortion, particularly when a large D.C. holdingcurrent is flowing.In the absence of significant distortion, look for ahigh noise level at the RXA pin. Another symptom ofthis problem, apart from data errors, is that the CarrierDetect bit (bit 3 in DR) comes on or blinks when nosignal is applied to the modem receiver. The systemmay also fail to disconnect at the end of a call. If this isI9-15

your experienced on' t confine your search to the normalcarrier bandwidth because the modern chip will alsobe susceptible to higher frequencies. Op-amps may benoisy or may self-oscillate at low level due to poorlayout. If the op-amps themselves are not causing thenoise, it may be due to poor circuit layout or grounding.If, finally, nothing suspicious is visible at the RXA pinthen the noise must be getting into the receive signalinside the modern Ie. This can be from the powersupply and bias pins or from signals routed under thechip. Check the connections to GND, VDD, VREF andISET pins for component values and placement androuting of decouplingcomponents. You are more likelyto have problems with supply noise if you are using aswitching power supply. Look also for fast digitalsignals routed under the modern IC; these should bere-routed and a ground plane placed under the chip.Serious interference pickup problems can be createdby two crystal oscillators producing beat frequenciesin-band to the modern. We strongly recommend usingone master crystal in the system. Check the gain in thereceive path from the line terminals and, in DSP-basedparts, the state of the Receive Gain Boost bit set by thecontroller. If either of these are incorrect, then noise inthe chip will appear more significant compared to thesignal.The transmitter of the modern can be a source ofnoise in the receiver. It should not generate signals thatare in-band to the receiver, but this can happen ifeither the buffer amplifier or the line transformer arecausing harmonic distortion. This will be mostnoticeable in call mode, when the low band transmitsignal has harmonics in the high band filter of thereceiver. For 5V only systems, the choice of op-amps inthe buffer amplifier and their D.e. bias point is crucialto obtaining a sufficient voltage swing withoutdistortion. Because of its internal operation, a smallamount of switching noise is present at the TXA pin.The capacitor across the buffer amplifier feedbackresistor is important to prevent this signal from reachingthe recei ver. It is difficult to obtain good rejection of thetransmit signal at the receiver for all practical lineconditions, but you should check that your four-wireto two-wire hybrid circuit is operating correctly. Formost terminations, the transmit signal at the RXA pinminus the receive buffer gain should be 6 dB below thelevel at the line.Modem Works In Loopback but Falls to Connector Makes Errors in Bursts with Some OtherModemsIf anything appears "flaky" about the modernoperation it is a good idea to check the oscillatorfrequency with a counter capable of resolving to atleast ten parts per million. Using an oscilloscope is ofno use whatsoever. Many systems that use crystaloscillators are not very particular about the exactfrequency; this is not so of modems. Measure thefrequency at the eLK pin and verify that it is between11.0581 MHz and 11.0603 MHz. Do not measure at theXTLlorXTL2pinsastheprobecapacitancewillaiter thefrequency of oscillation. Some causes of out-ofspecificationreadings are: a) the wrong crystalfrequency entirely, b) a series-resonant crystal, or c) aparallel-resonant crystal unmatched to the circuitcapacitance.Problems Unique to FSK ModesThe SSI 73K224L does not permit answer tonedetection in FSK modes, so ensure that a mode otherthan FSK is selected before a ttempti ng to detect answertones.9-16

SSt 78P236/2361/2362/7200Demo BoardDESCRIPTIONFEATURESNovember 1993The 78P236 demo board is a PC board designed tofacilitate the evaluation of the SSI 78P236 series ofsingle chip transceiver ICs. The demo board can beused to test different transceiver ICs by changing variouscomponents. The demo board includes all of thenecessary discrete components for the interface to acoded AMI line. A DIP switch allows easy control of theoption pins on the IC. A loopback function is easilyimplemented using a slide switch. The same switchallows either an encoded signal (TPOS, TNEG, TCLK)or composite signal (TDATA, TCLK) be input to thetransmitter. Simple test patterns can be injected into thedata stream. Several jumpers allow the change of thetransmitter and receiver clock polarity.• Allows easy evaluation of AMI transceiver ICs• Includes all necessary external components• Includes a digital loopback mechanical switch• Generates ALL ONEs and repeated ONE/ZEROpatterns• Accepts composite Clock/Data and convertsthem to AMI pulses (No B3ZS encoding)• Allows the use of either the receive clock or anexternal clock as the transmitter clock• 20-pin edge connector accepts flat coax cablesand provides logical signalsIFIGURE 1: Demo Board Block Diagram1193- rev. 9-17

SSI78P236/2361/2362/7200Demo BoardPOWER SUPPLY CONNECTIONThe demo board is constructed as a four layer PC board.The outer two layers carry the signals. The internal twolayers are the segmented ground and power supplyplanes. Three segments separate the receive, transmitand logical ground and supply planes. The three groundplanes are connected together using PC board traces atJP2 and JP8 positions. These traces can be cut toisolate the three planes from each other. The powersupply planes are connected to a single +5V bananajack (J4) using LC fitters of 4.7 J.lH and 0.1 J.lF. When aseparate digital +5V supply is available, L 1 is removedand the DVCC supply can be connected to J2.RECEIVE SIGNAL PATHThe AMI signal is connected to the BNC connector J1 O.The maximum recommended distance of the demoboard to a DSX crosspoint is 450 feet. The IC can handleadded resistive attenuation as referenced by its minimuminput signal level specification. The IC recovers clock,positive and negative data from the AM I signal. Thefollowing table shows the available receiver logicalsignals on the test points and edge connector J5:J5 PINTEST POINT1 LOWSIGI U1-273 RDATA = RPOS .OR. RNEG5 RPOS U1-257 RNEG U1-249 RCLK U1-2311 RCLKIThe AMI input Signal should be properly coded toprevent a long run of zeros on the line. The proper codeshould limit the number of zeros to three. The followingtable shows the proper coding required:The demo board may be loaded with components whichform a discrete equalizer for very long cables (R11, R12,R13, C31, L 10). The AMI input signal to the IC can bemonitored using a high impedance FET probe(TEKTRONIX P4064 or HP 1141A) connected to theTP14, TP15 pair.The input signal is coupled through a 1:1 widebandtransformer. The following table shows some of thesuggested manufacturers of this part:MANUFACTURERPART NO.Pulse Engineering PE-65966CoilcraftWB1010-PCMini Circuit T1-1 .The AMI line is terminated at 75 ohms using R10.Table 1 shows the required external components fordifferent ICs used for receiving AMI Signals at differentspeeds. Resistor R2 sets the center frequency of theoscillator. Capacitor C6 is used to bypass any noise onR2. Resistors R3,R20 and capacitor C26 controls thejitter characteristic of the IC.SINGLE ENDED INPUTIt is possible to directly couple the IC to the AMI signalwithout a transformer using two capacitors (C29, C30)for isolation. In this case jumpers in locations R11, R12should be cut and the transformerT1 should be bypassedby connecting pins 1 to 6 and 3 to 4 at the back of thedemo board. The minimum input level should be higherthan the transformer coupled circuit. The positive effectof the transformer in rejecting common mode noise isnot achieved in this case.IC SPEED MAX CODEMbitls zeros NAME78P236 44.736 2 B3ZS78P7200 44.736 2 B3ZS78P2361 51.840 2 B3ZS78P2362 34.368 3 HDB39-18

SSI 78P236/2361 1236217200Demo BoardTRANSMIT SIGNAL PATHThe IC accepts CMOS level NRZ logical inputs(TCLK,TPOS,TNEG) and converts them to the properAMI signal. As shown in Table 2, the three positionswitchS3andjumpersJP1,5,6allowselectionofdifferentsources for these logical signals. In its simplest case,placing S3 in the bottom position allows a digitalloopback.The following table shows the test points and J5 edgeconnector pins used for the transmitter.J5 PINTEST POINT15 TCLK clock input17 TNEG negative data19 TPOS positive data19 TDATA composite dataThe outputs of the IC, LOUT + and LOUT -, are connectedto a 1:1:1 wide band transformer. The following tableshows some of the suggested transmitter transformers:MANUFACTURERPART NO.Pulse Engineering PE-65969Minicircuit T4-1The transformer center tap is connected to the +5Vsupply through a filter comprised of a 4. 7 ~ inductor anda 0.11lF capacitor. The capacitor C27, when added to thePC board trace and the transformer input capacitances,will effect the pulse shape. This capacitor should beselected for individual PC boards. The objective is tomeet a pulse template at any cable length up to amaximum of 450 feet. The generated AMI signal isavailable on the BNC connector, J11, and it can bemonitored on TP12, TP13 pair using a high impedanceprobe.OPTION PINS CONTROLSwitch S1 changes the logic level of the option pins onthe IC which controls the transmitter. Table 3 shows thefunction of this switch.PERFORMING TESTS WITH DEMO BOARDThe general test setup using the demo board is shownin Figure 2. When the switch S3 is placed in its bottompoSition (Ioopback), the receiver logical output signals(RCLK, RPOS, RNEG) from the IC are connected to thetransmitter logical input (TCLK, TPOS, TNEG). As aresult, the received AMI Signal is transmitted back to thetest equipment. Bit error rate testing will indicate theability of the IC to receive and transmit the AMI signalwith no errors.As shown in Figure 2, 450 feet of 75 ohm coaxial cable(type RG59B) and resistive attenuation is inserted in thereceive path to exercise the IC for its lowest input level.The following tests are performed on the receiver:BIT ERROR RATE TESTA pseudo-random pattern is generated by the testequipment. This pattern is created using a shift registerof N bits. Preventing an all zero pattern, a combinationof 2**N-1 patterns of N bits is created in a randommanner. This pattern is used to simulate the live trafficon the AMI line. The following table shows the mostlyused patterns to test the IC:IC RANDOM FIXEDPATTERN PATTERN78P236 2**15-1 100100 ...78P7200 2**15-1 100100 ...78P2361 2**15-1 100100 ...78P2362 2**23-1 10001000When running these patterns, no bit errors are expectedin the absence of any noise. The test is repeated forfixedpatterns to exercise the IC for any pattern sensitivity.JITTER TOLERANCETelecommunication equipments should be able to 9recover clock and correct data even if the AMI Signalincludes a reasonable amount of timing jitter. For thistest, the test equipment adds jitter to the random AMIsignal. For jitter at a set frequency, the amplitude of thejitter is slowly increased until bit errors are observed.This process is repeated at different frequencies and aplot of the maximum tolerated jitter vs the jitter frequencyis made as shown in Figure 3. The IC should toleratejitter in excess of specified requirements.9-19

SSI78P236/2361/2362/7200Demo BoardINTRINSIC JITTERThe jitter generated by the IC in the absence of any jitteron ns transmitter logical input (TCLK, TP08 TNEG).should be minimal.JITTER TRANSFER FUNCTIONThe IC should not cause any amplification of the systemjitter, i.e., no peaking should be observed in the jittertransfer function. This objective is achieved by selectingthe PLL filter components for an overdamped response.The test equipment adds jitter to the AMI signal receivedby the IC. Measuring the jittertransmitted by the I C in thedigitalloopback mode indicates the shape ofthe transferfunction. As shown in Figure 4, the IC adds no peakingand higher frequency jitter is attenuated.TRANSMITTER TESTSThe AMI pulse generated by the IC can be tested for itsshape, amplitude and frequency content over differentlengths of cable. The demo board is usually placed inthe loopback mode (83 in bottom position).PULSE FREQUENCY CONTENTSFor an AMI signal with an all ones pattern, the transmntedsignal should have a frequency spectrum with the maincomponent at half of the bit rate. The signal power at theharmonics including the component at the bit rate shouldbe at least 20 dB lower than the main component. Aspectrum analyzer is used for this purpose.PULSE AMPLITUDEThe pulse amplnude for a pattern of 1 001 00 ... is measuredat different cable lengths by connecting the end of thecable to the scope using a 75 ohm termination adaptor(POMONA 4119). Except for the 78P2362, whosetransmitted pulse amplitude is needed to be fairly exact(2 Vp-p ± 5%), other IC's transmit amplitude may fall ina wide range of amplitudes from 0.72 to 1.7 Vp-p.PULSE TEMPLATEThe shape of the signal is examined by comparing it tothe published templates. The test setup is shown inFigure 2. The program resident in the computer readsthe transmitter waveform from the scope, scales itvertically, and plots it togetherwith the published templatemasks. The pulse shape should meet the mask for allcable lengths from zero to 450 feet. The LBO pin ascontrolled by switch 81-1 should be properly set. Forcable length of less than 225 feet this switch is open andfor longer cables this switch should be closed. A typicalpulse shapes for the 78P236 at the end of 450 feet ofcable is shown in Figure 5.PULSE IMBALANCEThe AMI pulse generated by the Ie includes pulses ofboth negative and positive polarities. The pulse imbalanceis examined by inverting the negative pulse using thescope and overlaying tt on a typical positive pulse. Nosignificant imbalance is observed.TABLE 1: External Components List for Different ICsData sheet ref. -> RFO RLF1 RLF2 CLF1 RTR RTT CTTDemo board ref. -> R2 R3 R20 C26 R10 R6 C2Unit -> kQ kQ kQ J.lF Q Q pF78P236 44.736 5.23 20 100 0.22 75 None 1078P7200 44.736 5.23 6.04 100 0.22 75 301 10---78P2361 51.840 4.53 20 100 0.22 75 None 1078P2362 34.368 6.81 20 100 0.22 75 None 59-20

~-.---SSI78P236/2361/2362/7200Demo BoardTABLE 2: Sources of the Transmitter Logical SignalsSwitch Source of: Source of: Polarity of:TPOSITNEGTCLKTCLK53JP52-1JP52-3JP12-1JP12-3TopExternalRCLK EXT Buffered InvertedJP6 ConvertedRCLK EXT Buffered InvertedMiddle 2-1 fromTDATAJP6 InternallyRCLK EXT Buffered Inverted2-3 generatedBottomRP05/RNEG RCLK RCLK RCLKRCLKTABLE 3: Function of the DIP Switch S1PositionICPlnFunctionOpenClosed51-151-251-351-4LBOOPT1OPT2NoneTX cable lengthTX amplitudeTX disabletest patternJP6 2-3, 53 Mid.L < 225' ---_ ...NormalEnable-----_.. - --1010 ...L> 225'Boost 2.7 dBDisable111 ...IEEE CABLESCOPE'--__ --,75QIII PRINTER IIBM PC + SOFTWARE+IEE488FIGURE 2: General Test Setup9-21

551 78P236/2361/2362/7200Demo Board~10c:6.. ............. ..................2-. '"w0::JI--::i1.0'.0..:2«a:wI--I--=; 0.1~.... .......'. ~'... .....""'.'.0.0110 100 1K 10K 100K1MJITTER FREQUENCY (Hz)FIGURE 3: Jitter Tolerance for 78P236+20+1000 0~z\~C)a: -10wI--I--::;-20\-3010 100 1K 10K 100K1MJITTER FREQUENCY (Hz)FIGURE 4: 78P236 Jitter Transfer FunctionLoop Filter BW = 165 kHz9-22

SSI 78P236/2361 1236217200Demo Board1.0~c(0.90.8wa..0.70f-0.6f- w 0.5C/)+ 0.4f-::J0.30..J0.2TEMP = 25°Cen =5 pFTRANSFORMER: PE 65664LENGTH: 450 FT.0.10.0-.06 -.04 -0.2 0.00.2 0.4 0.6 0.8 1.0 1.2 1.4TIME SLOTS (UI)FIGURE 5: Transmitter Pulse Shape for 78P236I9-23

053_'NtJrSHORT FORSINGLE ENDED INPUTREV B2 ONL~Y L 6~6~L1 DVCCn~~~ 0UlLlN+NCR2RFORGNDRVCCTP30 TP31 TP32 TP32TP TP TP TP~~ IYTP34TP35~~oen(Den3-0 .....Q)m'"tJ01\)mW... ena.-- I\)Wen .....I\)--W-- .....I\)enI\)o

551 78P236/2361 1236217200Demo BoardN. 1- > NOT INSTALLEDCUT FOR SINGLE ENDED1R11-12'~~----~--------~~OUT2CUT FOR SINGLE ENDEDFIGURE 7: Pad / Equalizer1T .01 T .01 J.vee.01 T .01C20 1 C21 1 C22 1 C23veeJP6U3B12 0 PR11>ClKCl0Q9874F74}-.:..:----ClKveea 674 474F02ITXNEGrnlJC)----o... JP574F08TClKBFIGURE 8: Encoder9-25

SSI78P236/2361/2362/7200Demo BoardORDER~G~FORMATIONAMI SPEEDMbit/sDEMO BOARD PART NUMBERSSt 78P236/2361/2362/7200 Demo Board44.736 OS-344.736 OS-351.840 STS-134.368 E-378P236-0B78P7200-0B78P2361-0B78P2362-0B---.-.--.. -.-----.--~------. ---.--------.--No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rightsof third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systemsreserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the datasheet is current before placing orders.Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-69141193 - rev. 9-26

SSI78Q8373TechnicalReferenceGuideIDISCLAIMERTHIS MANUAL IS INTENDED TO BE USED AS A GUIDE ONLY. Silicon Systems does not warrant any of the schematics shown or code segmentsprovided to be qualified for production. No responsibility is assumed by Silicon Systems for use or installation of the products described herein, nor anyinfringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems reserves the right to make changes in specifications at any time without notice.Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914©1994 Silicon Systems, Inc. 9-27 0894

9-28

OVERVIEWINTRODUCTIONThe SSI 78Q8373 is a device for Ethernet LAN applications that consists of an Ethernet protocol controller, Manchester Encoder/Decoder, lOBaseT transceiver, AUI port, and PCMCIA Bus Interface logic on one chip. It can operate using a 5-volt or 3.3-voltsupply. This document contains detailed descriptions of key parts of the protocol controller block, namely, the Buffer Manager blockand the Data Link Controller block, along with bit descriptions of all of the control and status registers. In addition, there isinformation on the power management capabilities of the SSI 78Q8373, how to configure the part for host and medium connections,information about how a host processor would handle packet transmission and reception on a network, and descriptions of the mediainterfaces (lOBaseT and AU!) and PCMCIA Bus Interface. For detailed pin descriptions, electrical and timing parameters, pleaserefer to the SSI 78Q8373 Data Sheet.2 GENERAL DESCRIPTIONThe SSI 78Q8373 combines the Ethernet network interface together with packet data management and consists of six major blocks:• Buffer Manager (and SRAM Interface)• Data Link Controller• Host/PCMCIA Interface• Manchester data Encoder/Decoder (EN DEC)• Twisted-pair Transceiver• Power Management78Q8373SRAMInterface'-- - -10BaseTTransceiver::::x::::::::::Twisted Pair Medium::::x::::::::::Host!PCMCIAInterfaceBufferManagerData LinkControllerManchesterENDECPowerManagementAUIPort? ":.PCMCIABus.2.1 Buffer ManagerFigure 1-1: Block Diagram (7808373)The Buffer Manager manages all accesses to the buffer memory through the SRAM interface. The buffer memory is connecteddirectly to the Data Link Controller (DLC), thus eliminating the need for a local microprocessor. The Buffer Manager also keepstrack of all buffer memory pointers automatically; simplifying the software driver task. Together with intelligent arbitration, theSSI 78Q8373 is a high performance LAN controller.The buffer memory is divided into a transmit memory section and a receive memory section. The transmit memory section can bepartitioned into 2K, 4K, 8K or 16Kbyte buffer sizes. If the transmit buffer size is greater than 2KB, then the transmit buffer isI9-29

1.2.1 Buffer Manager (continued)configured into two banks of equal size. There is only one transmit bank if a 2KB buffer size is selected. With the two banconfiguration, one transmit bank may be tied up during transmission but the host can still continue to load data packets into the secoOitransmit bank to be tranmitted later. The receive buffer has a ring architecture which can be configured from 4K to 62KB dependin;on the buffer memory configuration, which can range in size from 8K to 64KB.A central arbitrator inside the Buffer Manager prioritizes and services requests for access to the buffer memory from four source5the Transmitter, the Receiver, Host Read and Host Write. If necessary, the SSI 78Q8373 will assert a 'not ready' handshake to thhost while servicing the Transmitter and/or Receiver. The SSI 78Q8373 arbitration mechanism provides packet management b:interleaving packet data accesses to the buffer memory such that the operation appears to be simultaneous.For instance, in the situation where 2 transmit banks are configured, the host can load the first transmit bank and initiate ,transmission. While the first transmit bank is being transmitted, the host can continue to load packets in the second transmit ban~At this stage, the SSI 78Q8373 can potentially be receiving data from the medium and loading it into the receive buffer (if the SS78Q8373 is in a loopback mode or if self-reception occurs).1.2.2 Data Link ControllerThe Data Link Controller (DLC) implements the ISO/ANSI/IEEE 8802-3 CSMAlCD protocol. It consists of a Transmitter and:Receiver, each with its own independent CRC logic. Automatic generation and stripping of the 64-bit preamble and the 32-bit CR(code are provided on-chip.1.2.3 Host/PCMCIA InterfaceThe Host Interface provides connection to the host system. It consists of the various registers, DMA circuits and ready logic. Bot!word and byte interfaces are supported as well as big endian and little endian data ordering. Host access to the buffer memory ithrough BMR8 (and BMR9). Reading from BMR8 will read a byte or word from the receive buffer and writing to BMR8 will writea byte or word to the transmit buffer. The ready logic is capable of delaying host access to the buffer memory with a time-oumechanism. Both single and burst DMA transfer modes are supported.The PCMCIA interface circuitry builds on top of the SSI 78Q8373 generic host interface and is only active if the MODE pin is letunconnected (internally pulled-up). The SSI 78Q8373 can thus connect directly to a PCMCIA release 2.1 compliant bus. It als(supports decoding fortheextemal CIS memory (both ROM and Flash types). The SSI 78Q8373 pinout has been defined to minimiz

1.2.7 Pin AssignmentsFollowing are the pin assignments for both the QFP and TQFP versions of the S SI 78Q83 73.TABLE 1: Pin Assignment Table - PCMCIA Bus Mode -100-Lead TQFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE1 D1 104 26 OE I 51 RA4 04 76 DON AO2 D8 104U 27 WE I 52 RA5 04 77 DOP AO3 DO 104 28 INPACK 04 53 RA6 04 78 AGND P4 AO I 29 REG I 54 GND P 79 REXT R--5 A1 I 30 ROMG 04 55 VDD P 80 AVDD P- ---6 A2 I 31 FCE 04 56 RA7 04 81 TPIN AI7 A3 I 32 XPD 04 57 RA12 04.--~-82 TPIP AI8 RESET SI 33 XRST 04 58 RA14 04 83 MODE TI9 VDD P 34 GND P 59 RWE 04 84 DIN AI10 GND P 35 ROO 104U 60 RA13 04 85 DIP AI11 10WR I 36 RD1 104U 61 RA8 04 86 CIN AI12 lORD I 37 RD2 104U 62 RA~ 04 87 CIP AI13 CE2 I 38 RD3 104U 63 RA11 04 88 GND P--14 015 104U 39 RD4 104U 64 ROE 04 89--_...SPKRIN SI15 CE1 I 40 RD5 104U 65 RA15 04 90 SPKR 08--16 014 104U 41 RD6 104U 66 OSCI CI 91 CCRA I-_.-- -17 07 104 42 RD7 104U 67 OS CO 0 92 RRST 0418 GND P 43 GND P 68 VDD P 93 LEDLT OD16-------19 013 104U 44 RCSO 04 69 GND P 94 CB 0420 06 104 45 RCS1 04 70 GND P 95 10lS16 0421 D12 104U 46 RA10 04 71 TPDN AO 96 IREO 08-----~-.. -22 05 104 47 RAO 04 72 TPDP AO 97 WAIT 0423 D11 104U 48 RA1 04 73 TPON AO 98 010 104U24 04 104 49 RA2 04 74 TPOP AO 99 02 10425 03 104 50 RA3 04 75 VDD P 100 D9 104ULegend:I: Input (TTL level)04, 08: Output with 10L = 4 or 8 rnA0016: Output Open Drain with 10L = 16 rnA104, 104U: Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level input ISI: Schmitt trigger input •TI: Three-state input. May be connected to low, high, or left open.AI: Analog inputAO: Analog outputP: PowerR: Resistor to ground0: Output9-31

TABLE 2: Pin Assignment Table - PCMCIA Bus Mode -100-Lead QFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE1 D10 104U 26 D11 104U 51 RA1 04 76 TPON AO2 D2 104 27 D4 104 52 RA2 04 77 TPOP AO3 D9 104U 28 D3 104 53 RA3 04 78 VDD P---4 D1 104 29 OE I 54 RA4 04 79 DON AO5 D8 104U 30 WE I 55 RA5 04 80 DOP AO----------6 DO 104 31 INPACK 04 56 RA6 04 81 AGND P7 AO I 32 REG I 57 GND P 82 REXT R----8 A1 I 33 ROMG 04 58 VDD P 83 AVDD P9 A2 I 34 FCE 04 59 RA7 04 84 TPIN AI- _.-10 A3 I 35 XPD 04 60 RA12 04 85 TPIP AI---11 RESET SI 36 XRST 04 61 RA14 04 86 MODE TI-------12 VDD P 37 GND P 62 RWE 04 87 DIN AI13 GND P 38 RDO 104U 63 RA13 04 88 DIP-~14 IOWR I 39 RD1 104U 64 RA8 04 89 CIN AI15 lORD I 40 RD2 104U 65 RA9 04 90 CIP AI------16 CE2 I 41 RD3 104U 66 RA11 04 91 GND P17 D15 104U 42 RD4 104U 67 ROE 04 92 SPKRIN SI18 CE1 I 43 RD5 104U 68 RA15 04 93 SPKR 0819 014 104U 44 RD6 104U 69 OSCI CI 94 CCRA I-~20 D7 104 45 RD7 104U 70 OSCO 0 95 RRST----21 GND P 46 GND P 71 VDD P 96 LEDLT OD16--_.-------22 D13 104U 47 RCSO 04 72 GND P 97 CB 0423 D6 104 48 RCS1 04 73 GNO P----~98 10lS16 0424 012 I04U 49 RA10 04 74 TPON AO---~-99 IREO 0825 05 104 50 RAO 04 75 TPOP AO 100 WAIT 04Legend:I: Input (TTL level)04,08: Output with 10L = 4 or 8 rnA0016: Output Open Drain with 10L = 16 rnA104,I04U: Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level inputSI: Schmitt trigger inputTI: Three-state input. May be connected to low, high, or left open.AI: Analog inputAO: Analog outputP: PowerR: Resistor to ground0: Output9-32

TABLE 3: Pin Assignment Table - Generic Bus Mode -100-Lead TQFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE1 HD1 104 26 RD8 104U 51 RA4 04 76 DON AO2 HD8 104U 27 RD9 104U 52 RA5 04 77 DOP AO3 HDO 104 28 RD10 104U 53 RA6 04 78 AGND P4 HAO I 29 RD11 104U 54 GND P 79 REXT R5 HA1 I 30 RD12 104U 55 VDD P 80 AVDD P6 HA2 I 31 RD13 104U 56 RA7 04~ ~------.--81 TPIN AI-_.-7 HA3 I 32 RD14 104U 57 RA12 04 82 TPIP AI--------8 RESET SI 33 RD15 104U 58 RA14 04 83 MODE TI---------9 VDD P 34 GND P 59 RWE 04 84 DIN AI10 GND P 35 RDO 104U 60 RA13 04 85_.. _-DIP AI11 WR I 36 RD1 104U 61 RA8 04 86 CIN AI-----12 RD I 37 RD2 104U 62 RA9 04 ~.----- 87-------~-CIP AI--~-~13 BHE I 38 RD3 104U 63 RA11 04 88 GND P-----14 HD15 104U 39 RD4 104U 64 ROE 04 89 DMACK SI15 CS I 40 RD5 104U 65 RA15 04~-------90-_..-DMREQ 0816 HD14 104U 41 RD6 104U 66 OSCI CI 91 EOP I17 HD7 104 42 RD7 104U 67 OSCO 0-- - ---92 RRST 04------_..-18 GND P 43 GND 104U 68 VDD P 93 LEDLT OD16----19 HD13 104U 44 RCSO P 69 GND P 94 CB 04- -------20 HD6 104 45 RCS1 04 70 GND P 95 HWORD 04- -----------21 HD12 104U 46 RA10 04 71 TPDN AO 96_.._--INT 0822 HD5 104 47 RAO 04 72 TPDP AO 97 READY 0423 HD11 104U 48 RA1 04 73 TPON AO 98 HD10 104U24 HD4 104 49 RA2 04 74 TPOP AO 99 HD2 10425 HD3 104 50 RA3 04 75 VDD P 100 HD9 104ULegend:I: Input (TTL level)04,08: Output with 10L = 4 or 8 rnAOD16: Output Open Drain with 10L = 16 rnA104,104U: Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level inputSI: Schmitt trigger inputTI: Three-state input. May be connected to low, high, or left open.AI: Analog input 9AO: Analog outputP: PowerR: Resistor to ground0: Output9-33

~--- -_._---~-------TABLE 4: Pin Assignment Table - Generic Bus Mode -100-Lead QFPPIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE PIN# PIN NAME TYPE1 HD10 104U 26 HD11 104U 51 RA1 04 76 TPON AO.------2 HD2 104 27 HD4 104 52 RA2 04 77 TPOP AO3 HD9 104U 28 HD3 104 53 RA3 04 78 VDD p--4 HD1 104 29 RD8 104U 54 RA4 04---~79 DON AO-----5 HD8 104U 30 RD9 104U 55 RA5 04 80 DOP AO6 HDO 104 31 RD10 104U 56 RA6 04 81 AGND P7 HAO I 32 RD11 104U 57 GND-----RP 82 REXT---- ~----~-p--8 HA1 I 33 RD12 104U 58 VDD P 83 AVDD--------------9 HA2 I 34 RD13 104U 59 RA7 04 84 TPIN AI10 HA3 I 35 RD14 104U 60 RA12 04 85 TPIP AI---11 RESET SI 36 RD15 104U 61 RA14 04 86 MODE TIr-----------12 VDD P 37 GND P 62 RWE 04 87 DIN AI--13 GND P 38 RDO 104U 63 RA13 04 88 DIP AI14 WR I 39 RD1 104U 64 RA8 04 89 CIN AI---_.-.. -~---15 RD I 40 RD2 104U 65 RA9 04 90 CIP AI----------- --~--r---16 BHE I 41 RD3 104U 66 RA11 04 91 GND P- ----_.".-. -- --_._----17 HD15 104U 42 RD4 104U 67 ROE 04 92 DMACK SI--_._---- --18 CS I 43 RD5 104U 68 RA15 04 93 DMREQ 08---------_ .. ----~-----19 HD14 104U 44 RD6 104U 69 OSCI CI 94 EOP I--------,----20 HD7 104 45 RD7 104U 70 OSCO 0 95 RRST 0421 GND P 46 GND P 71 VDD P 96 LEOLT 00161-------- --------- -22 HD13 104U 47 RC80 04 72 GND P 97 CB 04----_... _--- -~--1-23 HD6 104 48 RC81 04 73 GND P 98 HWORD 04f--------- -----24 HD12 104U 49 RA10 04 74 TPDN AO 99 INT 08-----25 HD5 104 50 RAO 04 75 TPDP AO 100 READYLegend:-- _.•-'"C54I: Input (TTL level)04, 08: Output with 10L = 4 or 8 rnAOD16: Output Open Drain with 10L = 16 rnA104, 104U: Input (TTL level) and Output with 10L = 4 rnA; 104U refers to 104 with an internal pull-up resistorCI: CMOS level input81: Schmitt trigger inputTI: Three-state input. May be connected to low, high, or left open.AI: Analog inputAO: Analog outputP: PowerR: Resistor to ground0: Output9-34

~ BUFFER MANAGERThe Buffer Manager manages accesses to the buffer memory through the SRAM interface. The buffer memory is connected directlyto the Data Link Controller (DLC) , thus eliminating the need for a local microprocessor. The Buffer Manager keeps track of all buffermemory pointers automatically, simplifying the software driver task. Together with intelligent arbitration for accesses to the buffermemory, this makes the SS! 78Q8373 a high performance LAN controller.!.1 BUFFER MEMORY CONFIGURATIONThere are 13 different ways in which to configure the transmit and receiver buffer SRAM for the SSI 78Q8373. This is done using4 register bits, DLCR6. DLCR6 sets the total buffer memory size and DLCR6 sets the transmit buffer size. Ifthe transmit buffer is greater than 2KBytes, it is divided into two transmit banks as shown in the table below.BS1 BSO TS1 TSO TOTAL TRANSMIT BUFFER MEMORY RECEIVEDLCRS(1) DLCRS(O} DLCRS(3) DLCRS(2) BUFFER BUFFERMEMORY TX BANK #1 TX BANK #2 MEMORY0 0 0 0 8KBYTES 2KBYTES -- 6KBYTES1) 0 0 1 8KBYTES 2KBYTES 2KBYTES 4KBYTES0 0 1 0 IlIeaal set-uD0 0 1 1 IlIeaal set-uD0 1 0 0 16KBYTES 2KBYTES -- 14KBYTES0 1 0 1 16KBYTES 2KBYTES 2KBYTES 12KBYTES0 1 1 0 16KBYTES 4KBYTES 4KBYTES 8KBYTES0 1 1 1 IIleaal set-uD1 0 0 0 32KBYTES 2KBYTES -- 30KBYTES1 0 0 1 32KBYTES 2KBYTES 2KBYTES 28KBYTES1 0 1 0 32KBYTES 4KBYTES 4KBYTES 24KBYTES1 0 1 1 32KBYTES 8KBYTES 8KBYTES 16KBYTES1 1 0 0 64KBYTES 2KBYTES -- 62KBYTES1 1 0 1 64KBYTES 2KBYTES 2KBYTES 60KBYTES1 1 1 0 64KBYTES 4KBYTES 4KBYTES 56KBYTES1 1 1 1 64KBYTES 8KBYTES 8KBYTES 48KBYTESThe remaining buffer memory that is not used by the transmit memory will be used as the receive memory. Figure 2-1 shows anexample of a buffer memory configuration of 64 KBytes.TXBUFFER2 KBYTES2 KBYTES2 KBYTES4 KBYTES8 KBYTES4 KBYTES8 KBYTESRXBUFFER62 KBYTES60 KBYTES56 KBYTES 48 KBYTESIFigure 2·1: Maximum Buffer Size (64 KBytes) for Transmit and Receive Buffers9-35

2.1 BUFFER MEMORY CONFIGURATION (continued)The buffer memory path of the SSI 78Q8373 is 8 bits wide in PCMCIA Bus mode and can be either 8 or 16 bits wide in GenericBus mode (The 8-bit path in PCMCIA mode is imposed due to the lack of enough pins). In the Generic Bus mode, the buffer memorydata path width is selected through DLCR6. IfDLCR6 is set toa 1, then the SSI 78Q8373 data path will be byte-wide. Thereare eight different SRAM configurations depending on whether the data path is 8- or 16-bit (refer to Figure 2-2). The RCSO andRCS1 are the SRAM chip select pins. In the 8 bit-data bus for 8KByte and 32KByte configurations, only RCSO is used and theaddress least significant bit starts from AO. Figure 2-2 shows the configurations possible for the SRAM.DLCR6 (1:0)8 Bit RAM Data Bus:DLCR6 (4) RBYTE = 1DLCR6 (5) HBYTE = ° OR 116 Bit RAM Data Bus:available in Generic Bus mode onlyDLCR6 (4) RBYTE = °DLCR6 (5) HBYTE = °RA12·RAORA12·RA18$1,0 = 0,0RO(7:0)RA13·RA1RA13·RA18$1,0 = 0,1RA14·RAORA14·RA18$1,0 = 1,0RO(7:0)8$1,0 = 1,1RA15·RA1RA15·RA1Figure 2·2: SRAM Configurations9-36

TRANSMIT OPERATIONThe SSI 78Q8373 complies with the IEEE 802.3 CSMNCO specifications with a transfer rate of 1 OMbit/s through the transmissionmedium. It will assemble all packets from the host and append a 64-bit preamble and a 32-bit CRC to the head and tail of each packetrespectively before transmitting to the medium. As mentioned in the Buffer Memory Configuration section, one or more packetscan be written by the system within a transmit memory bank until the remaining space is insufficient for another packet. The hostcan then issue a signal, called "Transmit start" which is stored in BMR 10 to initiate a transmission to the medium. All packetswithin the same bank will thus be transmitted and followed by the status update or an interrupt if it is enabled. With the two transmitbanks configuration, one bank can be transmitting and the second bank can be loading data from the system. This concurrentoperation of transmitting and host writing will improve transmission throughput.If the transmit packet encounter a collision in the medium, the SSI 78Q8373 will perform a truncated binary exponential backoffroutine up to 16 attempts. After the 16th attempt, the SSI 78Q8373 will either skip the current packet or re-transmit the packet again'depending on the status of BMR 11 .TRANSMIT PACKET DATA FORMATThe packet to be transmitted is first loaded into the transmit buffer together with a 2-byte header of data length in bytes. Figure2-3 shows an example of how 3 packets are stored within a single transmit buffer:Packet Length (LSB)Packet Length (MSB)Data1Packet #1Packet Length (LSB)Packet Length (MSB) Packet #2Data2Packet Length (LSB)Packet Length (MSB)Data3Figure 2-3: Packet Format in Transmit BufferAfter the packets are loaded, the host will write the number of packets to be transmitted into B MR 10 and initiate transmission. Atthis stage, if a two transmit banks configuration is chosen, any new packets can now be loaded into the second bank..4 RECEIVE OPERATIONThe receive memory is configured as a ring structure which means the bottom of the memory is wrapped around to the top of thereceive memory. There are two pointers to handle incoming packet management and they are the receive pointer and the host readpointer. The receive pointer will always point to the next empty location in the receive memory. The host read pointer is used bythe host to retrieve accepted packets from the receive memory. 9Initially, the values of the two pointers are equal which implies that the receive buffer is empty. As soon as data is loaded into thereceive bank from the medium, the receive pointer will move away from the host read pointer. The preamble and the CRC bits areautomatically removed by the data link controller (OLC) before storing the data to the receive buffer. While accepting the data, thesize of the packet is checked. Under the IEEE specifications, the valid packet size is between 60 bytes to 1500 bytes (minus thepreamble and CRC portions). However, if set to I, the SSI 78Q8373 can accept packet sizes ranging from 6 bytes (by setting "acceptshort packet" in OLCR5 [ENA_SRTPKT] to a 1) to 2047 bytes. When a packet is successfully stored in the receive memory,the host can begin to read this packet. However, if there is more than one incoming packet or the packet size is too large, the receivepointer may override the host read pointer after wrapping around the ring structure. This situation is avoided with a buffer overflowflag,OVRFLO. When this flag is high, the receive pointer will not store any more data until the host read has cleared the memory.9-37

2.4 RECEIVE OPERATION (continued)Figure 2-4 shows the configuration of the transmit and receive buffer memory in the situation where the 2 transmit banks are selectedand explains the concept of a ring architecture of the receive buffer. The received packets are stored as they are accepted by the SSI78Q8373. The unused buffer space in the diagram shows that the host have read packets before 'Packet P-I' hence relieving thatbuffer space. Therefore the received packet' Packet P+2' can be wrapped around the end of the recei ve bufferto the start once again.The SSI 78Q8373 also checks the incoming packet for short packet errors, alignment errors and/or CRC errors. After one successfulpacket reception, the SSI 78Q8373 will perform an 8-byte re-alignment for the next packet in the receive buffer.2.4.1 RECEIVER BUFFER DATA FORMATTransmit Bank #1f- - - - - - - -Transmit Bank #2f- - - - - - - - -- --~Received Packet, P + 2 t +I- - - - - - - -Unused Buffer Space IIf- - - - - - - -IReceived Packet, P - 1 ReceiveI- - - - - - - - Ring IReceived Packet, PStructureI- - - - - - - -IReceived Packet, P + 1IIf- - - - - - - -Received Packet, P + 2t(Continued at the top) +\ I-- -- -Figure 2-4: Transmit and Receive Buffer OrganizationThe receive packet has a 4-byte header which consists of the status of the receive packet, a reserved byte, and the 2 bytes of datalength. Regardless of the SRAM word or byte configuration, the data length is always in terms of bytes. The data packets are linkedby the internal pointers which use the data length value in the header to calculate the length of the data packet. Then the receiverwill perform an 8-byte boundary alignment and the new address is generated. Under normal operation, any packets that have errorswill be discarded. Figure 2-5 shows how accepted packets are stored in the receive buffer.TheSSI 78Q8373 provides a means to accept erroneous packets, mainly for testing purposes. If the DLCR5 bit (ACPT _BADPKT)is set to aI, short packets or packets with alignment or CRC errors will be accepted. In these circumstances, the respective bits ofthe receive status registers will not be set. But the status byte to the host will still indicate that the packet has error(s).The format of the status byte is as shown below. Note that the bit names are similar to that of the DLC register bits. However, someof these bits are not a mirror image of the corresponding register bits and this is elaborat~d on in the Status Byte Format section.Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 00 0 PACKETOKREMOTERESETSHORTERRORALIGNERRORCRCERROROVERFLOW2.5 DMA OPERATIONData transfer via Direct Memory Access is available only in the Generic Bus mode. The DMA write or DMA read operation is similarto the I/O write or I/O read except that the handshake is done using DMREQ, DMACK and EOP signals. The DMREQ signal isused to request for DMA transfers and the DMACK signal acts like the CS to access the BMR8 and BMR9 register pair. The WRor RD signals accompany the DMACK to perform host write or host read operations respectively.An EOP signal is asserted during the last data word or byte transfer to terminate the process (the D M A_EOPregister bit [DLCR 1 ]will be set when EOP is asserted). The SSI 78Q83T3 will not assert further DMREQs when EOP has been asserted by the host DMA.If the DMA interrupts are enabled, the assertion of the EOP will also cause the SSI 78Q8373 to generate an interrupt to the host.9-38

DMA OPERATION (continued)Single or burst DMA operations are supported for data transfer between the host and the SSI 78Q8373. In single byte or wordaccesses, the SSI 78Q8373 asserts the DMREQ signal and waits for the host to respond with a DMACK acknowledge and a WRor RD signal. Upon acknowledgment, the SSI 78Q8373 negates the DMREQ until the host completes the data transfer. The DMACKsignal is set high when the transfer is complete. To start another DMA cycle, the SS I 78Q8373 will assert the DMREQ signal again.This continues until the host asserts the EOP signal during the last access cycle after which the SSI 78Q8373 will not make furtherDMREQ requests.In burst modes, the DMA operation can be programmed for 4,8 or 12 data transfers per DMREQ request. In these cases, the SSI78Q8373 will negate DMREQ two cycles before the end of each burst. An EOP assertion will terminate a DMA operation anytimeduring the burst data transfer.8 Byte AlignmentStatus ByteReservedLength (LSB)Length (MSB)Packet (N-1)DATA (N - 1)8 Byte AlignmentStatus ByteReservedLength (LSB)Length (MSB)Packet (N)DATA (N)8 Byte AlignmentStatus ByteReservedLength (LSB)Length (MSB)DATA (N+1)Packet (N+ 1)IFigure 2-5: Packet Format in Receive Buffer9-39

2.5.1 DMA WRITE (TRANSMIT)In a DMA write mode, the host performs the same function as an I/O write to load the transmit bank with one or multiple packetsof data. Typically the host has its own DMA controller which it programs to handshake with the DMA operation in the SSI 78Q8373.The host can use a combination of I/O and DMA to write a packet into the transmit buffer.The following depicts an example of how to perform a DMA write mode using a combination of I/O and DMA operation. First,the host determines the size of the packet and writes the byte length into the SSI 78Q8373's transmit buffer using I/O access.Subsequently, the host DMA is programmed with this length information. To start a DMA transfer, the host writes a 1 to theDMA_lENA bit (BMR12

DATA LINK CONTROLLERThe Data Link Controller (DLC) implements the ISO/ANSI/lEEE 8802-3 CSMA/CD protocol. It consists of a Transmitter and aReceiver, each with its own independent CRC logic. Automatic generation and stripping of the 64-bit preamble and the 32-bit CRCcode are provided on-chip.IEEE PACKET FORMATThe DLC of the SSI 78Q8373 complies with the international standards for Ethernet, ISO/ANSI/IEEE 8802-3. The IEEE 802.3Media Access Control (MAC) frame format is shown in Figure 3-1.Preamble101010 ......... 10- - - - -SFD10101011DestinationAddressSourceAddressLengthI- - - - -DataI- - - - -PaddingFCS7 Bytes1 Bytes6 Bytes6 Bytes2 BytesMin 46 bytes. max1500 bytesAs required to meet minimumpacket size4 BytesFigure 3-1: IEEE 802.3 Media Access Control (MAC) Frame Format,1.1 ELEMENTS OF THE MAC FRAMEThe MAC frame size is defined to cover the Destination and Source Address fields, Length Field, Data Field, Padding (if necessary)and Frame Check Sequence Field (CRC Code). The minimum frame size defined in the IEEE Media Access Control Protocol is64 bytes and the maximum frame size is 1518 bytes.Preamble Field:This is a 7-byte field consisting of alternating l's and O's to allow synchronization of phase lock loop (PLL) circuitry in thereceiver.Start Frame Delimiter (SFD) Field:The SFD sequence is 10101011. This immediately follows the preamble and the double 1 's signify the start of the frame.Address Fields:Each MAC frame consists of two address fields. The Destination Address Field specifies the destination address( es) for whichthe frame is intended and the Source Address Field specify the node that is transmitting the packet. The first bit (LSB) of theDestination Address is used to identify individual or group addressing. LSB = 0 indicates an individual address and LSB = 1indicates a group address. The SSI 78Q8373 offers 3 types of group addressing called multicast group, multicast hash andbroadcast addressing. A broadcast address consists of alII's in the Destination Address field and is used to broadcast to all activestations on the network. Please refer to Node ID and Hash Table Configuration Registers for detailed information on the othertwo multicast addresses.Length Field:This is a 2-byte field whose value indicates the number of data bytes in the Data Field. The Length Field is transmitted withthe high order byte first. However, some protocols use this field for other purposes (Ethernet calls this a Type Field instead).This is achieved by using values greater than the allocated values for a valid Length Field (value < 1500) to distinguish theprotocol used. The SSI 78Q8373 does not perform a consistency check on the length of the data field that follows this field.I•9-41

Data and PAD Fields:The data field may contain any data from a minimum of 46 bytes to a maximum of 1500 bytes. If necessary, the data fieldis extended to meet the minimum frame size requirement. These extra bits are caUedPadding. The SSI 78Q8373 does notperform automatic padding. Upper layer software is responsible for this task.Frame Check Sequence Field:A cyclic redundancy check (CRC) is used by the transmit and receive algorithms to generate a CRC value for the FCS field.This is a 32-bit sequence that is computed as a function of the addresses, length, data (and pad) fields. The SSI 78Q8373 hasa CRC circuitry that generates the CRC for the packet to be transmitted and checks the CRC of the received packets fortransmission errors.3.2 TRANSMITTER CIRCUITSCircuits within the transmitter include a transmit state machine, pseudo-random number generator, preamble generator, interframegap timer, exponential backoff generator and a time domain reflectometry counter. The CRC logic is shared by thetransmitter and the receiver. Any transmit errors will be reported via the DLCR status registers.The CRC logic calculates the IEEE 32-bitFrame Check Sequence (FCS) for the entire data packet (from the destination addressto the end of the data field) and appends theFCS to the end of the packet. In the event of self-reception in 'accept all packets' modes6r loop back, the CRC logic is used by the transmitter only.3.2.1 transmit Media Access ManagementThe SSI 78Q8373's DLC block implements the ISO/ANSI/lEEE 8802-3 Media Access Protocol called the CSMNCD. This isthe acronym for Carrier Sense Multiple Access with Collision Detect. Abiding by this protocol requires the controller to monitorthe presence of a carrier from other nodes on the network and deferring any transmission if a carrier is 'sensed' on the network.A collision is defined py the situation whereby two nodes transmit at nearly the same time and try to drive the network togetherwhich results in garbled data. In the event that a collision occurs, this is detected via the collision detection mechanism. A nodethat is involved in a collision will transmit a 32-bitJam Pattern to reinforce the collision such that every node on the network detectsit. It will then cease its transmission and wait a pseudo-random backoff interval before attempting to transmit the packet again.According to the ISO/ANSI/lEEE 8802-3, there must be a 9.6 msec interval between the transmission of packets for the networkto recover. This is called the Inter-Frame Gap (lFG) and the SSI 78Q8373' s DLC utilizes the IFG timer in the transmitter to recordthe interval starting from the end of the last packet on the network. The DLC will not transmit before this interval expires. If anothernode happens to transmit during the first 2/3 of the IFG interval, the SSI 78Q8373 will reset its IFG counter and start again at theend of this new transmission. However during the last 1/3 of the IFG interval, the SSI 78Q8373 will ignore any transmission onthe network that occurs during that time in accordance with the IEEE standard. This is to assure fairness and equality in accessingthe network. With two nodes transmitting at nearly the same time, a collision would occur resulting in pseudo-random backoffintervals for each node to resolve the contention.The SSI 78Q8373's TDR counter keeps track of the number of bits that has been transmitted. The counter maintains the countof the actual number of bits transmitted just before a collision or loss of carrier occurs. The count can then be used to diagnosethe medium as shown.Estimating the distance, D (m) from the transmitting node to a fault:N = number of bits transmitted (TDR Count)R = transfer rate, 10 Mbit/sS = signal propagation for coaxial cable (in the region of 2 x 10 8 m/secD = (N x S)/(2 x R) metersA pseudo-random number generator is used for collision backoffs. The range of the random num ber interval increases with eachcollision with the maximum range occurring for the 10th collision through the 16th collision. Hence it is called the truncated binaryexponential backoff. The value obtained from the pseudo-random number generator is counted down every slot-time (512 bits).When the interval expires, the SSI 78Q8373 will check the IFG timer and attempt to re-transmit.9-42

.2 Transmit ErrorsThere are 4 transmit error status bits in DLCRO. These cover the loss of carrier during collision, collision on the network, 16consecutive collisions and host write error. The loss of carrier usually indicates a fault on the network (open or shorted medium).The 16 collisions error indic·ates that host intervention may be necessary pertaining to the next step that the SSI 78Q8373 shouldtake. Please refer to Buffer Memory Registers Section (BMR 11

has been activated. Packets with alignment or CRC or short packet errors are accepted only if the ACPT _BADPKT bit (DCLR5

8MOLCENOECI TRANSMITMANAGERI RECEIVERIt----ITRANSMITTER IIMANAGER f--4- I RECEIVER I------- I IDECODERSSI78Q8370CD ENOEC Loopback(§ Media (TP connection) Loopback@ Media (AUI connection) Loopback~IENCODER I .. TWISTEDCDPAIRTRANSCEIVER~ "-'-1(§i--" r4-COAXTRANSCEIVERr----1i--"COAXCABLEFigure 3-2: 78Q8373 Loop Back ModesI9-45

4 POWER MANAGEMENTSSI 78Q8373 provides 3 modes of intelligent power management:1) Auto power down mode through BMR11.This mode is the default at reset/power up. The clocks are active only when they are needed. This auto power down mode Clbe disabled by programming a 1 which can be useful for chip debugging and maximum power consumption estimation.2) Standby mode through DLCR7 or through CCR1.SetDLCR7 = 0 to enter this mode, or, if the SSI 78Q8373 is in PCMCIA mode, set CCR 1 = I. This de-gates the oscillat~clock without shutting it off. All the internal clocks are not active with the oscillator still running. Using full static design, tlSSI 78Q8373 remembers all ofthe register settings, memory pointer values and the status of the state machines prior to enterirstandby mode. It can resume normal operation again when this bit is disabled.3) Oscillator shut off through BMRII.WARNING: This bit may only be set if using the internal oscillator. Setting this bit while using an external canned oscillat(can damage the chip.Due to the above danger, this bit can only be set (hardware protected) after the standby mode has been entered. Thus, accidentwrite can be prevented. The users need to be aware that the oscillator needs some time to stabilize. This startup time is typical]2 msec for SSI 78Q8373.The following programming sequence is recommended for entering this mode:i) Check that SSI 78Q8373 is idle (i.e. not in the middle of an operation).ii)iii)Set DLCR7 to '0' to enter standby mode.Set BMRII to '1' to shut off the internal oscillator.(SSI 78Q8373 is now in its lowest power consumption configuration).The 'wake up' sequence is as follows:i) Set BMRII to '0' to tum on the internal oscillator.ii)iii)Allow some time for the internal oscillator to stabilize. This is typically 2 m~cc.Set DLCR7 to '1' to go back to the normal mode.9-46

CONTROL AND STATUS REGISTERSThe registers in the SSI 78Q8373 can be divided into six groups: 1) Data Link Control Registers (DLCRO-7); 2) Node ID registers(IDR8-13); 3) Time Domain Reflectometry Registers (TDR14-15); 4) Hash Table Registers (HTR8-I5); 5) Buffer MemoryRegisters (BMR8-15); 6) PCMCIA Registers (CCRO-I).The Data Link Control Registers contain the transmit and receive status information, interrupt enable, SSI 78Q8373 setup andsoftware reset bit (DLCR6

5 CONTROL AND STATUS REGISTERS (continued)A register bit-map is also included for the Data Link Controller Registers, Buffer Manager Registers, and PCMCIA registers.Also shown are the default values for each register. Shaded bits are non-writeable.Bit 2COLBit 116COLBitORx InterruptEnableDLCR39-48

LEGEND DESCRIPTIONThe legend (column L in the register tables) used to describe register initial values, readability and writeability are denoted by thefollowing abbreviations:R: READABLEW: WRITABLEC: CLEARABLE: Writing a '1' clears this bit; writing a '0' has no effectH: CONDITIONALLY WRITABLE: The default values can only be changed depending on other conditions0/1: Power-up!Reset Default valueDATA LINK CONTROLLER REGISTERSThere are 8 Data Link Controller registers that will provide the status and control signals between the SSI 78Q8373 and host. Inthe following sections, each register bit will be explained.~.1 DLCRO· Transmit Status RegisterThis register provides the transmit status to the host. These status bits can also produce interrupt" if DLCR2 interrupt enable signalsare set (see DLCR2 for details). The status bits can be cleared by writing a '1' to the respective bit but writing a '0' has no effecton it. Note that more than one status bit can produce a common interrupt signal. Hence itis advisable forthe host to check this registerto find out how many of the status bits could have caused the genemtion of the interrupt signal.BIT76543210SYMBOL L DESCRIPTIONTXOK R,C,O TRANSMIT OK: When the packet is transmitted through the medium without any errorsor skipped due to excessive collisions, this bit is set high. If DLCR2 is enabled, thenthe bit can trigger an interrupt to the host.NET_BSY R,O NET BUSY: If this bit is read as 1, it indicates that the network is busy at the receiver.This bit reflects the status of the CRS signal.SELF_RX R,C,O SELF RECEPTION: The bit is used to indicate that self-reception has occurred. Writinga 1 or power reset will clear this bit. If DLCR2 is enabled, it can trigger an interruptto the host.TX_ERR R,O TRANSMIT ERROR: When read as a 1, this bit indicates a possible COllision on thenetwork or a loss of carrier during transmission. Automatically cleared on the nexttransmission. Writing a '1' or a '0' has no effect.JABBER R,O JABBER: When high, it indicates that excessive transmit length is detected by theinternal jabber timer. This is a serious error condition which only occurs when the chipmalfunctions. Can generate interrupts if enabled by the corresponding interrupt enablebit in DLCR2. This jabber error can only be cleared by hardware or software resetthrough DLCR6.COL R,C,O COLLISION: This bit is set high when a collision occurs on the data packet duringtransmission. The 7808373 performs up to 16 re-transmissions. If DLCR2 isenabled, it can trigger an interrupt to the host. The number of collisions is stored inDLCR4.16COL R,C,O 16 COLLISIONS: If a data packet has suffered 16 unsuccessful transmission then thisbit will set high. Generates an interrupt to the host if DLCR2 is enabled.HWR_ERR R,C,O HOST WRITE ERROR: When the host attempts to write data to the transmit buffermemory and did not get the response from 7808373 after 2.4 msec, this flag is set. Thisis to indicate that the transmit buffer is full. If DLCR2 is enabled, it can trigger aninterrupt to the host.I9-49

5.2.2 DLCR1 • Receive Status RegisterThis register provides the receive status to the host. These status bits can also produce interrupts if DLCR3 interrupt enable sign

:.4 DLCR3· Receive Interrupt Enable Reg isterThis register contains the bits to enable the status bits in DLCR1 to generate interrupts to the host.31T SYMBOL L DESCRIPTION7 PKT_RDY R,W,O PKT_RDY INTERRUPT ENABLE: When this bit is set high, it will enable PKT_RDYINT ENABLE(Packet Ready signal) to generate an interrupt.6 HRD_ERR R,W,O HRD_ERR INTERRUPT ENABLE: When high, enables HRD_ERR (Host Read Error)INT ENABLEto generate an interrupt.5 DMA_EOP R,W,O DMA_EOP INTERRUPT ENABLE: When high, enables the DMA_EOP to generate anINT ENABLEinterrupt.4 RMTRST R,W,O RMTRST INTERRUPT ENABLE: When high, allows the- RMTRST (Remote ResetINT ENABLEPacket Received) to generate an interrupt.3 SRT_ERR R,W,O SRT_ERR INTERRUPT ENABLE: When high, enables SRT_ERR (Received ShortINT ENABLEPacket) to generate an interrupt.2 ALG_ERR R,W,O ALG_ERR INTERRUPT ENABLE: When high, enables ALG_ERR (Alignment Error) toINT ENABLEgenerate an interrupt.1 CRC_ERR R,W,O CRC_ERR INTERRUPT ENABLE: When high, enables--CRC_ERR to generate anINT ENABLEinterrupt.OVRFLO R,W,O OVRFLO INTERRUPT ENABLE: When high, enables OVRFLO (Receive Buffer OverINT ENABLEflow) flag to generate an interrupt.°2.5 DLCR4· Transmit Mode RegisterThis register contains the collision count value (up to 16 collisions). SSI 78Q8373 will attempt to fe-transmit the current packet upto 16 times. After which, depending on the values setting in BMR 11, the host can either skip the current packet and continueto transmit remaining packets in the transmit buffer or re-transmit the current packet again.BIT7-4321°SYMBOL L DESCRIPTIONCOL3-0 R,O COLLISION COUNT: These 4 bits store the collision counter value. Bit 3 is the mostsignificant bit of the count.NO_BACK R,W,O NO BACKOFF ENABLE: When set to 1, it will disable the binary exponential backoffcircuitry.NOT_CB R,W,1 NOT_CONTROL BIT: The inverse of this bit is available for general use on th CB pin.EDLOOP R,W,1 ENDEC LOOP BACK: Active low. This bit enables the-loop back function of the78Q8370-ENDEC. Loop back is active when this bit is set to '0'.DSC R,W,O DISREGARD CARRIER: Program this bit to zero for normal network operation. Whenset to high, the transmitter will not defer to traffic on the network.I9-51

5.2.6 DLCR5 - Receive Mode RegisterThis register controls the way that SSI 78Q8373 receives a packet DLCR5 set high allows SSI 78Q8373 to accept packets thcontains alignment or CRC errors. DLCR5 set high allows SSI 78Q8373 to accept packets with packet length that is betwet:6 bytes and 2047 bytes (excluding preamble and CRC). Allowing the acceptance of a 6-byte packet is usually a diagnostic modThe Receive Buffer Empty (DLCR5

,7 DLCR5· Configuration Register 0liT SYMBOL L DESCRIPTION7 ENADLC R,W,1 ENABLE DATA LINK CONTROLLER: Active low, Enables the receiver and transmitterof 7808373. Setting this bit to high will reset all the state machines to their idle statesand allows access to Node 10 and Hash Table registers (depending on DLCR7settings).6 RAMSP R,W,O RAM SPEED: When set to 1, selects 100 nsec cycle SRAM: Otherwise, the SRAM isof 150 nsec cycle.5 HBYTE R,W1 HOST BYTE/WORD SELECT: If set high, host system bus will-operate in byte mode.If set to 0, it will operate in word mode.4 RBYTE R,H,1 RAM BYTE: When set high, the RAM databus will operate in b-yte mode, otherwise it willbe word mode. In PCMCIA mode, this bit will be internally hard set to 1. This is becausePCMCIA pinout makes use of the higher RAM databus. The following table is valid OOLYfor Generic Bus mode:HBYTE RAM BUS HOST BUFFER0 0 word--word _._-.0 1 word byte1 0 DO NOT USE1 1 byte byte3,2 TS1,O R,W,O,1 TRANSMIT BUFFER SIZE: Sets configuration of transmit buffer.TS1,O TX BANKS SIZE OF TOTAL TXTX BANK BUFFER00 1 2 KB 2 KB01 2 2 KB 4 KB10 2 4 KB 8 KB11 2 8 KB 16 KB1,0 BS1,O R,W,O,1 BUFFER MEMORY SIZE: Sets configuration of total Buffer Size.BS1 BSO SRAM SIZE0 0 8 KB0 1 16 KB1 0 32 KB1 1 64 KB------I9-53

5.2.8 DLeR7 - Configuration Register 1BIT SYMBOL L DESCRIPTION7,6 CTM1,0 R,H,OO CONTROLLER TEST MODES: Write 00 for normal operation.5 NOT_STBY R,W,1 NOT STANDBY (POWER DOWN): Active low. The power down mode is for energysaving. If set high, it enables power to the chip for all functions.4 RDYSEL R,- READY SELECT: Reflects the real time image of the RDYSEL pin (pin 94). If RDYSELpin is high, READY interface with the host is active high. Otherwise it is active low.3,2 RBNK1,0 R,W,O,O REGISTER BANK SELECT: To select the upper 8 registers as shown below:RBNK1 RBNKO REGISTERS0 0 DLCRO-7 + IDR8-13 + TDR14,150 1 DLCRO-7 + HTR8-151 0 DLCRO-7 + BMR8-151 1 RESERVED1 EOPSEL R,W,O END OF PROCESS PIN SIGNAL POLARITY: When high, EOP pin is active high. Whenlow, EIP pin is active low.0 INTLMOT R,W,O INTEL or MOTOROLA MODE: System must be in word mode. This applies to the nontransmittedbuffer header and the packet data. When this bit is low (INTEL MOOE), theleast significant byte will occupy the even address. Otherwise, the most significant byteswill occupy the even address (MOTOROLA MOOE).5.3 NODE 10 REGISTERS5.3.1 lOR 8:15· Node 10 RegisterslOR BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO8 107 106 105 104 103 102 101 1009 1015 1014 1013 1012 1011 1010 109 10810 1023 1022 1021 1020 1019 1018 1017 101611 1031 1030 1029 1028 1027 1026 1025 102412 1039 1038 1037 1036 1035 1034 1033 103213 1047 1046 1045 1044 1043 1042 1041 1040The NodeID registers (IDR8-13) are located in register bank '00' (DLCR7 = 00) at address xxx8H through xxxDH. Thunique Ethernet address is written into these registers during the initialization of the node with the first byte of the Ethernet addre~atIDR8. The IDRregisters are readable and writeable only when ENAOLC = 1 (DLCR6

The Time Domain Reflectometry (TDR 14-15) registers provide a means of locating a fault on the network. The TDR registers arelocated in the same register bank as the IDR8-13 but at address xxxEH through xxxFH. This 14-bit diagnostic counter keeps a countof the number of bits that has been transmitted during transmission of a packet starting from the preamble and including the CRCbits. TDR14 is the least significant byte and TDR15 is the most significant byte of the counter. Fourteen bits are sufficient for thepacket transmission of an IEEE compliant LAN. The remaining 2 bits (TDRI5

5.6.2 BMR10 - Transmit Packet CounterThis register consists the 1RANSMIT START BIT (TXST) and the total packet count for the SSI78Q8373 to transmit. The paccount is the number of packets that the host wants to transmit. To activate transmission, the packet count must be written the satime that the TXST bit is set to a 1. The user should not write into this register until the packet count has reached zero.BIT76-0SYMBOL l DESCRIPTIONTXST R,W,O TRANSMIT START BIT: When the packet(s) in the transmit buffer is ready for transferto the network, this bit is set to 1 in order to activate the transmit operation. Always readas a O.PACKET R,W,O TRANSMIT PACKET COUNT: The total number of packets to be transmitted to theCNT network. Each time a packet is successfully transmitted , the packet count is decremented.The host can read this register to check how many packets have not been transmitted.5.6.3 BMR11 -16 Collision ControlThe setting of this register determines the actions of the controller to be taken after 16 consecutive attempts to transmit a packThere are four modes (controlled by HALT, RESTART and SKIP bits in the register) to be selected:(1) automatic re-transmission of colliding packet(2) automatic skip of the colliding packet after 16 attempts(3) Halt for host intervention and retry transmission of colliding packet(4) Halt for host intervention and discontinue transmission of colliding packet.BIT765-3210SYMBOL l DESCRIPTIONOSC_OFF R,H,O OSCILLATOR SHUTOFF: When enabled ('1 '), this bit shuts off the internal oscillator.Setting this bit while using an external canned oscillator can damage the chip. For thisreason, this bit can only be set after the standby mode is entered (by settingDLCR7 = '1 ')AUTOPD R,W,O AUTO POWER: Upon power-up/reset, the chip is in automatic power managementmode. This mode can be disabled by writing a '1' to this bi!.RESERVED - RESERVED BIT.HALT R,W,O 16 COLLISION CONTROL: These three bits control the action to be taken by 78Q8373RESTARTin the event that 16 collisions occur in the transmission of a packet. Host interventionSKIPis possible as shown below.HALT RE-START SKIP DESCRIPTION OF ACTION TAKEN1 X 1 Do not halt. Skip colliding packet andcontinue transmitting.1 X 0 Do not halt. Retry -transmission of collidingpacket.0 X X Halt and await instruction from host forBMR11. 11' : results in colliding packetskipped and transmission resumed.10':results in colliding packet re-transmitted.9-56

.4 BMR12· DMA EnableThe DMA RENA and DMA TENA activates the DMA operation as follows:~IT SYMBOL L DESCRIPTIONr-2 RESERVED - RESERVED BIT.1 DMA_RENA R,W,O RECEIVE READ DMA ENABLE: When enabled (active high), it activates receive readDMA from the host.0 DMA_TENA R,W,O TRANSMIT WRITE DMA ENABLE: When enabled (active high), it activates transmitwrite DMA from the host to ICE's buffer memory.;.5 BMR13· DMA Burst & Transceiver Mode Register31T SYMBOL L DESCRIPTION7 APOL R,W,O AUTO POLARITY: When set to 0, it enables the automatic polarity correction of thereceived data. The reverse polarity is identified from either the start of idle signal or linkpulses.6 RTH R,W,O REDUCED THRESHOLD: When set high, twisted pair receive threshold is reduced by3 dB (for longer than the recommended 100 meters cable).5 ENLI R,W,O ENABLE LINK INTEGRITY: When set low, both transmit and receive link test functionsare enabled. When high, no link test is performed and the link status is assumed to beup and twisted pair port is selected if auto select mode is enabled. When this bit isenabled, the transmit link pulses function is always active regardless fo the status of thelink.4 PORT_SEL R,W,O PORT SELECT: This bit manually selects between Twisted Pair (when 0) or AUI (when1) and is only applicable when ASEL bit (BMR13

5.6.6 BMR14· Receive Filter & Interrupt Enable RegisterBIT SYMBOL l DESCRIPTION7 RESERVED - RESERVED BIT.6 INT ENABLE R,W,O LINK DOWN INTERRUPT ENABLE: When high, enables LD (BMR15

PCMCIA REGISTERSThere are 2 registers for the PCMCIA interface. Each bit is explained in the following sections .. 1 CCRO· Configuration Option Register~IT SYMBOL L DESCRIPTION7 SRESET R,W,O SYSTEM RESET: Setting this bit high is equivalent to assertion of hardware reset(except that this bit is not cleared). This bit is also reflected at the XRST pin to reset therest of the devices on the card.6 LevlREO R,W,O LEVEL MODE INTERRUPT REOUEST: When high, levefmode interrupt is selected.When low, pulse mode interrupt is selected.5:0 CI(5:0) R,W,O CONFIGURATION INDEX: This field is written with the index number of the entry in theCard's Configuration Table that corresponds to the configuration which the systemchooses forthe card. When CI(5:0) is 0, the chip does not respond to any I/O cycle, butwill use the memory cycle.'.2 CCR1 • Card Configuration and Status Register31T SYMBOL L DESCRIPTION7 NI R,O NOT IMPLEMENTED6 NI R,O NOT IMPLEMENTED5 IOis18 R,W,O 1/0 is 8 bit: This bit set high indicates to the host that the system is only capable of 8-bittransfer on its data bus. Since the 7808373 can support 16-bit transfer, the default valueof this bit is '0.' This bit does not affect the host byte/word mode setting of the 8373 whichis set by HBYTE (DLCR6 bit).4 RESERVED R,O RESERVED.----3 Audio R,W,O Audio Enable: This bit set to one will enable signals from SPKRIN to SPKR.2 PwrDwn R,W,O Power Down:This bit has the same function asthe NOT_STBY bit (DLCR7

6 78Q8373 & HOST INTERFACE CONFIGURATION6.1 PCMCIA INTRODUCTIONPCMCIA is an acronym for Personal Computer Memory Card International Association. Its goal is to promote interchangeabiliof PC Cards among a variety of computer and other electronic products.PC Cards are approximately 54 by 85 millimeters, but differ in thickness. Type 1 cards are 3.3 mm thick and type 2 cards a5.0 mm. All have a 68-pin interface at one end.6.1.1 Memory and 1/0 Address SpaceA Memory Address Space of 64 Mbytes (AO-A25) is permitted for each memory card installed in a system. The Memory AddreSpace consists of Common Memory and Attribute Memory. The Common Memory may be accessed by a host for memory reoand write operations.There is an additional 64 Mbytes address space for Attribute Memory which is selected by the REG signal at the interface. TIAttribute Memory is divided into• Card Information Structure (CIS) - contains the manufacturer's description of card capabilities and specifications.• Card Configuration Registers (CCR) - a set of registers that allows the card to be configured by the host.The I/O Address Space of 64 Mbytes is shared and divided among all cards installed in the system. The I/O interface requires ththe Memory-Only Interface also be implemented within the same socket, and that the Memory-Only Interface be selected in tlsocket when no card is inserted and immediately following Card reset and the application of V cc to the card. The I/O interface al~supports additional signals like IREO, 101S16, 10WR, lORD, SPKR, INPACK and STSCHG.The following diagram summarizes which address space that the host is accessing depending on the logic values of REG, I/O realwrite and Memory read/write signals.OE,WECE1, CE2COMMONMEMORYfATTRIBUTEMEMORYCISCCR10RD,IOWRCE1, CE2[]~ __________--) "--____ ~ ~-.JyyMEMORY ADDRESS SPACE1/0 ADDRESS SPACEFigure 6-1. Host Address Space Accessing9-60

PCMCIA INTERFACE FOR 551 78Q8373SSI 78Q8373 complies to the PCMCIA Release 2.1 Specifications and powers up as a memory card when in PCMCIA mode. Toenter the I/O mode, the Configuration Index CI(5:0) in the CCRO register must be written with a non-zero value. Only then can theother registers of SSI 78Q8373 be accessed by the host.In the Attribute Memory Address Space, the CIS is located at address 0 and the CCR is located at an offset value determined bythe CCRA pin, illustrated in Figure 6-2 below.4000000hl«202h 1---__ C_C_R_1 __-I200h I--__ C_C_R_O __-fCISOh ~ ______ --'CCRA = A82 9 = 512 (decimal)= 200 (hex)Figure 6·2. Attribute Memory Address 5paceI9-61

CCRA pin must be connected to another address pin apart from A(3:0). For instance, if CCRA is connected to AS, then CCR(located at address 200h, an offset of 200h from address O. An example of how to use the SSI 7SQ8373 with a Flash MemoryEEPROM is shown below.(CCRA - A8) - 0, A(7:0)0(7:0) FLASHMEMORYOE ORWE PARALLELE2FCEI 512 x 80(7:0)OEWESSI78Q8373(CeRA = A8) = 1, A(3:0)CE, I/O SIGNALSPCMCIA BUSFigure 6-3. SSI 7808373 Interface to Flash Memory or EEPROM6.3 GENERIC BUS INTERFACE FOR SSI 7808373For non-PCMCIA applications, the SSI 78Q8373 can interface with the host via a 'generic' bus interface. Transferring of datpacket status, packet sizes and so on can be accessed easily by the host either by using programmed I/O or DMA modes. Packeto be transferred to the network must first be stored in the buffer memory via a register called Buffer Memory Register 8 (BMR~Similarly, packets to be read by the host is retrieved via the BMR8. Thus BMR8 acts as a window to the buffer memory.To interface with the host, the SSI 78Q8373 has 4 host address pins (HA

78Q8373 & MEDIUM INTERFACE CONFIGURATIONThe SSI 78Q8373 has an integrated twisted pair transceiver and supports interface to coax transceiver through AUI signaling. Thetwo port selection (either AU! or TP) is done automatically based on the status of link integrity. In a link-good state, the TP port isselected and in a link-fail state, the AUI port is selected. This automatic selection can be disabled by writing a '1' to register bitBMR 13 and manual selection is in effect. In manual selection mode, the A UI or TP port may be selected by writing appropriatevalue to BMR13.TWISTED PAIR TRANSCEIVERThe TP transceiver supports complete IEEE 10BASE-T functionality as well as several enhanced functions such as autopolaritydetection and correction, smart-squelch logic and long distance mode .. 1 Link IntegrityDuring idle periods, link pulses are generated and received by both MAUs (Medium Attachment Units) at either end of the twistedpair to ensure that the cable has not been broken or shorted. A positive, 100 ns Link Integrity signal is generated and transmittedby the SSI 78Q8373 every 13 ms during idle periods. The chip assumes a link-good state if it receives valid link pulses or a packet.Ifneitherisreceivedfor 105 ms, theSSI78Q8373 enters alink-fail state. It then needs4 consecutive positive link pulses (or 8 negativelink pulses) to resume link-good state. Only link pulses spaced between 3 ms and 105 ms are considered valid.In a link-fail state, the SSI 78Q8373 disables normal Transmit, Receive, Collision, loopback and SQE test functions. The receptionof a packet will put the device in a link-good state. However, that packet will not be relayed to the Manchester ENDEC unit.Subsequent packets will be relayed as per normal as long as the device remains in a link-good state.The link status is flagged by register bit BMR15 as well as the LEDL TR pin. The Link Integrity function can be disabled bywriting a '1' to BMRI3 which forces the SSI 78Q8373 into a link-good state.:.2 AutopolarityBecause twisted pair differential signals can easily be inverted due to wiring errors, the SSI 78Q8373 incorporates autopolaritydetection and correction circuitry. Polarity circuitry monitors the polarity of the received SOl (Start Of Idle) and link pulses andcorrects the data internally if the signal is inverted. The inverted polarity is flagged by register bit BMR 15 and the autopolarityfunction may be disabled by writing a '1' to BMRI3.1.3 Smart Squelch LogicThe twisted pair squelch logic dynamically adjusts the sensitivity and threshold of the receiver. Before signals begin to arrive at theTPIP/TPIN pins, the SSI 78Q8373 is in a high noise rejection, squelch state and no data is passed through. A valid incoming dataneeds to trip the threshold detectors with three peaks of alternating polarity occurring within a 400 ns window. Once a signal hasbeen qualified by the squelch circuitry, the SSI 78Q8373 assumes an unsquelch state with reduced threshold. See the datasheet forthe squelch and unsquelch threshold levels.At the beginning of each packet there is a preamble consisting of alternating ones and zeros resulting in a 5 MHz Manchester signalon the twisted pair. The SSI 78Q8373 uses the standard 1 OBASE-T specified threshold levels to unsquelch the incoming preamble.As data begins to arrive, the 10 MHz component of the Manchester encoded signal may have less amplitude since it is attenuatedmore than the 5 MHz component. For this reason, the threshold levels are reduced in the unsquclch state. This greatly reduces thechance of prematurely detecting the SOl by the threshold detectors.The twisted pair smart squelch circuitry is returned to a squelch state by any of these conditions: a normal SOl signal, an invertedSOl signal or a missing SOl signal. A missing SOl signal is assumed when no transitions crossing the threshold detectors haveoccurred for 250 ns after a packet has been received. In this case, a normal SOl signal is generated and appended to the received data.1.4 Long ModeWriting a' l' to BMR13 places the SSI 78Q8373 in long mode where the thresholds of the detectors are lowered to support longercable length than the recommended 100 meters. Dynamic squelch circuitry is still functional in long mode. The squelch thresholdof the long mode is the same as the un squelch threshold of the normal mode and the unsquelch threshold of the long mode is another3 dB down.1.5 Collision DetectionA collision happens when both transmitting and receiving functions occur simultaneously in the twisted pair transceiver. Thecollision signal originating from the twisted pair transceiver is multiplexed together with the collision signal from the AUI moduleand is relayed to the controller. Collisions will not be reported when the device is in a link-fail state. The internal collision signalis also activated when a jabber condition occurs or when the SQE test is being performed.I9-63

7.1.6 SQE TestAn internal Signal Quality Error (SQE) test is also provided on chip. After each packet transmission, an SQE signal (also referrto as "heartbeat" signal) is sent internally to the controller. This feature is provided to match the coax transceiver functionality7.1.7 JabberAn independent circuit monitors the length of each transmission and inhibits it if it surpasses a 26.2 ms maximum allowed transntime. This function keeps a damaged node from continuously transmitting on the network. When jabber occurs, the transceiver aldiscontinues loopback and sends a collision signal to the controller. The jabber status is flagged by register bit DLCRO.7.1.8 Normal Loopback7.1.9 LEDThe twisted pair transceiver provides the normalloopback function specified by the lOBASE-T standard. The normalloopbafunction is disabled when a collision occurs during which the received data from TPIP/N is passed through instead. Link fail aJjabber states also disable the normalloopback.The LEDLT pin serves functions. A connected LED lights up during link-good state and blinks off temporarily during transmissilactivity.7.1.10 TP DriverThe transmit driver consists of four differential signals, the true and Complement transmit data TPOP, TPON and their respecti'50 ns delayed signals TPDP, TPDN. These drivers, when combined with the resistor network shown in Fig 7.1, provide the signpre-equalization required by the lOBASE-T standard.A Manchester encoded data consists of 10 MHz (50 ns) component as well as 5 MHz (100 ns) pulses. A twisted pair cable attenuata 10 MHz signal more than a 5 MHz signal. Equalization is required to decrease the relative power in the 5 MHz com ponetransmitted by the SSI 78Q8373. This causes the 10 MHz and 5 MHz components of the signal to have approximately the same powFigure 7.1. Twisted Pair Interface Connections (5 volts)(contact Silicon Systems for 3-volt connections)9-64

content at the far end of the twisted pair. To achieve the power reduction of the 5 MHz component, the four transmit signals aresummed resistively as shown in Fig 7.2. The values of the five network resistors are selected to allow the twisted pair line to beterminated in 100 ohm.The drivers are designed to have equal rise/fall times as well as balanced low-to-high and high-to-low propagation delays to minimizecommon-mode energy. It is also important to maintain equal load capacitance from the board layout for each data output so as tomaintain the equal rise/fall times and propagation delays.The twisted pair magnetics and filters shown in Fig 7.2 isolate the SSI 78Q8373 from the twisted pair media and reduce the radiatedemissions. As a result of the well matched drivers, the common-mode choke is optional and the device still meets the lOBASE-Tstandard of +/- 50 m V of common-mode energy. Various integrated modules are available with di fferent level of integration froma few vendors listed in Table 7.1.·able 7.1ption Resistor Network EMI Filter & Isolation Common-mode Choke1 Discrete 1) Pulse PE654212) Valor PT3877 (Optional)3) Bel Fuse A556-2006-DE4) FilMag 78Z1120B2 Discrete 1) Pulse PE654312) Valor FL 101231 Bel Fuse 0556-2006-01 0556-3392-003 1) Pulse PE654852) PCA EPE6052G.11 TP ReceiverThe SSI 78Q8373 twisted pair receiver uses a high-speed differential comparator designed to preserve the edge timing of theincoming data. The comparator architecture significantly minimizes the bit jitter added by the transceiver. Dual threshold detectorsare used by the twisted pair smart squelch circuitry to qualify both positive and negative signal peaks. The threshold levels aredynamically controlled to further enhance the immunity to noise. Refer to the smart squelch logic section.ATTACHMENT UNIT INTERFACE (AUI)AUI is a standard Ethernet interface that connects Data Terminal Equipment (DTE) to a Medium Attachment Unit (MAU). Thereare 3 pairs of differential signals that connect to an AUI: one pair for transmission, one pair for reception and the other one pair forcollision indication. A typical AUI connection diagram is given in Fig 7.2.~.1 AUI DriverThe SSI 78Q8373 AUI drivers have been designed to provide balanced differential voltage levels when signaling. The drivers haveequallow-to-high and high-to-Iow propagation delays to provide minimal skew.At the end of transmission, the AUI drivers ramp to VDD slowly to avoid undershoot. An internal digital to analog converter ensuresthat the driver ramp-up occurs over approximately 8 J..IS resulting in a smooth transition into an idle state.~.2 AUI ReceiverThe AUI receiver uses high-speed differential comparator to preserve the edges and duty cycle of the incoming data. A thresholddetector and squelch circuit are used to qualify valid data from noise. During idle, the AUI is in a high noise rejection squelch state.When the first negative edge crosses the threshold of the threshold detector, the AUI enters into unsquelch state and begins receivingdata. The AUI reverts back to squelch state by a normal Start-Of-Idle (SOl) signal or a missing SOl signal. A missing SOl signalis assumed when no transitions haveoccuredon the receiver inputs for 175 ns. In this case, an SOl signal is generated and appendedto the received data.I•9-65

7.2.3 Termination and IsolationThe AUI cable is specified by the standard to have characteristic impedance of 78 ohms. For mini mal reflection, the A UI cable tto be terminated with a 78 ohm resistance at the far end. A 0.1 J..IF' capacitor connected to the mid val ue point of the termination resishelps to bypass common mode noise picked up by the AUI cable. This capacitor is optional for on-board transceiver because th(will be minimum common mode noise.The SSI 78Q8373 AUI supports both transformer coupling as well as capacitive coupling as shown in the figure. Please note tlfor capacitive coupling, the termination resistors have to reside at the inputs of the SSI 78Q8373 AU! receivers.SSI78Q8373REXTfRm =20 kDOPDONDIPDINCIPCINTRANSMIT--. lopISOLATIONRECEIVE ¢TN ISOLATIONCOLLISION· ¢TN ISOLATION"(AUI CABLE) · ·---------------,· - - - - - - - - - - -" if 10 BASE-5TRANSCEIVERTN (TERMINATION NETWORK)1)RT/2 392) ~QTNTRANSCEIVER~ MEDIUM00ISOLATION1) TRANSFORMER COUPLINGFOR ON-BOARDTRANSCEIVER~O.1 f.JFRT/2 ,FOR OFF-BOARDTRANSCEIVER2) CAPACITIVE COUPLINGFigure 7.2. Attachment Unit Interface (AUI) Connections9-66

USING THE SSI 78Q8373 ON THE NETWORKThis section deals with the transmission of data using the SSI 7SQ8373 from the host point of view. It will cover the interactionof register configurations and the actual transmission executed. For more detailed information on the function of the Data LinkController in this respect (with regards to Inter-Frame Gap, fairness and equality of the line, Jam Pattern, Backoff Algorithm etc.),please refer to the Transmitter Circuits Section.INITIALIZATIONInitialization begins with a hardware reset immediately after power on. A pulse with a minimum of 200 nanosecond duration isrequired to be applied to the RESET pin. This resets ICE's internal pointers and registers to their initial state. ENADLC, DLCR6= 1 acts as a software reset resetting all buffer memory pointers. The software reset does not change the contents of the status andcontrol registers or the DLCR 0-7, IDR8-13, TDRI4-1S, HTRS-IS and BMRI0-1S registers. Hardware reset sets the ENADLC bithigh.The initialization of the 8373 by the host include the loading of the Ethernet Address of the node into IDRS-13 with IDR8 as theleast significant byte of the address and group addressing in the Hash Table registers (if desired). To access the Node ID registers,(or any of the other bank of registers) the following is executed. Please note that all register values arc in hexadecimal notation unlessotherwise stated.a) Disable the DLC by setting DLCR6 = 1b) Select the register bank by setting DLCR7 as required.DLCR7 = 00 (default setting after hardware)DLCR7 = 01 (selects Hash Table registers)DLCR7 = 10 (selects Buffer Memory registers)DLCR7 = 11 (Reserved)The host should load the Ethernet Address and Hash Table Configurations at this stage.c) The default settings of DLCRO-7 after a hardware reset or power on are as follows:DLCRO = 00 (Transmit Status)DLCRI = 00 (Receive Status)DLCR2 = 00 (Transmit Interrupt Mask)DLCR3 = 00 (Receive Interrupt Mask)DLCR4 = 06 (Transmit Mode)DLCRS = 41 (Receive Mode)DLCR6 = B6 (Configuration Register 1)DLCR7 = 20 (Configuration Register 2)The host can now select the type of interrupt enables that should be activated in DLCR2-3. Unless a loop back mode is requiredin a testing environment, DLCR4 need not be changed.d) The default setting ofDLCRS allows the reception of normal packets i.e. packets that meet the IEEE requirements and doesnot contain any errors. The host can enable the 'remote reset' capability of SSI 78Q8373 or enable the reception of 'bad packets'with the activation of appropriate bits in this register. The Address Mode bits can be reprogrammed for hash table acceptanceif necessary. Please refer to the Data Link Controller Registers Section for details.e) DLCR6 configures the size of the transmit buffer and overall buffer size. This should be changed according to the host'srequirements. DLCR6 is reset to 0 for transmission and reception activities and set to I for access to the Node ID and HashTable Register Banks.t) DLCR7 configures the access to the 3 register banks. To access the Node ID and Hash Table Register Banks, DLCR6= 1 must be set to 1. DLCR7 sets the big endian and little endian byte ordering depending on the host's configuration.g) BMRII denotes the action to be taken by SSI 7SQ8373 should a 16 collision happen on the network. This should beprogrammed accordingly before transmission or the default setting will be used.PACKET TRANSMISSION USING THE SSI 78Q8373!.1 Transmission Without ContentionBefore initiating a transmission, the host wi11load in the data packet(s) into the transmit buffer via BMR8 (and BMR9 if in wordmode). Each data packet will contain a 2-byte header of the total packet length, destination and source addresses and the data to betransmitted. The host initiates transmission by writing the number of packets into BMR 10 and setling TXST bit = 1 (BMR 10

The 2-byte header is loaded into a counter within the transmit circuit. The counter will decrement its value as each byte is transmitto the medium. When it reaches zero, this signifies that an entire data packet has been transmitted. At the same time, the paccount value (pACKET CNT

ECEIVE PACKET:INTEL FORMATMOTOROLA FORMATIGH BYTE LOW BYTE HIGH BYTE LOW BYTEeserved Packet status Packet status Reservedata length high byte Data length low byte Data length low byte Data lenath hjgh byteestination address 2 nd Destination address 1 st Destination address 1 st Destination address 2 nd(te byte byte byteource address 2 nd byte Source address 1 st byte Source address 1 st byte Source address 2 nd byte:math field LSB Lenath field MSB Lenath field MSB Lenath field LSBata field 2 nd byte Data field 1 st byte Data field 1 st byte Data field 2 nd bytePACKET RECEPTION USING THE SSI 7808373:.1 Reception Without ContentionWhen not transmitting, SSI 78Q8373 will consistently monitor the network. To determine if a packet on the network is for the node,SSI 78Q8373 will check the destination address of the packet. Depending on the Address Modes (DLCRS

e accepted by SSI 78Q8373. The SRT _ERR bit (DLCR 1

-~---~ ---__--_.--"-'---~~------~------~~-.---Application GuideMonolithic Dual-ToneMulti-Frequency(DTMF) ReceiversINTRODUCTIONThe Silicon Systems integrated DTMF Receivers andTransceivers are complete Touch-Tone detection andgeneration systems. Each can operate in a stand-alonemode for the majority of telecommunications applications,thereby providing the most economical implementationof DTMF signaling systems possible. Each combinesprecision active filters and analog circuits withdigital control logic on a monolithic CMOS integratedcircuit. SSI DTMF chip use is straightforward and theexternal component requirements are minimal. Thisapplication guide describes device operation, performance,system requirements and typical application circuitsfor the SSI DTMF chips.HOW THE SILICON SYSTEMS DTMFCIRCUITS WORKGENERAL DESCRIPTION OF OPERATIONThe task of a DTMF Receiver is to detect the presence ofa valid DTMFsignalona telephone lineorothertransmissionmedium. The presence of a valid DTMF signalJanuary 1993indicates a single dialed digit; to generate a valid digitsequence, each DTMF signal must be separated by avalid pause.Table 1 gives the established Bell system standards fora valid DTMF signal and a valid pause. The SSI DTMFReceivers meet or exceed these standards.Similar device architecture is used in all SSI DTMFReceivers. Figure 1 shows the SSI 75T202 Block Diagram.This architecture is implemented in all SiliconSystems single chip receivers, as well as SSi Transceivers.In general terms, the detection scheme is asfollows: The input signal is pre-filtered and then split intotwo bands, each of which contains only one DTMF tonegroup. The output of each band-split filter is amplifiedand limited by a zero-crossing detector. The limitedSignals, in the form of square waves, are passed throughtone frequency bandpass filters. Digital logic is then usedto provide detector sampling and determine detectionvalidity, to present the digital output data in the correctformat, and to provide device timing and control.PARAMETEROne Low-Group Tone, andOne High-Group ToneFrequency ToleranceAmplitude RangeRelative Amplitude (Twist)DurationInter-tone PausesVALUE697, 770, 852 or 941 Hz1209,1336,1477 or 1633 Hz--------~- ------ _. ~fo ± (1.5% + 2 Hz)--I---24 dB ~ A ~ 6 dBm @ 600n (Dynamic Range 30 dB).. _--~-..._------_._----~-.. ~-~-~--.-------8dB ~ High Group Tone ~ +4dBLow Group Tone- -"-_.-- ------~----40 ms or longer40 ms or longerTABLE 1: Bell System Standards-------- --- ----~-~---I0193 - rev. 9-71 DTMF Receiver Application Guide

PERFORMANCE CONSTRAINTSSPEECH IMMUNITY AND NOISE TOLERANCEThe two largest problems confronting a DTMF Receiverare:1) Distinguishing between valid DTMF tone pairs andother speech or stray signals that contain DTM Ftone pairfrequencies. This is referred to as SpeechImmunity.2) Detecting valid tone pairs in the presence of nOise,which is typically found in the telephone (or othertransmission medium) environment. This is referredto as Noise Tolerance.The SSI DTMF Receivers use several techniques todistinguish between valid tone pairs and other straysignals. These techniques are explained in later sections.Briefly, the techniques are: .1) Pre-filtering of audio signal. Removes supplynoise and dial tone from input audio signal andemphasizes the voice frequency domain.2) Zero-cross detection. Limits the acceptable levelof noise during detection of a tone pair. Importantfor speech rejection.3) Valid tone pair/pause sampling. Samples thedetection filters and checks for consistency beforea valid tone is declared.DETAILED DESCRIPTION OF OPERATIONAUDIO PREPROCESSORThe Audio Preprocessor is an analog filter that bandlimits the input analog signal between 500 Hz and 6 kHz.In addition, it emphasizes the 2 kHz to 6 kHz voice region.Band limiting suppresses power supply and dial tonefrequencies, and high frequency noise. The emphasizedvoice region helps to equalize the audio response sincemany phone lines tend to roll off at about 1 kHz. Inaddition, preservation of the upper voice frequencies isimportant in providing speech immunity.TONE BAND SPLITTINGAfter the analog signal is preprocessed, it is split into twobands, each of which contains only one DTMF toneED (7g~t~)CLRDVDVHEXJ828lMzDlD2D408ENVP.GNDIN1633FIGURE 1: SSI75T202 Block DiagramDTMF Receiver Application Guide 9-72

group. The band-split filters are actually band-stop filtersto maintain all frequencies except the other tone group;this is done to maintain all analog information to enhancespeech immunity but not allow the other tone group to actas interfering noise for the band being detected. Theseband-stop filters have ''floors'' that limit the amount oftone pair twist which further enhances speech immunity.See device data sheets for acceptable twist limits.ZERO-CROSSING DETECTORSThe output of each band-splitfilter is amplified and limitedby a zero-crossing detector (limiter). The function of thezero-crossing detector is to produce a square wave at theprime frequency emanating from the band-split filter. If apure tone is not present, as in the case of voice or otherinterfering noise, a rectangular wave with a variableperiod will result. Proportional to the interference, thelimiter output power is spread over a broad frequencyrange as the zero crossings "dither." When a high levelof noise or speech occurs, no single bandpass filter pairwill contain significant power long enough to result in atone detection. On the other hand, when a pure DTMFtone exists with acceptable noise levies, the output of thelimiter will not have any significant dither and tone detectionwill occur. The zero-crossing detector also acts asAGC (Automatic Gain Control) in that the output amplitudeis independent of input amplitude; this additionallyestablishes an acceptable signal-to-noise ratio not dependenton tone amplitude.BANDPASS FILTERS & AMPLITUDE DETECTORSThe bandpass filters perform tone frequency discrimination.Their responses are tailored so that if the frequencyof the limited square wave from the zero-crossing detectoris within the tone frequency tolerance, the fitler outputwill exceed the amplitude detector threshold. The amplitudedetectors are interrogated periodically by the digitalcontrol circuitry to acertain the presence of only one tonein each band for the required duration. In a similarfashion, valid pauses are measured by the absence ofvalid tone pairs for the specified time.TIMING AND LOGICDuring the qualification process, the output decodergererates the proper digital code for the received DTMFtone pair. Afterthe fidelity and duration ofthis signal havebeen verified, the timing circuitry latches this code intothe output register and raises the data valid (DV) flag.The only precision external element needed for the SSIDTMF Receivers is a 3.58 MHz parallel resonant crystal(color-burst frequency) with a .01 % tolerance for the onboardoscillator. A 1 Mn 10% resistor should be connectedin parallel with the crystal. This generates thepreCise clock for the filters and for the logic timing andcontrol of the chip.CIRCUIT IMPLEMENTATIONStandard CMOS technology is used for the entire circuit.Logic functions use standard low-power circuitry whilethe analog circuits use precision switched-capacitorfiltertechnology.HOW TO USE THE SSI DTMF RECEIVERSPRECAUTIONSAlthough static protection devices are provided on thehigh-impedance inputs, normal handling precautionsobserved for CMOS devices should be used.All CMOS parts are prone to a destructive latch-up mode.This behavior is inherent to these parts due to theirphysical structure. The latch-up mode can best bedescribed as a low impedance, high current state existingbetween the power supply connections on a CMOS chip.This is also referred to as triggering of parasitic SCRbehavior.The most common cause of a latch-up mode is operatinga CMOS part outside its rated power supply voltage. Thisover-voltage need not be applied at power supply pinsonly to cause latCh-up. Latch-up can occur when overvoltageis applied at any input oroutput. Forthe SSI DTMFReceivers & Transceivers, the pin voltages should beconstrained to the range between VN - 0.5V and VP +0.5V (except the analog input pin whose conditions arediscussed below). Clamping diodes should be utilizedwherever necessary to ensure~that voltage ratings arenot exceeded.Another cause for latch-up is fast dv/dt transients affectingthe chip. These transients are encountered in applicationsthat require the connection/disconnection of "live"boards. While these applications are very rare and theirimplementation is best avoided, it must be mentionedthat whenever they are necessary, they present a severeenvironment for CMOS parts. Care must be taken insuch instances to ensu re that grou nd planes and rails areconnected first and disconected last. This will go a longway in eliminating voltage transients.Voltage transients that exist on power lines must also beeliminated. High voltage transients caused by switchingof high current devices can trigger latch-up. High frequencydecoupling is a requirementforthe proper operationof the SSI DTMF devices. A 0.01J..lF to a 0.1J..lFceramic decoupling capacitor should be connected to thepower supply pin at the Chip.I9-73DTMF Receiver Application Guide

+V (12V)Vp12 VOLTSSIDTMFOPEN COLLECTOR INTERFACEFIGURE 2: Interface Circuit for Conversion from TTL Output Levels to 12V SSI DTMF Input LevelsPOWER SUPPLYExcessive power supply noise should be avoided, and toaid the user in this regard, power supply hook-up optionsare provided onsome devices.Since the digital circuitry of the devices possess the highnoise immunity characteristics of CMOS logic, it is theanalog section that is affected most by power supplynoise. On those SSI DTM F Receivers that have separateAnalog Negative and Digital Negative supply connections(grounds), namely VNA and VND, an unfilteredsupply may be used at VND. It is necessary that VND andVNA differ no more than 0.5V.The analog circuitry of the devices require low powersupply noise levels as specified on the device data sheet.The effects of excessive power supply noise are decreasedtone amplitude sensitivity and less tone detectionfrequency bandwidth. Power supply noise can besignificantly reduced by decoupling the chip with a 0.1 fJ.Fceramic capacitor. Power supply noise effects will beslightly less if the analog input is referenced to VP. Thisis normally accomplished by connecting VP to groundand utilizing a negative power supply.DIGITAL INPUTSThe digital inputs are directly compatible with standardCMOS logic devices powered by VP and VN (or VND).The input logic levels should swing within 30% of VP orVN to insure detection. Any unused input must be tied toVN or VP. Figure 2 shows a method for interfacing TILoutputs to 12V SSI DTMF Receivers.ANALOG INPUTThe analog input is the signal input pin for the devices,and is specially biased to facilitate its connection toexternal circuitry, as shown in Figure 3. The signal levelat the analog input pin must not exceed the positivesupply as stated on the device data sheets. If thiscondition cannot be guaranteed by the external circuitry,the signal must be AC coupled into the chip with a .01 fJ.F± 20% capacitor.ANALOG INPUT NOISEThe SSI DTMF Receivers will tolerate wide-band inputnoise of up to 12 dB below the lowest amplitude tonecomponent during detection of a valid tone pair. Anysingle interference frequency (including tone harmonics)between 1 kHz and 6 kHz should be at least 20 dB belowthe lowest amplitude tone component. Adherence tothese conditions will ensure reliable detection and fulltone detection frequency bandwidth. Because of theinternal band limiting, noise with frequencies above 8 kHzcan remain unfiltered. However, noise near the 56 kHzinternal switched-capacitor-filter sampling frequency willbe aliased (folded back) into the audio spectrum; noiseabove 28 kHz therefore should be low-pass filtered witha circuit as shown in Figure 4 using a cut-off frequency(/c) of 6.6 kHz.A 1 kHz cut-off frequency filter can be used on "normal"phone lines for special applications. When a phone lineis particularly noisy, tone pair detection may be unreliable.A 1 kHz low pass filter will remove much of the noiseenergy but maintain the tone groups; however, a decreasedspeech immunity will result. This usage shouldonly be considered for applications where speech immunityis not important, such as control paths that carry nospeech.DTMF Receiver Application Guide 9-74

vpIIIIIIVIN < VP IIII>-IIIIIIVIN > VP IIIII c: 0.01 iJ-F I c:I :!: I :c(.)c f- >-H- , (.)cAnalog in : Q.Q.Analog in IIIIIIIIIIIIIGNDvpGNDrFIGURE 3: Direct and AC Coupled ConfigurationsSome DTMF tone pair generators output distorted toneswhich the SSI DTMF Receivers may not detect reliably(inexpensive extension telephones are an example).Most of the interfering harmonics of these may be removedby the use of a 3 kHz low-pass filter as in Figure 4.Some speech immunity degradation will result. It shouldbe mentioned that when using low-pass filters, a highercut -off frequency will preserve more of the speech immunityadvantages.The SSI DTMF Receivers provide superior speech immunityand noise rejection. The analog signals aresubjected to stringent criteria and rigorous qualification inorder to assure that only true DTMF tone pairs aredetected and decoded properly. Stray signal and noisewith sufficient amplitude will cause a DTMF receiver todisqualify a DTMF tone pair.Such a condition can be occasionally encountered whenusing DTMF "beepers." Beepers are normally used totransmit DTMF signals from dial-pulse phones. It hasbeen obse(ved that the non-linearity in the response ofcarbon microphones in telephone handsets introducesintermodulation products, which actually produce newfrequency components. These components happen tofall direclty into the useful bandwidths of some of thebasic tones that the receiver must detect. Because of thepresence of these components (normally referred to asthird-tone) with a valid DTMF tone, detection is disabled.To inhibit the more common higher frequency third tonesfrom arriving to the receiver, the circuit shown in Figure 5is suggested.TELEPHONE LINE INTERFACEIn applications that use an SSI DTM F Receiverto decodeDTMF signals from a phone line, a DAA (Direct AccessArrangement) must be implemented. Equipment intendedfor connection to the public telephone networkmust comply with and be registered in accordance toFCC Part 68. For PBX applications referto EIA StandardRS-464.Some of the basic guidelines are:1) Maximum voltage and current ratings of theSSI DTMF Receivers must not be exceeded; thiscalls for protection from ringing voltage, if applicable,which ranges from 80 to 120V RMS over a20 to 80 Hz frequency range.2) The interface equipment must not breakdown withhigh-voltage transient tests (including a 2500Vpeak surge) as defined in the applicable document.3) Phone line termination must be less than 2000 DCand approximately 600n AC (200-3200 Hz).4) Termination must be capable of sustaining phoneline lop current (off-hook condition) which is typically18 to 120 mA DC.5) The phone line termination must be electricallybalanced with respect to ground.6) Public phone line termination equipment must beregistered in accordance to FCC Part 68 or connectedthrough registered protection circu itry.Registration typically takes about six months.I•9-75DTMF Receiver Application Guide

NOISYSIGNALIFC R C(kHz) (kQ) (1lF)(=5%) (=20%)ANALOG IN DTMF 1.0 1.6 0.1RCVR3.1 5.1 0.016.6 2.4 0.01SUGGENSTEDCOMPONENT VALUESFIGURE 4: Filter for Use in Noisy EnvironmentsReady made DAA devices are also available. The SSI73M9001 is a DAA Micromodule housed in a 30-pin DIPfootprint.Figure 6 shows a simplified phone line interface using a600n 1:1 line transformer. Transformers specially designedfor phone line coupling are available from manytransformer manufacturers.Figure 7 shows a more enhanced version of Figure 6.These added features include:1) A 150V su rge protector to eliminate high voltagespikes.2) A Texas Instruments TCM 1520A ring detector,optically isolated from the supervisory circuitry.3) Back-to-back Zener diodes to protect the DTM F(and optional multiplexer Op-Amp) from ringervoltage.4) Audio multiplexer which allows voice or otherOUTPUTSaudio to be placed on the line (a recorded message,for example) and not interfere with incomingDTMF tone detection.The digital outputs of the SSI DTMF Receivers (exceptXOUT) swing between VP and VN (or VND) and are fullycompatible with standard CMOS logic devices poweredfrom VP and VN. The 5V DTMF devices wi" alsointerface directly to LSTTL. The 12V DTMF devices caninterface to TTL or low voltage MOS with the circuit inFigure 8.Data Outputs D8, D4, D2 and D1 are three-state enabledto facilitate interface to a three-state bus. Figure 9 showsthe equivalent circuit for the data outputs in the highimpedance state. Care must be taken to prevent eithersubstrate diode in Figure 9 from becoming forward biasedor damage may result.51K0.01 IlFINPUT 0-1 I0.011lF12.9KANALOG INSSIDTMFRCVRVCCFIGURE 5: Filter for Use in Environments where a Third Tone ExistsDTMF Receiver Application Guide 9-76

TIMINGWithin 40 ms of a valid tone pair appearing at the DTMFReceiver Analog Input, the Data Outputs D8, D4, D2 andD1 will become valid. Seven microseconds afterthe dataoutputs have become valid DV will be raised. DV willremain high and the outputs valid while the valid tone pairremains present. Refer to individual data sheets for thetiming of signals.SYSTEM INTERFACEProvision has been made on the SSI DTMF Receivers(with the exception of SSI 75T204) for handshake interfacewith an outside monitoring system. In this mode, theDV strobe is polled by the monitoring system at leastonce every 40 ms to determine whether a new valid tonepair has been detected. If DV is high, the coded data isstored in the monitoring system and the CLRDV is pulsedhigh. With some systems operating in the handshakemode, it may be desirable to know when a valid pausehas occurred. Ordinarily this would be indicated by thefalling edge of DV. However, inthe handshake mode, DVis cleared by the monitoring system each ti me a new validtone pair is detected and, therefore, cannot be used todetermine when a valid pause is detected. The detectionof a valid pause in this case may be observed bydetecting the clearing of the Data Outputs. Since, inhexadecimal format (the mode normally used with ahandshake interface), the all zero state represents acommonly unused tone pair (D), the detection of a validTIP]RING1 :1600n_----l ANALOGINPUTSSI DTMFRECEIVERFIGURE 6: Simplified Phone Line Interfacepause may be detected by connecting a four-input NORgate to the device outputs and sensing the all zero state.TIME BASEThe SSI DTMF Receivers contain an on-chip oscillatorfor a 3.5795 MHz parallel resonant quartz crystal orceramic resonator. The crystal (or resonator) is placedbetween XIN and XOUT in parallel with a 1 Mn resistor,while XEN is tied high. Since the switched-capacitorfiltertime base is derived from the oscillator, the tonedetect band frequency tolerance is proportional to thetime base tolerance. The SSI DTMF Receiverfrequencyresponse and timing is guaranteed with a time baseaccuracy of at least ± 0.01 %. To obtain this accuracy theCTS Part No. MP036 or Workman Part No. CY1-C or22 knTIP o----;----.--------OoIIIIf----____...fi""150VANALOGINPUTSSI DTMFRECEIVERIISOLATED OUTPUTRING 0----1-----*-------------'FIGURE 7: Full Featured Phone Line Interface9-77 DTMF Receiver Application Guide

5VVpvp12 VOLT551DTMFSSI75T201OUTPUT PINFIGURE 8: SSI 12V DTMF to TTL Level Interfaceequivalent quartz crystal is recommended. In less criticalapplications a suitable ceramic resonator may be implemented.The use of a ceramic resonator requires the addition oftw030pF± 1 0% capacitors; one between XIN and VN (orVND) and the other between XOUT and VN (or VND).Extra caution should be used to avoid stray capacitanceon the resonant circuit when using a ceramic resonatorinstead of a quartz crystal.When the oscillator is connected as above and XEN istied high, the ATB (Alternate Time Base) pin delivers asquare wave output at one-eighth the oscillator frequency(447.443 kHz nominal). The ATB pin can beconverted to a time base input by tying XEN low; A TB canthen be externally driven from another device such as theAT'B output of another DTMF. No crystal is required forthe ATB input device; XIN must be tied high if unused.Several SSI DTMF Receivers can be driven with a singlecrystal (refer to device data sheet for fan-out limit).XOUT is designed to drive a resonant circuit only and isnot intended to drive additional devices. If a 3.58 MHzclock is needed for more than one device and it isdesirable to use only one resonant device, an outsideinverter should be used for the time base, buffered by asecond inverter or buffer. The buffer output would thendrive XIN of the SSI DTM F Receiver as well as the otherdevice(s); XOUT must be left floating and XEN tied high.DIAL TONE REJECTIONThe SSI DTMF Receivers incorporate enough dial tonerejection circuitry to provide dial tone tolerance of up too dB. Dial tone tolerance is defined as the total power ofprecise dial tone (350 Hz and 440 Hz as equal amplitudes)relative to the lowest amplitude tone in a valid tonepair. The filter of Figure 10 may be used for further dialtone rejection. This filter exhibits an elliptic highpassFIGURE 9:Equivalent Circuit of SSI DTMF ReceiverData Output in High Impedance Stateresponse that provides a minimum of 18 dB rejection at350 Hz, and 24 dB rejection at 440 Hz so long as thecomponent tolerances indicated are observed. TheDTM F on-chip filter rejects 350 Hz at least 6 dB more than440 Hz. Therefore, employing the filter of Figure 10yields a dial tone tolerance of +24 dB.PRINTED CIRCUIT BOARD IMPLEMENTATIONThe SSI DTMF Receivers are analog in nature andshould be treated as such; circuit noise should be kept toa minimum. To be certain of this, all input and output linesshould be kept away from noise sources (high frequencydata or clock lines); this is especially true for the AnalogInput. Noise in the ground or power supply lines can beavoided by running separate traces to supportive logiccircuits or by running thicker (lower resistance) busses.Capacitance power supply bypassing should be performedat the device. Referto the Power Supply sectionabove.PERFORMANCE DATAA portion of the final SSI DTMF Receiver device characterizationuses the Mitel CM7290 tone receiver test tape.The evaluation circuit shown in Figure 11 was used tocharacterize the SSI 75T201. The speed and outputlevel of the tape deck must be adjusted so that thecalibration tone at the beginning of the tape is at exactly1000 Hz and 2V rms.The Mitel tape tests yield similar results on all of theSSI DTMF Receivers. Test results for the SSI 75T201are summarized in Table 2. In short, the measuredperformance data demonstrates that the SSI DTMFReceivers are monolithic realizations of a full "centraloffice quality" DTMF Receiver.DTMF Receiver Application Guide 9-78

CIRCUIT IMPLEMENTATION(SINGLE SUPPLY)VpVp6000TO SSI DTMFANALOG IN PINNote: All resistors 1%, all caps 5%, unless noted, op-amps: 1/2 LM1458 or equivalentFIGURE 10: Dial Tone Reject Filter+12VH/B286Vp XOUT 14 3.579545 MHzENXINI-'-'-~---'SSI75T2015 IN1633 08 2019 elROV 04210.1 ~F-12ANALOG IN220213 VNA 01V NOOVIFIGURE 11: Circuit for Receiver Evaluation9-79 DTMF Receiver Application Guide

-.~-------.-----~--~-----------.~--------~---~~TEST #RESULTS2a, b B.W. = 5.0% of fo2c, d B.W. = 5.0% of foI--------+-------------------~.----~---~ ....-------~---------2e, f B.W. = 5.3% of fo2g, h B.W. = 4.9% of fo2i, j B.W. = 5.0% of fo2k, I B.W. = 5.3% of fa2m, n B.W. = 5.3% of fo20, P B.W. = 4.8% of fo3 160 decodesAcceptable Amplitude Ratio (Twist) = -19.1 dB to +15.2 dBDynamic Range = 32.5 dBGuard Time = 23.3 ms100% Successful Decodes at N/S Ratio of -12 dBV2-3 Hits Typical on Talk-Off Test-- ._-------_._---- ------~~----~-~TABLE 2: Mitel #CM7290 Tape Test Results for SSI75T201 (Averaged for 10 parts)APPLICATIONSCREATING HEXADECIMAL "0" OUTPUT UPONDIGIT "0" DETECTIONTo be consistent with pulse-dialing systems, theSSI DTMFReceivers provide a hexadecimal "10" output upon thedetection of a digit "0" tone pair when in the hexadecimalcode format. However, some applications may insteadrequire a hexadecimal "0" with a digit "0" detection. Thecircuit of Figure 12 shows an easy method to recode thehexadecimal outputs to do this using only 4 NOR gates.Note that this circuit will not give proper code forthe ,,* ","B", or "C" digits and will cause both digits "D" and "0" tooutput hexadecimal "0." This circuit should therefore beconsidered for numeric digits only. The output codeformat is shown in Table 3.This circuit is useful for applications that require a displayof dialed digits; the digit display usually requires a hexadecimal"0" input for a "0" to be displayed.1~CHANNELREMOTECONTROLDTMF signaling provides a simple, reliable means oftransmitting information over a 2-wire twisted pair. Thecomplete schematic of a 16-channel remote control isshown in Figure 13. When one of the key pad buttons isdepressed, a tone pair is sent over the transmissionmedium to the SSI DTM F Receiver.SSIDTMFRECEIVERDBD4 04D2D1~---------------

HexadecimalHexadecimal & Figure 12 CircuitDigit 08 04 02 01 Digit 08 04 02 011 0 0 0 1 1 0 0 0 12 0 0 1 0 2 0 0 1 03 0 0 1 1 3 0 0 1 14 0 1 0 0 4 0 1 0 05 0 1 0 1 5 0 1 0 16 0 1 1 0 6 0 1 1 07 0 1 1 1 7 0 1 1 18 1 0 0 0 8 1 0 0 09 1 0 0 1 9 1 0 0 10 1 0 1 0 0 0 0 0 0.1 0 1 1.0 0 0 1# 1 1 0 0 # 1 1 0 0A 1 1 0 1 A 1 1 0 1B 1 1 1 0 B 0 1 0 0C 1 1 1 1 C 0 1 0 1D 0 0 0 0 D 0 0 0 0TABLE 3: Output Code of Figure 13VpH!B28VpXOUT3.579545 MHzEN16XENXINSSIOTMFRECEIVERlN16:;.3 0819CLROV0412ANALOG IN 0213VNA 0110pFVNOOV18oCOLIVpCOL224110 SO Vdd9 SI10 S226VOR 9VBATTERY V+ 8 S37MK 5087S4 01S514 16v-1312lK11V--=-S6 02S718 4514 21S8 0317S92022S10 0419SII14ENlS12 STROBE13S131623S1415SIS Vss12202122IFIGURE 13: 16-Channel Remote Control9-81 DTMF Receiver Application Guide

2-0F-8 OUTPUT DECODEThe circuit shown in FiQure 14 can be used to convert thebinary coded 2-of-8 to the actuaI2-of-8 code (or 2-of-7 ifdetection of 1633 Hz tone is iflhibited). The output datawill be valid while DV is high. If it is desired to force theeight outputs to zero when a valid tone is not present, DVshould be inverted and connected to both E-NOT inputsof the 4555.DTMF TO ROTARY DIAL PULSE CONVERTERThe 2-of-8 output of Figure 14 can be modified to interfacewith a pulse dialer as shown in Figure 15. If a 12VDTMF is used the 4049 will translate the 12V outputs tothe 5V swings required for the MK5099 pulse dialer.Figure 16 shows the interface for adding pulse detectionand counting to a SSI DTMF Receiver.The loop detector provides a digital output representingthe telephone loop circuit "make" and "break" conditionassociated with rotary pulse dialing. For the circuit ofFigure 16, ground represents a "make" and VP a "break."The loop detector feeds dial pulses to IC-1, a binarycounter, and to IC-2A, a re-triggerable "one-shot." Whena dial pulse appears the 01-NOT output of IC-2A immediatelygoes low, resetting IC-1. The clock input to IC-1is delayed by R1-C1 so that reset and count input do notoverlap. The binary outputs of IC-1 will reflect the pulsecount and 0.2 seconds after the last pulse the 01-NOToutput will go high. C3-R3 differentiate this pulse andclock the output latch, IC-3, holding the output pulse untilthe next digit.The 0.2 second timeout of IC-2A indicates the end of dialpulsing since even a slow (8 pps) dial would input anotherpulse every 0.125 seconds. The binary outputs of IC-1are paralleled with those of the SSI DTMF Receivercircuit through diodes to the inputs of IC-3. A pulldownresistor is necessary on each IC-3 input pin. IC-1 mustbe a binary, not BCD, counter.With a 4175 for IC-3 the output data is latched until thenext valid input, whether from a rotary dial or dual toneinstrument. A unique situation exists, however, whengoing on-hook. The loop detector will output a continuouslevel of VP which would trigger IC-2A and put a singlecount into IC-1.A high level from the loop detector alsoturns on 01, pulling the clock input of IC-3 to ground.Since the loop detector output will be low at the completionof dialing, all outputs are valid even when thetelephone is placed on-hook, an important considerationif output data is recorded.VpVpXOUT3.579545 MHz316ENXENXIN5510TMFRECEIVERI~~528 004 6975 770519IN 1633CLRDVDBD4202103A 046 8527 941INPUT1213ANALOG IN 02VNA 014 ORVINV NOOV158 0002A 031110120913361477VssFIGURE 14: Touch-Tone to 2-of-8 Output ConverterDTMF Receiver Application Guide 9-82

Vp+5V141312D 3.579545MHz-16H/B28ENXENVPXOUTXIN14 3.579545 MHZ1MDS111U1MK 5087SSI DTMFRECEIVER52IN1633D820COl2COl119ClRDVTONE OUT - - -I1216 ~~~"-'--------+-I TRANSMISSION '------..---=-j ANALOG INMEDIUM 13V1- __NAORVNVNDD4D2D1DV2122-1845564049MK50994 QODIAL PULSES OUTMUTE1812C3C2C11477 5 Q11336 (658)1209 7 Q3Vp 0------1 V+V-R4R3R2R113 941 12 QO1414 852 11 Q11515 no 10 02 (658)16 697 9 Q3 13RC1RC31 MEG270KNOT NEEDED IF A 5 VOLT SSIDTMF RECEIVER IS USEDTHE 4556 MUST THEN BEREWIRED TO COMPENSATEFOR THE MISSING INVERSION.FIGURE 15: Touch-Tone to Rotary Dial Pulse Converter Adding Rotary Dial Pulse Detection CapabilitiesI9-83 DTMF Receiver Application Guide

DATA OUTPUTFROM SSI DTMFA 8 C DIC-1IC-3112-4520 4175aoADO 00018D1 0102CD2 0203DD3 03i.047100KRESETR2 C2Vp~100K .1'DV' FROMSSI DTMF10K+12IC-2A1/2-4538iOIS2 SEC01.047C3100KALL DIODES - SMALL SIGNALSILICON -1N914, 1N4154, ETC.01FIGURE 16: Adding Pulse Detection and Counting to the SSI DTMF ReceiverNo responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights of thirdparties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems reservesthe right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is currentbefore placing orders.Silicon Systems, Inc., 14351 Myford Road, Tustin, GA 92680-7022, (714) 573-6000, FAX: (714) 573-6914DTMF Receiver Application Guide0193 - rev.

GlossaryACK - "Acknowledge" character. A transmission controlcharacter transmitted by a station as an affirmativeresponse to the station with which a connection hasbeen set up. An acknowledge character may also beused as an accuracy control character.ACOUSTIC COUPLER - A type of low-speed modeminterface frequently used with portable terminals. Itsends and receives data using a conventional telephonehandset and does not require an electrical connectionto the line.ADAPTIVE DIFFERENTIAL PULSE CODE MODU·LATION (ADPCM) - An encoding technique, standardizedby the CCITT, that allows an analog voice conversationto be carried within a 32K bps digital channel.Three or four bits are used to describe each sample,which represents the difference between two adjacentsamples. Sampling is done 8,000 times per second.ALGORITHM - A prescribed set of well-defined rules forthe solution of a problem in a finite numberof steps, e.g.,A full statement of an arithmetic procedure for evaluatingsine x to a stated precision.AMPLITUDE - Magnitude or size. In waveforms orsignals occurring in a data transmission, a completedefinition of the waveform can be made if the voltagelevel is known at all times. In this case, the voltage levelis called the amplitude.ANSWERBACK - A reply message from a terminal thatverifies that the correct terminal has been reached andthat it is operational.APPLICATION LAYER- Thetopoftheseven-layerOSImodel, generally regarded as offering an interface to,and largely defined by, the network user; in IBM's SNA,the end-user layer.ASCII- American Standard Code for Information Interchange.A 7 -bit binary code that defines 128 standardcharacters for use in data communications.ASYNCHRONOUS - Occurring without a regular orpredictable time relationship to a specified event, e.g.,The transmission of characters one at a time as they arekeyed. Contrast with synchronous.ASYNCHRONOUS TRANSMISSION - Transmissionin which each information character, or sometimes eachword or small block, is individually synchronized, usuallyby the use of start and stop elements. Also calledstart-stop or character asynchronous transmission.ATTENUATION - A decrease in the power of a current,voltage, or power of a received signal in transmissionbetween points because of loss through lines, equipmentor other transmission devices. Usually measuredin decibels.AUI - Attachment unit interface. The electrical interfacebetween the traditional line electronics (transceiver)and the DTE components (ENDEC & MAC).AMPLITUDE MODULATION - Method of modifying theamplitude of a sine wave signal in order to encodeinformation.ANALOG LOOPBACK - A technique used for testingtransmission equipment that isolates faults to the analogsignal receiving or transmitting circuitry. Basically,where a device, such as a modem, echoes back areceived (test) signal that is then compared with theoriginal signal.ANALOG SIGNAL - Signal in the form of a continuouslyvarying physical quantity such as voltage, which reflectsvariations in some quantity.ANSI- American National Standards Institute. A highlyactive group affiliated with the International StandardsOrganization (ISO) that prepares and establishes standardsfor transmission codes (e.g., ASCII), protocols(e.g., ADCCP), media (tape and diskette), and highlevel languages (e .g., Fortran and Cobol), among otherthings.0194 - rev. 9-85AUTO-ANSWER - Automatic answering; the capabilityof a terminal, modem, computer, or a similar device torespond to an incoming call on a dial-up telephone line,and to establish a data connection with a remote devicewithout operator intervention.AUTOBAUD - The generally used term for automaticallydetecting the bit rate of a start/stop (characterasynchronous) communication format by measuringthe length of the start bit of the first character transmitted.Some modems extend this to additionally determinethe parity in use by stipulating that the first twocharacters from the DTE should be "AT." The wordautobaud comes from a popular misuse of baud rate tomean the same as bit rate.AUTODIAL - Automatic dialing; the capability of aterminal, modem, computer, or a similar device to placea call over the switched telephone network, and establisha connection without operator intervention.I

AUTOMATIC DIALER, OR AUTODIALER - Devicewhich allows the user to dial preprogrammed numberssimply by pushing a single button.BANDPASS FILTER - A circuit designed to allow aSingle band of frequencies to pass; neither of the cut-offfrequencies can be zero or infinite.BANDWIDTH - 1) The range· of frequencies that canpass over a given circuit. The bandwidth dete rmines therate at which information can be transmitted through thecircuit. The greater the bandwidth, the more informationthat can be sent through the circuit in a given amount oftime. 2) Difference, expressed in hertz (Hz), betweenthe highest and lowest frequencies of a transmissionchannel.10Base-T - Ethernet on unshielded twisted pair.10Base-2 - Ethernet on thin coax.10Base-5 - Ethernet on thick coax.BASEBAND - Pertaining or referring to a signal in itsoriginal form and not changed by modulation. Abaseband signal can be analog or digital.BASEBAND SIGNALING - Transmission of adigital oranalog Signal at its original frequencies, i.e., a signal inits original form, not changed by modulation; can be ananalog or digital signal.B'AUD - A measure of data rate, often misused todenote bits per second. A baud is equal to the numberof discrete conditions or signal events per second.There is disagreement over the appropriate use of thisword, since at speeds above 2400 bitls, the baud ratedoes not always equal the data rate in bits per second.BELLCORE - Bell Communications Research; organizationestablished by the AT&T divestiture, representingand funded by the BOCs and RBOCs, for thepurposes of establishing telephone network standardsand interfaces; includes much of former Bell Labs.BERT - Bit Error Rate Test. A test conducted bytransmitting a known, pattern of bits (commonly 63,511, or 2047 bits in tength), comparing the patternreceived with the pattern transmitted, and counting thenumber of bits received in error. Also see bit error rate.Contrast with BLERT.BINARY CODE - Representation of quantities expressedin the base-2 number system.BINARY SYNCHRONOUS COMMUNICATIONS - Ahalf-duplex, character-oriented data communicationsprotocol originated by IBM in 1964. It includes controlcharacters and procedures for controlling the establishmentof a valid connection and the transfer of data. Alsocalled bisync and BSC. Although still enjoying widespreadusage, it is being replaced by IBM's moreefficient protOCOl, SDLC.BIPOLAR - 1) The predominant signaling method usedfor digital transmission services, such as DDS and T1 ,in which the signal carrying the binary value successfullyalternates between positive and negative polarities.Zero and one values are represented by the Signalamplitude at either polarity, while no-value "spaces" areat zero amplitude. 2) A type of integrated circuit (IC orsemiconductor) that uses NPN, PNP, and junctionFET's as the primary active devices, as opposed toCMOS, which uses MOS FET's. See Alternate MarkInversion.BISON - Broadband integrated services digital network.BIT - The smallest unit of information used in dataprocessing. It is a contraction of the words "binary digit."BIT ERROR RATE (BER) - In data communicationstesting, the ratio between the total number of bitstransmitted in a given message and the number of bitsin that message received in error; a measure of thequality of a data transmission.BITS PER SECOND (BIT/S) - Basic unit of measure forserial data transmission capacity; Kbit/s, or kilobits, forthousands of bits per second; Mbit/s, or megabit/s, formillions of bits per second, etc.BOC - Bell Operating Company. One of 22 local telephonecompanies spun off from AT&T as a result ofdivestiture. The 22 operating companies are dividedinto seven regions and are held by seven RBHCs(Regional Bell Holding Company).BROADBAND - Referring or pertaining to an analogcircuit that provides more bandwidth than a voice gradetelephone line, i.e., a circuit that operates at a frequencyof 20 kHz or greater. Broadband channels are used forhigh-speed voice and data communications, radio andtelevision broadcasting, some local area data networks,and many other services. Also called wideband.BUFFER - A storage medium or device used for holdingone or more blocks of data to compensate for.a differencein rate of data flow, ortime of occurrence of events,when transmitting data from one device to another.9-86 0194 - rev.

BUS - 1) Physical transmission path or channel. Typicallyan electrical connection, with one or more conductors,wherein all attached devices receive all transmissionsat the same time. Local network topo logy, such asused in Ethernet and the token bus, where all networknodes listen to all transmissions, selecting certain onesbased on address identification. Involves some type ofcontention-control mechanism for accessing the bustransmission medium. In data communications, a networktopology in which stations are arranged along alinear medium (e.g., a length of cable). 2) In computerarchitecture, a path over which information travelsinternally among various components of a system.BYTE-Groupofbits handled as a logical unit; usually 8.CABLE - Assembly of one or more conductors within aprotective sheath; constructed to allow the use of conductorsseparately or in groups.CALL PROGRESS DETECTION (CPO) - A techniquefor monitoring the connection status during initiation ofa telephone call by detecting presence and/or dutycycle of call progress signaling tones such as dial-toneor busy signals commonly used in the telephone network.CALL PROGRESS TONES - Audible signals returnedto the station user by the switching equipment to indicatethe status of a call; dial tones and busy signals arecommon examples.CAP MODEM - Carrierless amplitude phase modem.CCITT - Co mite Consultatif International de Telephonieet de Telegraphie. Telegraph and Telephone ConsultiveCommittee. An advisory committee to the InternationalTelecommunications Union (ITU) whose recommendationscovering telephony and telegraphy haveinternational influence among telecommunications engineers,manufacturers, and administrators.CDPD - Cellular digital packet data 19.2 Kbitls wirelessmodem.CENTRAL OFFICE (CO) - See ExchangeCHANNEL BANK - Equipment typically used in atelephone central office that performs multiplexing oflower speed, digital channels into a higher speed compositechannel. The channel bank also detects andtransmits signaling information for each channel, andtransmits framing information so that time slots allocatedto each channel can be identified by the receiver.CHANNEL SERVICE UNIT (CSU) - A component ofcustomer premises equipment (CPE) used to terminatea digital circuit, such as DDS or T1 at the customer site;performs certain line-conditioning functions, ensuresnetwork compliance per FCC rules and responds toloopback commands from central office; also, ensuresproper ones density in transmitted bit stream and performsbipolar violation correction.CHANNEL, VOICE GRADE - Channel suitable fortransmission of speech, analog data, or facsimile, generallywith a frequency range of about 300 to 3000 Hz.CHARACTER - Letter, figure, number, punctuation, orother symbol contained in the message. In data communication,common characters are defined by 7- or 8-bit binary codes, such as ASCII.CHIP - A commonly used term which refers to anintegrated ciruit.CIRCUIT, TWO-WIRE-Acircuitformedbytwoconductorsinsulated from each othe r that can be used as eithera one-way or two-way transmission path.CLOCK - In logiC or transmission, repetitive, preciselytimed signal used to control a synchronous process.CMOS - Complementary Metal-Oxide Semiconductor.A type of transistor, typicailly used in low-power integratedcircuits.COAXIAL CABLE - Cable conSisting of an outerconductor surrounding an inner conductor, with a layerof insulating material in between. Such cable can carrya much higher bandwidth than a wire pair.CPE - Customer Premises EquipmentCROSSPOINT - 1) Switching array element in anexchange that can be mechanical or electronic. 2) Twostatesemiconductor switching device having a lowtransmission system impedance in one state and a veryhigh one in the other.CROSSTALK - Interference or an unwanted signalfrom one transmission circuit detected on another,usually an adjacent circuit.CYCLIC REDUNDANCY CHECK (CRC) - A powerfulerror detection technique. Using a polynomial, a seriesof two 8-bit block check characters are generated thatrepresent the entire block of data. The block checkcharacters are incorporated into the transmission frame,then checked at the receiving end.I0194 - rev. 9-87

IIDATA COMMUNICATIONS EQUIPMENT (DCE) -Equipment that performs the functions required to connectdata terminal equipment (DTE) to the data circuit.In a communications link, equipment that is either partof the network, an access-point to the network, anetwork node, or equipment at which a network circuitterminates; in the case of an RS-232C connection, themodem is usually regarded as DCE, while the userdevice is DTE, or data terminal equipment; in a CCITTX.2S connection, the network access and packetswitchingnode is viewed as the DCE.DATA LINK - Any serial data communications transmissionpath, generally between two adjacent nodes ordevices and without any intermediate switching nodes.DATA SET - A synonym for modem used by AT&T anda few other vendors.DATA SERVICE UNIT (DSU) - A device that replacesa modem on a Digital Data Service (DDS) line. The dataservice unit regenerates the digital signals fortransmissionover digital facilities.DATA TERMINAL EQUIPMENT (DTE) - Equipmentwhich is attached to a network to send or receive data,generally end-user devices, such as terminals andcomputers, that connect to DCE, which either generateor receive the data carried by the network; in RS-232Cconnections, designation as either DTE or DCE determinessignaling role in handshaking; in a CCITT X.25i~erface, the device or equipment that manages theinterface at the user premises; see DCE.dB - Decibel; unit for measuring relative strength of asignal parameter such as power, voltage, etc. Thenumber of decibels is twenty times the logarithm (base10) of the ratio of the power of two signals, or ratio of thepower of one signal to a reference level.dBm - Decibels relative to one milliwatt.DDS - 1) Digital Data Service. A digital transmissionservice supporting speeds upto 56 KbiVs. 2) DataphoneDigital Service. An AT&T leased line service offeringdigital transmission at speeds ranging from 2400 to56 Kbitls.DECT - Digital European cordless telephone.DJCT - Digital Japanese cordless telephone.DIAL-UP - The process of, or the equipment or facilitiesinvolved in, establishing a temporary connection via theswitched telephone network.DIAL TONE (DT) - Signal sent to an operator or subscriberindicating that the switch is ready to receive dialpulses.DIGITAL - Referring to communications procedures,techniques, and equipment whereby information is encodedas either binary "1" or "0"; the representation ofinformation in discrete binary form, discontinuous intime, as opposed to the analog representation of informationin variable, but continuous, waveforms.DIGITAL LOOPBACK - A technique for testing thedigital processing circuitry of a communications device.It may be initiated locally, or remotely via a telecommunicationscircuit. The device being tested will echo backa received test message, after first decoding and thenre-encoding it, the results of which are compared withthe original message.DIGITAL SIGNAL - Discrete or discontinuous signal;one whose various states are discrete intervals apart.DIP - Dual-In-Line Package. Method of packaging electroniccomponentsfor mounting on printed circuit boards.DISTORTION - The modification of the waveform orshape of a signal caused by outside interference or byimperfections of the transmission system. Mostforms ofdistortion are the result of the characteristics of thetransmission system to the different frequency components.DOTTING, DOUBLE DOTTING, PATTERN - The term"dotting" was coined by Bell to describe a data patternconsisting of alternate marks and spaces. The CCITTuses the full description of "alternating binary ones andzeros" on first needing this idea in a recommendation,but then abbreviate this to "reversals." By extrapolation,"double dotting" has come into use to refer to the datapattern termed "S1"which is used in V.22bis to indicate2400 biVs capability. The full description is "unscrambleddouble dibit 00 and 11 at 1200 bitls for 100 ± 3 ms."DS-1 - Digital Signal level 1 ; telephony term describinga digital transmission format in which 24 voice channelsare multiplexed into one 1.544 Mbit/s (U.S.) T1 digitalchannel.08-3 - Digital Signal level 3; telephony term describingthe 44.736 Mbitls digital signal carried on a T3 facility.DSP RTOS - Digital signal processing real time ope rat­ing system.DELAY DISTORTION - The change in a signal from thetransmitting end to the receiving end resulting from thetendency of some frequency components within achannel to take longer to be propagated than others.9-88 0194 - rev.

DTMF - Dualtone Multifrequency (DTMF) - Basis foroperation of most push button telephone sets. An inbandsignalling technique in which a matrix combinationof two frequencies, each from a group of four, are usedto transmit numerical address information; it encodes16 possible combinations of tone pairs using two groupsof four tones each. The two groups of four frequenciesare 697 Hz, 770 Hz, 852 Hz, and 941 Hz, and 1209 Hz,1336 Hz, 1477 Hz, and 1633 Hz. DTMF is used primaryfor call initiation in GSTN telephone applications.IIECHO - The distortion created when a transmittedsignal is reflected back to the originating station.ECHO CANCELLER - A devise used to reduce oreliminate echo. It operates by placing a signal that isequal and opposite to the echo signal on the returntransmission path.ECHO SUPPRESSOR - A mechanism used to suppressechoes on long-distance analog connections.The device suppresses the transmission path oppositein directiontothe one being used. Thisfeature, althoughnecessary for voice transmission, often interferes withdata transmission.EIA - Electronic Industries AssociationEIA INTERFACE, EIA232D, RS 232C - The logical,electrical and physical characteristics of the connectionbetween a DTE and a modem is set out in EIA specification232D. Previously this has been known as RS232C.The logical characteristics are essentially similar tothose specified in CCITT recommendation V .24 and theelectrical characteristics to those in V.28.ELECTROMAGNETIC INTERFERENCE (EMI) -Radiation leakage outside a transmission medium thatresults mainly from the use of high-frequency waveenergy and signal modulation. EMI can be reduced byappropriate shielding.EMI - See Electromagnetic Interference.ENDEC - Encoder/Decoder. The 10 Mbitls Manchesterencoder and decoder circuit for Ethernet signalling.ENVELOPE DELAY - An analog line impairmentipvolving a variation of signal delay with frequencyacross the data channel bandwidth.EQUALIZATION - The introduction of components toan analog circuit by a modem to compensate for theattenuation (signal loss) variation and delay distortionwith frequency (attenuation equalization) and propagationtime variations with frequency (delay equalization).Generally, the higher the transmission rate, the greaterthe need for equalization.ERROR - In data communications, any unwantedchange in the original contents of a transmission.ERROR BURST - A concentration of errors within ashort period of time as compared with the averageincidence of errors. Retransmission is the normal correctionprocedure in the event of an error burst.ERROR CONTROL - A process of handling errors,which includes the detection and in some cases, thecorrection of errors.ETHERNET - A media-access specification for localarea networks, developed by IEEE and known as theIEEE 802.3 spec.EXCHANGE - Assembly of equipment in a communicationssystem that controls the connection of incomingand outgoing lines, and includes the necessary signalingand supervisory functions. Different exchanges, orswitches, can be costed to perform different functions,e.g., Local exchange, trunk exchange, etc. See Class ofExchange. Also known as Central Office (U.S. Term).EXCHANGE, PRIVATE AUTOMATIC BRANCH(PABX) - Private automatic telephone exchange thatprovides for the switching of calls internally and to andfrom the public telephone network.EXCHANGE, PRIVATE BRANCH (PBX) - Private,manually operated telephone exchange that providesprivate telephone service to an organization and thatallows calls to be transmitted to or from the publictelephone network.EXCHANGE AREA - Area containing subscribersserved by a local exchange.IIFILTER - Circuit designed to transmit signals of frequencieswithin one or more frequency bands and toattenuate signals of other frequencies.FIRMWARE - Permanent or semi-permanent controlcoding implemented at a micro-instruction level for anapplication program, instruction set, operating routine,or similar user-oriented function.FLOW CONTROL - The use of buffering and othermechanisms, such as controls that turn a device on andoff, to prevent data loss during transmission.I0194 - rev. 9-89

FOUR-WIRE CIRCUIT OR CHANNEL - A circuit containingtwo pairs of wire (or their logical equivalent) forsimultaneous (Le., full-duplex) two-way transmission.Contrast with two-wire channel.FRAME - 1) A group of bits sent serially over a communicationschannel; generally a logical transmission unitsent between data-link-layer entities that contain itsown control information for addressing and error checking.2) A piece of equipment in a common carrier officewhere physical cross connections are made betweencircuits.FRAMING - Control procedure used with multiplexeddigital channels such as T1 carriers, whereby bits areinserted so the receiver can identify the time slotsallocated to each subchannel. Framing bits can alsocarry alarm signals indicating specific alarm conditions.FREQUENCY - Rate at which an event occurs, measuredin hertz, kilohertz, megahertz, etc.FREQUENCY BANDS - Frequency bands are definedarbitrarily as follows:Range (MHz)0.03-0.30.3-3.03-3030-300300-30003000-30,00030,000-300,000NameLow frequency (LF)Medium frequency (MF)High frequency (HF)Very High frequency (VHF)Ultra high frequency (UHF)Super high frequency (SHF) (microwave)Extremely high frequency(EH F) (millimeterwave)FSK - Frequency Shift Keying. A method of modulationthat uses two different frequencies, usually phasecontinous, to distinguish between a mark (digital 1 ) anda space (digital 0) when transmitting on an analog line.Used in modems operating at 1200 bit/s or slower.FULL-DUPLEX - Pertaining to the capability to sendand receive simultaneously.GAIN - Denotes an increase in signal power in transmissionfrom one point to another, usually expressed in dB.prevent the high-band data signal from interfering withthe operation of billing apparatus in certain countries.GSTN - General Switched Telephone NetworkHALF-DUPLEX - Pertaining to the capability to sendand receive but not simultaneously.HANDSHAKE - An eXChange of control sequencesbetween two locations to set up the correct parametersfor transmission.HDLC - High-level Data Link Control. Bit-oriented communicationprotocol developed by the ISO (InternationalStandards Organization).HARMONIC DISTORTION - A waveform distortion,usually caused by the nonlinear frequency response ofa transmission.HERTZ (Hz) - A measure of electromagnetic frequency;one hertz is equal to one cycle per second.HF - High Frequency.HIGH FREQUENCY (HF) - Portion of the electromagneticspectrum, typically used in short-wave radio applications.Frequencies in the 3 to 30 MHz range.aHz - See Hertz.IEEE -Institute of Electrical and Electronics Engineers.IEEE 802.11 - Wireless local area network IEEE standard.INITIALIZE - To set counters, switches, addresses, orcontents of storage to zero orother starting values at thebeginning of, or at prescribed points in, the operation ofa computer routine.INTERFACE - A hardware and/or software link betweentwo devices. The interface defines all signal characteristicsand other specifications for physical interconnectionof the devices.GUARD TONE -In CCITT recommendations V.22 andV.22bis, guard tones may optionally be transmittedalong with the data signal from the answering modem.A single frequency of either 1800 or 550 Hz is used andthe data signal power must be reduced to keep theoverall energy level the same as for transmission withoutguard tone. The purpose of the guard tone is toINTEROFFICE TRUNK - Direct trunk between localcentral offices (Class 5 offices), or between Class 2, 3,or 4 offices; also called intertoll trunk.1854 - Interim standard 54 - half analog/digital, secondgenerationNorth American standard.9-90 0194 - rev.

ISO - International Organization for Standardization.ITU - International Telecommunications Union. Theparent organization of the CCIIT.IIJITIER - Slight movement of a transmission signal intime or phase that can introduce errors and loss ofsynchronization for high-speed synchronous communications.See Phase jitter.LIMITED-DISTANCE MODEM - A short-haul modemor line driver that operates over a limited distance.Some limited-distance modems operate at higherspeeds than modems that are designed for use overanalog telephone facilities, since line conditions can bebetter controlled.LINE HIT - A transient disturbance causing a detectableerror on a communications line.LINE-LOADING - The process of installing loading coilsin series with each conductor on a transmission line.Usually 88 milliHenry coils installed at 6,000 foot intervals.KEY PULSING (KP) - Manual method of sendingnumerical and other signals by the operation ofnonlocking pushkeys. Also called Key Sending.KEY SERVICE UNIT (KSU) - Main operating unit of akey telephone system.KEY TELEPHONE SYSTEM (KTS) - When more thanone telephone line per set is required, pushbutton or keytelephone systems offer flexibility and a wide variety ofuses, e.g., pickup of several exchange lines, PABXstation lines, private lines, and intercommunicatinglines. Features of the system include pickup and holdingintercommunications, visual and audible signals,cutoff, exclusion, and signaling.KP - Key Pulse (signaling unlocking signal). See KeyPulsing...kHz - Kilohertz, kilocycles per second.KTU - Key Telephone Unit. See Key Service Unit.LEASED LINE - A line rented exclusively to one customerfor voice or data communications; dedicatedcircuit, typically supplied by the telephone company ortransmission authority, that permanently connects twoor more user locations and is for the sole use of thesubscriber. Such circuits are generally voice grade incapacity and in range of frequencies supported, aretypically analog, are usedforvoiceordata, can be pointto-point,or multipoint, and can be enhanced with lineconditioning. Also called private line, tie line, or dedicatedfacility.LED - Light-Emitting Diode.LIGHT-EMITTING DIODE (LED) - Semiconductor junctiondiode that emits radiant energy and is used as alight source for fiber optic communications, particularlyfor short-haul links.0194 - rev. 9-91LINK - 1) A physical circuit between two points. 2) Alogical circuit between two users of a packet switched(or other) network permitting them to communicate(although different physical paths may be used).LINK LAYER - The logical entity in the OSI modelconcerned with transmission of data between adjacentnetwork nodes. It is the second layer processing in theOSI model, between the physical and the networklayers.LOADING COILS - An inductance coil installed atregular intervals along a transmiSSion line. Used toimprove the quality of voice grade circuits.LOCAL EXCHANGE - Exchange in which subscribers'lines terminate. The exchange has access to otherexchanges and to national trunk networks. Also calledlocal central office, end office.LOCAL LOOP - The part of a communications circuitbetween the subscriber's equipment and the equipmentin the local exchange .LOCAL TRUNK - Trunks between local exchanges.LOSS (TRANSMISSION) - Decrease in energy of signalpower in transmission along a circuit due to theresistance or impedance of the circuit or equipment.IIMAC - Media access controller - a protocol controller ICthat implements the 802.3 CSMAICO protocol.MARK - The signal (communications channel state)corresponding to a binary one. The marking conditionexists when current flows (current-loop channel) orwhen the voltage is more negative than -3 volts (EIARS-232 Channel).I

MATRIX - In switch technology, that portion of theswitch architecture where input leads and output leadsmeet, any pair of which may be connected to establisha through circuit. Also called switching matrix.MAU - Media attachment unit - a transceiver thatconnects to the AUI port on an Ethernet interface card.Mbit/s - Megabits per second.MEGAHERTZ (MHz) - A unit of frequency equal to onemillion cycles per second.mNAK - "Negative acknowledge" character. A transmissioncontrol character that indicates a block of data wasreceived incorrectly.NOISE - Undesirable energy in a communications path,which interferes with the reception or processing of asignal.ns - Nanosecond; also nsec. One-billionth of a second.MF - 1) Medium Frequency. 2) Multifrequency. SeeDualtone Multifrequency Signaling (DTMF).MODEM - A contraction of modulate and demodulate;a conversion device installed in pairs at each end of ananalog communications line. The modem at the transmittingend modulates digital signals received locallyfrom a computerorterminal;the modem at the receivingend demodulates the incoming signal, converting itback to its original (Le., digital) format, and passes it tothe destination business machine.MODULATION - The application of information onto acarrier signal by varying one or more of the signal'sbasic characteristics (frequency, amplitude, or phase);the conversion of a signal from its original (e.g., digital)format to analog format.MODULATION, PULSE CODE (PCM) - Digital transmissiontechnique that involves sampling of an analoginformation signal at regular time intervals and codingthe measured amplitude value into a series of binaryvafues, which are transmitted by modulation of a pulsed,or intermittent, carrier. A common method of speechdigitizing using a-bit code words, or samples, and asampling rate of a kHz.ms - Millisecond. One-thousandth of a second.MULTIPLEXER - Device that enables more than onesignal to be sent simultaneously over one physicalchannel.MULTIPLEXING - Division of a transmission facility intotwo or more channels either by splitting the frequencyband transmitted by the channel into narrower bands,each of which is used to constitute a distinct channel(frequency-division multiplex), or by allotting this commonchannel to several different information channels,one at a time (time-division multiplexing).MUX - See Multiplexer.OFF HOOK - By analogy with the normal householdtelephone, a modem is off-hook when it is using thetelephone line to make a call. This is similar to raisingthe telephone handset, or taking it off the hook. Goingoff-hook is also known as "seizing the line."ON-HOOK - By analogy with the normal householdtelephone, a modem is on-hoOk when it is not using thetelephone line. As with a telephone where the handsetis on the hook, the line may be used by other equipmentto make a call. Going on-hook is also known as "droppingthe line."OSI - Open Systems Interconnection. Referring to thereference model, OSI is a logical structure for networkoperations standardized within the ISO; a seven-layernetwork architecture being used for the definition ofnetwork protocol standards to enable any OSI-compatiblecomputer or device to communicate with any otherOSI-compliant computer or device for a meaningfulexchange of information.OVERFLOW - Excess traffic on a particular route,which is offered to another (alternate) route.PABX - Private Automatic Branch Exchange. SeeExchange, Private Automatic Branch (PABX).PACKET - A group of binary digits including data andcall control signals that is switched as a compositewhole. The data, call control signals, and error controlinformation are arranged in a specified format.PBX - Private Branch Exchange. See Exchange,Private Branch.PCMCIA - Personal Computer Memory Card InternationalAssociation. Type 1: 3.3 mm thickType 2: 5.0 mm thick9-92 0194 - rev.

PHASE JITTER - In telephony, the measurement, indegrees out of phase, that an analog signal deviatesfrom the referenced phase of the main data-carryingsignal. Often caused by alternating current componentsin a telecommunications network; or: a random distortionof signal lengths caused by the rapid fluctuation ofthe frequency of the transmitted signal. Phase jitterinterferes with interpretation of information by changingthe timing.PHASE MODULATION - One of three ways of modifyinga sine wave signal to make it carry information. Thesine wave or "carrier" has its phase changed in accordancewith the information to be transmitted.PROPAGATION DELAY - The period between the timewhen a signal is placed on a circuit and when it isrecognized and acknowledged at the other end. Propagationdelay is of great importance in satellite channelsbecause of the great distances involved.PROTOCOL - A set of procedures for establishing andcontrolling communications. Examples include BSC,SDLC, X.25, V.42, V.42bis, MNP, V.22bis handshake,etc.PSK - Phase Shift Keying. A method of modulation thatuses the differences in phase angle between two symbolsto encode information. A reference oscillator determinesthe phase angle change of the incoming signal,which in turn determines which bit or dibit is beingtransmitted. DPSK (Differential Phase Shift Keying) is avariation of PSK which changes the phase relative tothe previous phase.REPEATER - 1 ) I n analog transmission, equipment thatreceives a pulse train, amplifies it and retimes it forretransmission. 2) In digital transmission, equipmentthat receives a pulse train, reconstructs it, retimes it,and often then amplifies the signal for retransmission.3) In fiber optics, a device that decodes a low-powerlight signal, converts it to electrical energy, and thenretransmits it via an LED or laser-generating light source.See also Regenerative Repeater.REVERSE CHANNEL - A simultaneous low speed datapath in the reverse direction over a half-duplex facility.Normally, it is used for positive/negativeacknowledgements of previously received data blocks.RINGER EQUIVALENCE NUMBER - This is a numberthat the FCC assigns to approved telecom equipmentthat measures how much load it places on the networkduring ringing. In the U.S.A., you can connect telephones,modems, FAX machines etc. In parallel to thesame telephone line only as long as the sum of theirringer equivalence numbers is less than five. Mostcountries have a similar regulating system in force,although the methods used to arrive at the numbervarywidely.RINGING SIGNAL - Any AC or DC signal transmittedover a line or trunk for the purpose of alerting a party atthe distant end of an incoming call. The signal canoperate a visual or sound-producing device.RINGING TONE - Tone received by the calling telephoneindicating that the called telephone is being rung.Also called Ringback.PULSE CODE MODULATION (PCM) - A method oftransmitting information by varying the characteristicsof a sequence of pulses, in terms of amplitude, duration,phase, or number. Used to convert an analog signal intoa digital bit stream for transmission.mREGENERATIVE REPEATER -1) Repeater utilized intelegraph applications to retime and retransmit thereceived signal impulses and restore them to theiroriginal strength. These repeaters are speed- and codesensitiveand are intended for use with standard telegraphspeeds and codes. 2) Repeater used in PCM ordigital circuits which detects, retimes, and reconstructsthe bits transmitted.REGENERATOR - Equ ipment that takes a digital signalthat has been distorted by transmission and producesfrom it a new signal in which the shape, timing, andamplitude of the pulses are that same as those of theoriginal before distortion.0194 - rev. 9-93RSSI- Receive signal strength indicator (i.e., go to gaincontrol in AM signal).SCRAMBLER/DESCRAMBLER - A scrambler functionuses a defined method for modifying a data stream,in order to make the altered data stream appear random.A descrambler reverses the effect of the scramblerusing the previously defined method to recover theoriginal data stream. Most often used for data encryption,or to avoid transmitting repetitive data patters thatcan adversely affect data recovery in modems andother data transmission equipment.SDLC - Synchronous Data Link Control. IBM bit orientedprotocol providing for half-duplex transmission;associated with IBM's System Network Architecture(SNA).SHIELDED PAIR - Two insulated wires in a cablewrapped with metallic braid or foil to prevent interferenceand provide noise-free transmission.I

SIGNAL· TO·NOISE RATIO - The relative power of asignal as compared to the power of noise on a line. Asthe ratio decreases, it becomes more difficult to distinguishbetween information and interference.SIMPLEX - Pertaining to the capability to move in onedirection only. Contrast with half-duplex and full-duplex.SIGNALING - Process by which a caller or equipmenton the transmitting end of a line informs a particularparty or equipment at the receiving end that a messageis to be communicated.SMART IF - Microcontroller bus interface for programcontrol of RF components.SONET - Synchronous optical network.SPACE - OppOSite signal condition to a "mark." Thesignal (communications channnel state) correspondingto a binary zero. In an EIA RS-232 channel, the spacingcondition exists when the voltage is more positive than+3 volts.SS - Spread spectrum.ST - Start (signal to indicate end of outpulsing).STS1 - 51.84 Mbitls.START·STOP (SIGNALING) - Signaling in which eachgroup of code elements corresponding to a character ispreceded by a start signal that serves to prepare thereceiving mechanism for the reception and registrationof character, and is followed by a stop signal that servesto-6ring the receiving mechanism to rest in preparationfor the reception of the next character. Also known asasynchronous transmission.TCVCXO - Temperature-compensated, voltage - con-trolled crystal oscillator.STOP·BIT - In asynchronous transmission, the quiescentstate following the transmission of a character;usually 1-, or 2-bit times long.STOP ELEMENT - Last bit of a character in asynchronousserial transmission, used to ensure recognition ofthe next start element.SUBSCRIBER LINE - Telephone line connecting theexchange to the subscriber's station. Also called(U.S. term) access line and subscriber loop.SW56 - Switched 56 Kbit/s digital transmission.SYNCHRONOUS - Having a constant time intervalbetween successive bits, characters, or eventS. Synchronoustransmission doesn't use non-information bits(such as the start and stop bits in asynchronous transmission)to identify the beginning and end orcharacters,and thus is faster and more efficient than asynchronoustransmission. The timing is achieved by transmittingsync characters prior to data or by extracting timinginformation from the carrier or reference.SYNCHRONOUS NETWORK - Network in which allthe communications links are synchronized to a commonclock.SYNCHRONOUS TRANSMISSION - Transmissionprocess where the information and control charactersare sent at regular, clocked intervals so that the sendingand receiving terminals are operating continuously instep with each other.IIT-CARRIER - A time-division multiplexed, digital transmissionfacility, operating at an aggregate data rate of1.544 Mbitls and above. T-carrier is a peM systemusing 64 Kbitls for a voice channel.T1 - A digital facility used to transmit a DS-1 formatteddigital signal at 1.544 Mbit/s; the equivalent of 24 voicechannels.T1 CIT2IT3/T4 - Digital carrier facilities used to transmitsignals at 3.152M, 6.312M, 44.736M, 274.176 Mbitls,respectively.T3 - A digital carrier facility used to transmit a DS-3formatted digital carrier signal at 44.736 Mbitls; theequivalent of 672 voice channels.TACS - Total access communications system. (U.K.analog cellular standard).TDMA - Time division multiple access.TOUCH-TONE - An AT&T trademark fordualtone multifrequencysignaling equipment. Use of tones Simplifiesthe switching system deSign and greatly expandsthe potential for adding features to telephone systems.It also speeds up the dialing operation for a personmaking a call.TRANSCEIVER - Device that can transmit and receivetraffic.TRUNK - Transmission paths that are used to interconnectexchanges in the main telephone network, twoswitching centers, or a switching center and a distributionpoint, such as a telephone exchange line thatterminates in a PABX network.9-94 0194 - rev.

TTL - Transistor-Transistor Logic. Digital logic familyhaving common electrical characteristics.TURNAROUND TIME - The time required to reversethe direction of transmission, e.g; to change from receivemode to transmit mode in order to acknowledgeon a half-duplex line. When individual blocks are acknowledged,as is required in certain protocols (e.g.,IBM BSC) the turnaround time has a major effect onthroughput, particularly if the propagation delay islengthy, such as on a satellite channel.TWO-WIRE CIRCUIT - Circuit formed of two conductorsinsulated from each other, providing a send andreturn path. Signals may pass in one or both directions.VIDEOTEX - An interactive data communications applicationdesigned to allow unsophisticated users to conversewith remote databases, enter data for transactions,and retrieve textual and graphics information fordisplay on subscriber television sets or low-cost terminals.VSLI - Very Large Scale Integration.V SERIES RECOMMENDATIONS­(CCITT V.xx Standards)Also see Voiceband Modem Standards chart onpage 9-12.V.1 - Definitions of key terms for binary symbol notation,such as binary 0 = space, binary 1 = mark.V.2 (1) - Specification of power levels for data transmissionover telephone line.V.4 - Definition of the order of bit transmission, the useof a parity bit, and the use of start/stop bits for asynchronoustransmission.V.S - Specification of data-signaling rates (bit/s) forsynchronous transmission in the switched telephonenetwork.V.6 - Specification of data signaling rates (bit/s) forsynchronous transmission on leased telephone circuits.V.7 - Definitions of other key terms used in the V-seriesrecommendations.V.10 - Description of an unbalanced physical levelinterchange circuit (unbalanced means one active wirebetween transmitter and receiver with ground providingthe return).V.11 - Description of a balanced physical level interchangecircuit (balanced means two wires between thetransmitter and receiver with both wires' signals constantwith respect to Earth).V.1S - Description of use of acoustic couplers for datatransmission.V .16 - Description of the transmission of ECG (electrocardiogram)signals on the telephone channel.V.19 - Description of one-way parallel transmissionmodems using push-button telephone sets.V.20 - Description of one-way parallel transmissionmodems, excluding push-button telephone sets.V.22 - Operating at 1.2 Kbitls, encodes two consecutivebit (dibits); the dibits are encoded as a change relativeto the previous signal element.V.22bis - Operating at 2.4 Kbitls, encodes four consecutivebits (quadbits); the first two bits are encodedrelative to the quadrant of the previous signal element,the last two bits are associated with the point in newquadrant.V.24 - Definition of the interchange circuit pins betweenDTEs (data terminal equipment) and DCEs (data circuit-terminatingequipment).V.2S - (2) - Specifications for automatic-answeringequipment.V.2Sbis - (2) - Specifications for automatic-answeringequipment.V.28 - Description of unbalanced interchange circuitsoperating below 20 Kbit/s.V.29 - Operating at9.6 Kbitls, encodes four consecutivebits (quadbits); the first bit determines the amplitude,the last three bits use the encoding scheme of V.27.V.29 - Operating at 4.8 Kbit/s, encodes two consecutivebits (dibits); amplitude is constant and phase changesare the same as V.26.V.31 - Description of low-speed interchange circuits (upto 75 Bit/s).V.31bis - Description of low-speed interchange circuits(up to 1.2 Kbitls).V.32 - Operating at9.6 Kbit/s, encodesfourconsecutivebits (quadbits); the bits are mapped to a QAM signal.I0194 - rev. 9-95

V.32 - Operating at 9.6 KbiVs with Trellis-coded modulation(TeM), encodes four consecutive bits, two ofwhich are used to generate a fifth bit; the bits aremapped to a QAM signal.V.32 - Operating at 4.8 Kbitls, encodes two consecutivebits (dibits), which are mapped to a QAM signal.V.42 - Defines a method of error control.V.42bls - Defines a method of data compression.Note: In the United States, EIA RS-496 specifies thesemeasurements and RS-366 specifies these procedures.VOICE-GRADE CHANNEL - a channel with a frequencyrange from 300 to 3000 Hz and suitable for thetransmission of speech, data, or facsimile.WORD - A group of bits handled as a logical unit;usually 16.9-96 0194 - rev.

Voiceband Modem StandardsCCITTStandardDataRate(Bitts)Full-orHalf­DuplexChannelSeparationCarrierFrequency(Hz)ModulationMethodModulationRate(Baud)Bits Synchronous Back GSTNEncoded or ChannelAsynchronousLeasedLinesEqualizationScramblerV.21300FullFrequencyDivision1080, & 1750FrequencyShift3001:1 Either ND YesNoNDNOV.221200FullFrequencyDivision1200, & 2400PhaseShift6002:1 Either ND YesPoint-to-Point2-WireFixedYesV.22V.22bisV.23V.236002400600(1)1200 (1)FullFullHalfHalfFrequencyDivisionFrequencyDivisionN1AN/A1200, &24001200, & 24001300, & 17001300, &2100PhaseShiftQuadrature­AmplitudeModulationFrequencyModulationFrequencyModulation60060060012001:1 Either ND Yes4:1 Either ND YesN/A Either Yes YesN/A Either Yes YesPoint-ta-Point2-WirePoint-to-Point2-WireNoNoFixedFixed/AdaptiveNDNDYesYesNDNDV.2S2400Full4-Wire1800PhaseShift12002:1 Synchronous Yes NoPoint-to-PointMuHipoint4-WlreNDNDV.26bisV.26blsV.26terV.26terV.2724001200240012004800HalfHalfEitherEitherEitherN/AN1AEchoCancellationEchoCancellationND (3)18001800180018001800PhaseShiftPhaseShiftPhaseShiftPhaseShiftPhaseShift120012001200120016002:1 Synchronous Yes Yes1:1 Synchronous Yes Yes2:1 Either ND Yes1:1 Either ND Yes3:1 Synchronous Yes NoNoNoPoint·to·Point2-WirePoinl-to-Point2-WireYes (3)FixedFixedEitherEitherManualNDNDYesYesYesV.27blsV.27bisV.27terV.27terV.2948002400480024009600EitherEitherHalfHalfEither4-Wire(4)4-Wire(4)NoneNone~ 4-Wire18001800180018001700PhaseShiftPhaseShiftPhaseShiftPhaseShiftQuadrature·AmplitudeModulation160012001800120024003:1 Synchronous Yes No2:1 Synchronous Yes No3:1 Synchronous Yes Yes2:1 Synchronous Yes Yes4:1 Synchronous No No2-Wire,4-Wire2-Wire,4-WireNoNoPolnt·ta-Point4-WireAdaptiveAdaptiveAdaptiveAdaptiveAdaptiveYesYesYesYesYesV.297200Either4-Wire1700PhaseShift (5)24003:1 Synchronous ND NoPoint·to·Point4-WireAdaptiveYesV.29V.3248009600EitherFull4-WireEchoCancellation17001800PhaseShift (5)Quadrature­AmplitudeModulation240024002:1 Synchronous ND No4:1 Synchronous ND YesPoint-ta-Point4-WirePoint·to·Point2-WireAdaptiveAdaptiveYesYesV.32blsV.32144009600FullFullEchoCancellationEchoCancellation18001800Trellis­CodedModulationQuadrature­AmplitudeModulation240024006:1 Synchronous ND Yes4:1 Synchronous ND YesPoint·to·Point2-WirePoint-to-Point2-WireAdaptiveAdaptiveYesYesV.324800FullEchoCancellation1800auadrature­AmplitudeModulation24002:1 Synchronous ND YesPoint-ta-Point2-WireAdaptiveYesV.33V.341440028600HalfFullEchoCancellation1800Trellis­CodedModulation2400Synchronous ND Yes12:1 Synchronous ND YesPoint-ta-Point2-WireAdaptiveNDYesYesBell (U.S.) Standard103 300201 2400202 1200208 4800212 1200FullHalfHalfHalfFullFrequencyDiviSionNoneNoneNoneFrequencyDivision2225&1270(m)2025 &1070(6)18001200 & 220018001200 & 2400FrequencyShiftPhaseShiftFSKQuadrature·AmplitudeModulationPhaseShift1. BiVs not used in specification; rate stated in baud. Low speed 75 biVs back channel forasymetric full·duplex3001200120016006001:1 Either No Yes2:1 Synchronous No Yes1:1 Either Yes Yes3:1 Synchronous No Yes2:1 Either No Yes4. For half-duplex, 2-wire usedNoPoint·to·Point2-WirePoint·la-Point2-WlrePoint-to· Point2-WireNoFilledAdaptiveAdaptiveFixedNoYesNoYesYesI2. Half·duplex may still use a backward channel5. Amplitude is constant on a relative basis3. Makes no mention of 4-wire (must be assumed) ND = Not defined (i.e., not specified in the recommendation)9-97

Notes:9-98

Section 10PACKAGING/ORDERINGINFORMATIONI10

Silicon SystemsPackaging IndexDUAL-IN-LiNE PACKAGE (DIP)PlasticCeramicSURFACE MOUNTED DEVICES (SMD)Quad (PLCC)Quad Flatpack (QFP)Thin Quad Flatpack (TQFP)Very Thin Quad Flatpack (VTQFP)Ultra Thin Quad Flatpack (UTQFP)Small Outline (SOIC)Package Width (mil) Pitch (mil)SON 150SOL 300SOW 400SOM 300 0.8PINSPAGE NO.8,14,16 & 18 10-420, 22, 24 & 24S 10-528,32 & 40 10-68,14,16& 18 10-722,24 & 28 10-820,28 10-932 &44 10-10~ ----52 & 68 10-11-----------52 & 100 10-12128 10-1332 & 48 10-14----64,80 & 100 10-15120 & 128 10-16~---.-----144 10-17------_ ..32,48 & 64 10-18100 10-19--_ ... _.-120 10-20--64 & 100 10-218,14& 16S0N 10-2216,18,20,24 & 28 SOL 10-2334 SOL 10-24---32 SOW 10-2436S0M 10-2444S0M 10-25Very Small Outline Package (VSOP)Very Thin Small Outline Package (VTSOP)Ultra Thin Small Outline Package (UTSOP)------~ ...20 & 24 10-25--16 & 20 10-2624 &36 10-2710-0

~~ Small form factor Package Selector GuideQuad Flatpack PackagesPACKAGE TYPE52 G (QFP)1 ()() G (QFP)128 G (QFP)32 GT (TQFP)48 GT (TQFP)ACTUAL SIZE(AREA)oDD••BODY SIZE LAYOUT AREA mm 2 ACTUAL SIZE THI

~~ Small Form Factor Package Selector GuideQuad Flatpack PackagesPACKAGE TYPEACTUAL SIZE(AREA)BODY SIZE LAYOUT AREA mm 2 ACTUAL SIZE THlacNESS(PITCH) mm (THICKNESS) mm120 GT (TQFP)128 GT (TQFP)DD14.0 x 14.0 (0.4) 16.0 x 16.0 = 256 1.420.0 x 14.0 (0.5) 22.0 x 16.0 = 352 1.4144 GT (TQFP)D20.0 x 20.0 (0.5) 22.0 x 22.0 = 484 1.448 GV (VTQFP)7.0 x 7.0 (0.5) 9.0 x 9.0 = 81 1.064 GV (VTQFP)10.0 x 10.0 (0.5) 12.0 x 12.0 = 144 1.0100 GV (VTQFP)14.0 x 14.0 (0.5) 16.0 x 16.0 = 256 1.0120 GV (VTQFP)14.0 x 14.0 (0.4) 16.0 x 16.0 = 256 1.064 GU (UTQFP)10.0 x 10.0 (0.5) 12.0 x 12.0 = 144 0.710-2

~~. Small form factor Package Selector GuideSmall Outline PackagesPACKAGE TYPE AOUAL SIZE BODY SIZE LAYOUT AREA mm 2 AOUAL SIZE THICKNESS(AREA) (PITCH) mm (THICKNESS) mm16S0N 9.8 x 3.9(1.27) 9.8 x 6.0 = 58.8Iii -1.65--16 SOL 10.2 x 7.5 (1.27) 10.2 x 10.2 = 104 2.5420 SOL 12.8 x 7.5 (1.27) 12.8 x 10.2 = 130.6 2.5424 SOL..15.4 x 7.5 (1.27) 15.4 x 10.2 = 157 2.54-20 SOY (VSOP) 7.2 x 5.4 (0.65) 7.9 x 7.2 = 56.9 1.924 SOY (VSOP) 7.8 x 5.6 (0.65) 7.8 x 7.6 = 59.28II -1.1536 SOM (SSOP) 15.1 x 7.5 (0.8) 15.1 x 10.2 = 154 2.5444 SOM (SSOP) 18.3 x 7.5 (0.8) 18.3 x 10.2 = 186.7 2.5416 VT (VTSOP) 5.0 x 4.4 (0.65) 6.4 x 5.0 = 32-0.920 VT (VTSOP) 6.5 x 4.4 (0.65) 6.5 x 6.4 = 41 .6 0.9D = Actual Body Size = Full layout Aroo All dimensions are nominal values.I10-3

Package InformationPlastic DIP0.400 (10.160)0.350 (9.980)0,770 (19.558)0.745 (18.923)0.050(1.270)0.020 (0.508)0.215 (5.461)~vmI0.145 (3.680) ,0.150 (3.810) t0.125 (3.175)r- 0.100 TYP. (2.540)J ~0.Q15 (0.381)0.023 (0.584)8-Pin Plastic0.310 (7.874)0.285 (7.239)14-Pin Plastic0,070 (1,778)0.015 (0,381)_t-t0.770 (19.558)0,745 (18.923)16-Pin Plastic::I]!VVnf\RN Tr- 0.100~~0.015(0.381)~TVP. (2.540)0,930 (Zl.622)0.860 (22.352)18-Pin Plastic10-4

Package InformationP'NNO.1-OD~58)*IDENT. 0.265 0.240 (6.731)096)-L1.040 (26.416)1.010 (25.654)* 1.195 (30.353)1.175 (29.845) --- I~:~:!;.~~~)~mv~ * ~:~~~!6~~:~* 0.135 (3:429) 0.015 (0.381)••. ,~ •. "'1 •. ,~ • .,.,0.120(3.048) 0.125(3:175) _ _ _ -r~~0.015 (0.381)0.023 (0.584)~0.100TYP.(2.540) - - -~ rr=r===:-+---20 Pin Plastic*24S Pin Plastic1.100 (27.940)1.080 (27.432:::---) - ... -..1:±;VVnRlVVnRr TTYP. (2.540) --~~r-.. 1000.015 (0.381)0.023 (0 584)22-Pin Plastic=,~ : : : : : : : : : : ]f~1.290 (32.766)1.200(30.480)::J;mRMRRRRN T ~r-0.100TYP.(2.540) -~r~)0.015(0.381)10-524-Pin PlasticI

Package Information~~,--t : : : : : : : : : : : : ]fL.- 1.450(36.830)1.380(35.052)::;tmfV\Ml\RRR_RRRt T ~~0.100TYP.(2.540) - -~~0.015(0.381)0.023(0.584)--..0.610(15.494) 0-15'\28-Pin Plastic:: Tlmrrm ~ i t ~ i 32·Pin Plastic1.625 (41.275)~25(3.17~i=nnnr ~ l~~--.I LO.l00TYP (2540 0.610(15.494) 0-15'_I 1- . . ) i-. 0.585(14.859) I0.015 (0.381) ....0.023 (0.584),~o,-D)::::::::: ]ft- 2.070 (52.578)2.020(51.308)::];m mfW\RRt Tilt ~~~0.015 (0.381)~)--l L - - l 0.610(15494) 0-15'_I 1- 0.100 TYP. (2.540) L-. ~9) ...... Ii40-Pin Plastic10-6

Package InformationCerdip-D I5)0.290 (7.366)---I-PIN NO. 1 1IDE NT.0.3320.260o.no (19.558)0.690 (17.526)°MOf ~ 0.175(4.445)-'-.~ n v~ v ~j .'"'"~'''':'-1 r- ~ ~-1 r- ::~:::;;~'"0.332 (8.433)0.280 (7.1 12)0.325 (8.255)~0.038 (0.965) 0.125 (3.175)MIN 0.030(2.413)14-Pin Cerdip0.332 (8.433)0.280 (7.112)0.830 (21.082)0.770 (19.558)0.325 (8.255)0.290 (7.366)--~nm00nRt_G~::::::t0020I 0175 (4 445), 0105 (2 667)--- t---0100TYP-1 r--, r- -1 r-0.030 (0.965) 0.125 (3.175)MIN 0.030 (2.413)16-Pin Cerdip0.332MAX0.930 (23.622) MAXI ~~i I~18-Pin CerdipI0.060 0.0210.038 0:01510-7

Package InformationPINNO.l---Or=-=-IIDENT. .~0.432 (10.973)MAX1.120 (28.448) MAX 0.420 (10.668)MAX:~'~2~T~::~m~--I_~_·~_~~_:~_~:~:O.l00TYP. (2.540)-1 I--IIII0.175 (4.445)~0.060 (1.524) 0.023 (0.584) 0-15'_0.038 (0.965) 0.015 (0.381)0.023 (0.584) ---r-0.015 (0.381)lI II II Il22-Pin Cerdip0.632 (16.053)MAX1.220(30.998) MAX 24-Pin Cerdipo.o.~)J.-~gtl 0.190(4.826)0.070(1.778) 1 0.085(2.159)0.020 (0.508) T/ 0.175(4.445)~ I I II II 0.125(3.175)0.625 (15.875)MAXI I1 J R1 10.023 (0.584~-+0.015 (0.381)O.I00TVP. 0.060(1.524) 0.023(0.584) ()'15'_(2.540) 0.038 (0.965) 0.015 (0.381)I~:,---f:::::::::::: ]0.632(16.053)MAX1.430 (36.322) MAX0.190 (4.826) -I- '~g'190(4'826)0.085 (2.159)~T0.175 (4.445)I I II II 0.125(3.175)0.100 TYP. 0.060 (1.524) 0.023 (0.584)(2.540) 0.038 (0.965) 0.015 (0.381)0-15' -tI0.625(15.875)MAXI I1 J :iJI0.023 (0.584)~-4-0.015(0.361)28-Pin Cerdip10-8

Package InformationQuad (PLCC)0.395 (10.033)1-4-___ 0.385 (9.779)•0.354 (8.992) I14---0.350 (8.89) ~J----.-----r---------------~O.042 (1.067)0.056 (1.422)PIN NO.,IDENTJO'..,.-50-r-(8..,.-.8--r9)--r--.-.,.......,.--.-~0.395 (10:033) 0.354 (8.992)r9) 03ffi j0.050 TYP (1.27)14--- 0.290 (7.366) ~0.320 (8.128)20-Pin Quad PLCC0.495 (12.573)0.485 (12.319)0.495 (12.573) ______ ....... 10.485 (12.319)0.456 (11.650)0.450 (11.430)T~~~:;:~~::~~~~I\U~ u LJ~LI0.020 (0.50B)0.075 (1.905)0.065 (1.651) J~ t----J I ~ 0.ojO(1.270) ~ 0.045 (1.140)0.016(0.406) 0.020 (0.50B)0.390 (9.906)0.430 (10.922)I28-Pin Quad PLCC10-9

Package Information.023.029 J32-Pin Quad PLCC0.075(1.905)J0.065(1.651)44-Pin Qua d PLCC10-10

Packag e I nformation.785 (19.939).795 (20.193).075 (1.905)n~ .065(1.651) I'""Ou ~~ ,."'«"') \ 'r.050TYP(1.j~0)L -..016 (00406) .045 (1.140).020 (0.508) .020 (0.508).690 (17.272).730 (18.542).750 (19.050).756 (19.202)52-Pin Quad PLCC.985 (25.019).995 (25.273)~.075 (1.905)065(1.651) --:.'65'

Package InformationQuad Flatpack (QFP)=l ~9082(~0~06~)U ~u213(0084) ,~,,~ \~ 0 H , I C1Li I015(0006) ~I I I 070(0028)030(0012) ~ j4-- 090(0035). 1377(0542) I.. 14 03 (0 552) •52-Lead Quad FlatpackNOTE: Controlling dimensions are in mm19'62(O'772) ~~~~~~~~~~1----- ~!:~~ ~~~~:~ ----~1+------- ::::: ~~:~~~~ -------1,1100-Lead Quad FlatpackNOTE: Controlling dimensions are in mm10-12

Package Information9'90(0'783)20.10 (0.791) ~~I'~lWWUUUUUUUUUU) lI23.~(0923)-- It--------- :~::~::~ -------+1Form Length = 1.6 mm128-Lead Quad FlatpackNOTE: Controlling dimensions are in mmI10-13

Package InformationThin Quad Flatpack (TQFP)8.7 (0.343)9.3 (0.366)--r-----+--- 241732-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mm(')'"8.7 (0.343)9.3 (0.366)48-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mmLfe.o(o)~ ::~ :~::~: 0.20 (0.008)0.60 (0.024) Typ.10-14

Package Informationmnml13.75(0.541)14.25 (0.561)F~!±:!±~=:!::=!::~=='='=11.7(0.460)12.3 (0.484)PIN No.1 Indicator1.40 ;0.055) f1.60 (0.063)PIN No.1 Indicator11.80 (0.465) sa12.20 (0.480)54-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mm0.15( 0.0059)0.25 (0.0098)0.50TYP.(0.20)1.40 (0.055)1.60 (0.063)SO-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mm1--------- ~::~ ~~~~: --------i100-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mm1--_____ ~13=;:~.~~~~~~~~~O~-----------iI1.40 (0.055)1.60 (0.063)0.00(0)o.ro •. OO·'1PIN No. 1 Indicator10-15

Package Information15.7(0.618)16.3 (0.641)120-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mmPIN No.1 IndicalDr~~b=rf=====L=~0.18 (0.007) 0.40 TYP.(0.016) 1.40 (0.055) 0.20 (0.008)0.27 (0.01 1) 1.60 (0.063)I~UUUUUUUU;lI """~, 22.3(0.878)I0.50(0.0197)TYP1-------- 15.7(0.618)16.3(0.642)128-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mm10-16

Package InformationPIN No.1 Indicator21.80 (0.858) ------------122.20 (0.874)21.80 (0.658)22.20 (0.874),. 19.90 (0.764) 1.35 (0.053)20.10 (0.791) 1.45 (0.057)-i ·"~·""'I0.45 (0.016) 0.17 (0.007) 0.50 (0.020) TYP. 0.15 (0.006)0.75 (0.030) 0.27 (0.011)144-Lead Thin Quad FlatpackNOTE: Controlling dimensions are in mmI10-17

Package InformationVery Thin Quad Flatpack (VTQFP)8.7 (0.343)9.3 (0.366)Pin 11 Identification~ _______ 6.~~~~~~ ______ ~~32-Lead VTQFPNOTE: Controlling dimensions are in mm48·Lead VTQFPNOTE: Controlling dimensions are in mm54-Lead VTQFPNOTE: Controlling dimensions are in mmPin _1 ldenUcalion~ _____________ 9;~(~.~8:~~~ ____________ ---..,~10-18

Package Information~ _______________ ~15~.7~(~0.6_1~8) ________________ ~·116.3 (0.641)~~~~~~A~~~15.7 (0.618)16.3 (0.641)PIN NO.1 Indicator13.8 (0.543) SO14.2 (0.559)1.00 (0.039)1.20 (0.047)f.- 0.60 (0.024) TYP.--j r- I0.18 (0.007)0.27 (0.011)100-Lead VTQFPNOTE: Controlling dimensions are in mmI10-19

Package Information\4---------- 15.7 (0.618) _________ --116.3 (0.641)15.7 (0.618)16.3 (0.641)PIN No.1 IndicatorI_ 13.80 (0.543) SO _I14.20 (0.559)1.00 (0.039)1 .20 (0.047)L0.00 (0)0.20 (0.008)120-Lead VTQFPNOTE: Controlling dimensions are in mm10-20

Package InformationUltra Thin Quad Flatpack (UTQFP)64-Lead Ultra Thin Quad FlatpackNOTE: Controlling dimensions are in mmPin_1ldentification14------- 9.8(0.386)50 ______ _+115.7 (0.618)1--------- 16.3(0.641) --------0;15.7 (0.618)16.3(0.641)100-Lead Ultra Thin Quad FlatpackNOTE: Controlling dimensions are in mmPIN NO.1 IndicatorI10-21

Package Information-1 r-.050TYP.(1.270)+.160 (4.064)---.150 (3.810)+Small Outline (SON)8-Lead SON.200 (5.080).185 (4.699).245 (6.223).230 (5.842).010 (0.254).070(1.778) r~ 1.003 (0.076).060(1.524) L QJ=LHJJJl~.016 nom (0.40) -.j f.- rIc-d\----'.185 (4.699).170 (4.318)\Ifh=-1 I-- O.050TYP. (1.270)~D0.160 (4.064)0.150 (3.810)PINNO.l--.. ~BEVEL0.350 (8.890)0.330 (8.382)0.010 (0.254)0.070(1.778)'~ I 0.003(0.076)0.060(1.524)~ ~-.J j.- 0.016 nom (o:;-f-.j I-- .050TYP. (1.270)0.245 (6.223)0.230 (5.842)14-Lead SON16-Lead SON.400 (10.160).380 (9.652).010 (0.254).070(1.778) t~ \.003(0.076).060 (1.524) ~ -L-.J j.- .016 nom (0.40) 1fi::d,1c..:.:.--.245 (6.223).230 (5.842).185 (4.699).170 (4.318)\I~10-22

Package InformationSmall Outline (SOL)I-1 r-.050TVP. (1.270):r:-.285 (7.239)PINNO.1~ ~BEVEL I U U I .415 (10.S41) U U Ir- .395 (10.033)--,.010 (0.254).110 (2.794) '~ I .003(0.076}.092 (2.336) L --L~ 1---.01 6 nom (0.40) r16-Lead SOL--1 r-.050TYP.I(1.270)-,-.305 (7.747).285 (7.239):~'-F::;,~:;~~.010 (0.254).110 (2.790) t~ 1·003 (0.076}.092 (2.336) L-. ~-.J j.-.016nOm(0.40} f20-Lead SOL(!-.J I=-.420 (10.668).390 (9.906).335 (8.509).320 (8.128).420 (10.668).390 (9.906).335 (8.509).320 (8.128)\I~-1 r-.050TYP. (1.270)I:J::.285 (7.239)PIN N01 -L:;:;:::;::;:::;:rn::::;:;:::;::;:::;::::;::;::;=n:J~BEVEL FJ----.465 (11.S11).445 (11.303)r:===========~ .010 (0.254).110 (2.794) t L===:J I .003 (0.076).092 (2.336) L-. \l.H~-..L~ j.-.016nOm(0.40} f18-Lead SOL-1 r- .050 TYP. (1.270)~,,1n I~~ .285 (7.239)~~V~~1_. ~F L.~15(15'621}U U U UI595(15.113} ~.010 (0.254).110 (2.790) t Qbjib:t£6J±iifiiiEJi] I .003 (0.07S).092 (2.336) ~ -L.... 1 f.-.016nom(0.40) f24-Lead SOL-1 r-.050TYP.(1.270)~~,-~::::::::::::: :~~F~UUUUU'.695(17.653) ~.010 (0.254).110 (2.790) ,- I .OO3(0.076}.092 (2.336) ~ ~-.J \.-.016 nom (040)f28-Lead SOLI10-23

Package InformationSmall Outline (SOL/SOM/SOW)--.j r-0.040TYP. (1.02)34-Lead SOL0.335 (8.52)0.320 (8.14)--.j r-0.050TYP. (1.270)~~~,_J: :: :: : :: : : : : : )~I U U U U U U 0.820 (20.828) U U U U U U Ir--0.795(20.193)~32-Lead SOW::~:~::::::C .~~~-..j f.- 0.016 nom (0.40) f0.010 (0.254)0.003 (0.076):: :::::::~~,-c l~E :~}=lEI EI EI EI EI EI EI 0.612 (15.54)! EI EI EI EI EI EI ElI------'--r--0.584(14.846)~0.110(2.790) C 0.115(0.29)- I 10.003 (0.076)0.092 (2.336) ~j LO.030 (O.7S) TYP. j LO.0315 (o.SOlTYP.j LO.O~TYP.36-Lead SOM(Fine Pitch)10-24

Package Information~~~~~~~~-,- tr---- 0.700(17.78)~0.305 (7.747) 0.420 (10.668)0.285 (7.239) 0.390 (9.906)::,:p' -----I ~ ~ ~ ~ ~ ~ ~ '''''''',,: ~ ~ ~ ~ ~ ~ ~ I~ i0.0875 (2.223) ,-~M'"""'~ 0.0115 (0.29),.,~ ."'l L J1I1l1J111J1J1!LJIIJ1f1J1Mn-FlLf'ro,. "'1~1_(1._~) ______ ~44-Lead SOM(Fine Pitch)j LO.030(0.75)TYP. j LO.0315 (0.80) Typj lO.12.0.20Package InformationNOTE: Controlling dimensions are in mmVSOPL 0.77 (0.030)I ~ 0.53 (0.021)5.35!211)5.25 (0.207)F,7.25 (0.285) ----l.~1, 7.15(0.281)2.05(0.0811+= I8.1 (0.319)7.7 (0.303)II~~~~.1 ~l:r::;::r::r=;::;::::;::;::::;:::;::::;:::;:::::;::;:::;::;:::::;::;::::;:::;:J---I.+ - b[!/l[=====R)1.80(0.071)L~~-..1 f.- 0.35 (0.014) 10.25 (0.010) 0 (0)\W20-Lead VSOP0.20 (0.008)NOTE: Controlling dimensions are in mm-1 r- 0.65;~026)7.8 (0.307)7.4(0.291)F7.9(0.311)~c )U ~II: : : : : : : : : : :11 +--l L 0.75(0.03)~I I~ 0.45 (0.02)1.45(0.057) +-- .-7.7 (0.303)0.20 (0.008)I~1.05(0.041) L ~-..l f.- 0.28(0.011) 10.18 (0.007)24-Lead VSOPI10-25

Package InformationVTSOPNOTE: Controlling dimensions are in mm~~16.10 (0.240)6.70 (0.264)PINNO.1_. 1 1~BEVEL I U U I 4.90 (0.193, U U I1 I5 ,0 . (0.20"0.00UOMaxC0.65 BSC~II ~~ 0.17 (0.007) I(0)-.t.::20 (0.008)0.30 (O.012)T4.50 (0.176)4.30 (0.169)0.75 (0.029)0.50 (0.20)16-Lead VTSOPNOTE: Controlling dimensions are in mmI~4.50 (0.176)4.30 (0.169)0.65 BSC0.17 (0.007)0.00 (0)-.t::20 (0.008)f0.75 (0.029)0.50 (0.20)20-Lead VTSOP10-26

Package InformationUTSOP(;:::::::: :JIIF6.20(0.244)U U U U I6.60 (0.259) ~0.00 (0)0.70 (0.027) r I 0.20 (0.008)0.90 (0.035) L ~.050 Typ. --i ~ 0.22 Typ. -. ~ 1 1_(0.0197) ~ I I - (0.009) I I I0.60 Typ.(0.024)4.20 (0.165)4.60 (0.181)24-Lead UTSOP;: ::](I EJ EJ EJ EJ EJ EJ EJ 9.20 (0.362) I EJ EJ EJ EJ EJ EJ EJ Ir-9 .60 (0.378) ~0.70(0.027) m - 0.00(0)0.90 (0.035)C~0.50 Typ. (0.0197) j L 0.22 Typ. (0.009) j L '- cin I 10.20 (0.008)t6.10 (0.240)6.70 (0.264)~36-Lead UTSOP;-------4.20 (0.165) I4.60 (0.181)~( )~--l I---- 0.60 Typ.(0.024)I10-27

SHIPPING OPTIONSRTape and ReelPIN COUNT OPTIONlor 2 digits?I\)CD32C32032F32H32M32P32R33C33P33R34B34P34R36C66F67F73073K73M75T78A78P78079INPRODUCT CATEGORYHOD ControllerHOD Data RecoveryElectronic FilterHOD Head Positioni!19HOD ,v,olor Speed ControllerHOD Pulse DetectionHOD Read/Write AmpOptical ControllerOptical Pulse DetectionOptical PreampFDD InterfaceFDD Pulse DetectionFDD Read/Write AmpMisc. Non-HDD ControllerStandard Automotive ProductsStandard Aulomotive ProductsModem Device SetK -Series ,v,odemModem/Modem SupportTone SignallingAnaloq TelecomDigitarT elecomLAN ProductsWireless ProductsMODIFIERSCommunication Productsl low PowerSl low Power SerialU UARTStorage ProductsR Damping ResislorM Mirror ImageRI Resislor, Inverted ImageRM Resislor, Mirror ImageT 100 V IV Read Mode Gain (R/W)U ISO V IV Read ,v,ode Gain (R/W)V 200 V IV Read Mode Gain (R/W)W 2S0 V IV Read Mode Gain (R/W)X 300 V IV Read Mode Gain (R/W)y 3S0 V IV Read Mode Gain (R/W)Z 400 V IV Read Mode Gain (R/W)Cannot use A-E in left positionModifiers are listed in hierarchical order.C Commercial (0 °C 10 +70 0C)I Industrial (-40°C 10 +8S 0C)J Burn-In (168 Hours)K Burn-In (48 Hours)Modifiers are listed inhierarchical order.CFGGTGUGVHPTSNlWMVVTPACKAGE TYPESide-Brazed CeramicFlatpackQFP, Quad Flatpack (2.S mm height)TQFP, Thin Quad Flatpack (1.4 mm height)Ultra Thin Quad Flatpack (0.7 mm height)Very Thin Quad Flatpack (I.O mm height)PlCCPlastic DipMetal CanPlastic, Skinny DipSmall Ou~ine, Narrow (ISO mil.)Small O~ine, large (300 mil.)Small Ou~ine, Wide (400 mil.)Small Ou~ine, (300 mil.), Fine Pitch (0.8 mm)Very Small Ou~ine (220 mil.) Fine Pitch (O.65 mm)Very Thin Small Outline (I.O mm height)~cn(1) 0.= _.~. n::l 0

Section 11·SALES OFFICES11I

United StatesRegional Offices & Sales RepresentativesNORTHWESTHEADQUARTERSSilicon Systems, Inc.2001 Gateway Pl., Ste. 301 EastSan Jose, CA 95110Ph: (408) 432-7100FAX: (408) 432-7111CALIFORNIAMagna SalesSanta ClaraPh: (408) 727-8753FAX: (408) 727-8573IDAHOWestern Technical SalesBoisePh: (208) 376-8700FAX: (208) 376-8706MINNESOTAOHMS Technology. Inc.MinneapolisPh: (612) 932-2920FAX: (612) 932-2918OREGONWestern Technical SalesBeavertonPh: (503) 644-8860FAX: (503) 644-8200WASHINGTONWestern Technical SalesBellevuePh: (206) 641-3900FAX: (206) 641-5829SpokanePh: (509) 922-7600FAX: (509) 922-7603SOUTHWESTHEADQUARTERSSilicon Systems, Inc.1860 Lefthand Cr., Suite ALongmont, CO 80501Ph: (303) 678-8003FAX: (303) 678-7920Tustin Sales OfficePh: (714) 573-6630FAX: (714) 832-5247Texas Sales OfficePh: (214) 479-9170FAX: (214) 479-9172ARIZONAWestern High Tech Marketing, Inc.ScottsdalePh: (602) 860-2702FAX: (602) 860-2712CALIFORNIAHadden AssociatesSan DiegoPh: (619) 565-9444FAX: (619) 565-1802SCCubedWestlake VillagePh: (818) 865-6222FAX: (818) 865-6223TustinPh: (714) 731-9206FAX: (714) 731-7801COLORADOLange SalesLittletonPh: (303) 795-3600FAX: (303) 795-0373Colorado SpringsPh: (719) 632-8340FAX: (719) 632-8419IOWACahill, Schmitz & HoweCedar RapidsPh: (319) 377-8219FAX: (319) 377-0958KANSASrush & west associates, Inc.OlathePh: (913) 764-2700FAX: (913) 764-0096MISSOURIrush & west associates, inc.St. LouisPh: (314) 965-3322FAX: (314) 965-3529MONTANALange SalesBoise,lDPh: (208) 323-0713FAX: (208) 323-0834NEW MEXICOWestern High Tech Marketing, Inc.AlbuquerquePh: (505) 884-2256FAX: (505) 884-2258TEXASOM Associates, Inc.AustinPhl (512) 794-9971FAX: (512) 794-9987RichardsonPh: (214) 690-6746FAX: (214) 690-8721HoustonPh: (713) 789-4426FAX: (713) 789-4825UTAHLange SalesSalt Lake CityPh: (801) 487-0843FAX: (801) 484-5408EASTERNHEADQUARTERSSilicon Systems, Inc.2646 S.W. Mapp Rd., Ste. 203Palm City, FL 34990Ph: (407) 223-1143FAX: (407) 223-8085Georgia Sales OfficePh: (404) 409-8405FAX: (404) 368-1060New Hampshire Sales OfficePh: (603) 898-1444FAX: (603) 898-9538ALABAMAElcomHuntsvillePh: (205) 830-4001FAX: (205) 830-4058CONNECTICUTOrion GroupSouthingtonPh: (203) 621-8371FAX: (203) 628-0494FLORIDAProfessional Sales Assoc.Delray Beach(Melbourne/Miami/Ft. Lauderdale)Ph: (407) 498-2029FAX: (407) 499-7987Seminole(OrlandofTampalSt. Petersburg)Ph: (813) 393-5423FAX: (813) 393-5423GEORGIAElcomNorcrossPh: (404) 447-8200FAX: (404) 447-8340ILLINOISCircuit Sales, Inc.ItascaPh: (708) 773-0200FAX: (708) 773-2721INDIANAArete Sales, Inc.Fort WaynePh: (219) 423-1478FAX: (219) 420-1440LiztonPh: (317) 994-5084FAX: (317) 994-5088Microcomponents Inc.KokomoPh: (317) 454-6988FAX: (317) 454-6987KENTUCKYSee IndianaMARYLANDBurgin-Kreh AssociatesBaltimorePh: (410) 265-8500FAX: (410) 265-8536MASSACHUSETTSMill-Bern AssociatesWoburnPh: (617) 932-3311FAX: (617) 932-0511MICHIGANTrilogy Marketing, Inc.Auburn HillsPh: (810) 377-4900FAX: (810) 377-4906MISSISSIPPIRefer calls to Elcom, Huntsville, ALNEBRASKARefer calls torush & west associates, inc.Davenport, IAPh: (319) 388-9494FAX: (315) 388-9609NEW JERSEY - NORTHTechnical Marketing GroupWest CaldwellPh: (201) 226-3300FAX: (201) 226-9518NEW JERSEY - SOUTHOmni SalesErdenheim, PAPh: (21 5) 233-4600FAX: (215) 233-4702NEW YORKElectra SalesRochesterPh: (716) 427-7860FAX: (716) 427-0614E ast SyracusePh: (315) 463-1248FAX: (315) 463-1717NEW YORK (Long Island)Technical Marketing GroupMelvillePh: (516) 351-8833FAX: (516) 351-8667NORTH CAROLINARefer calls to Elcom, Norcross, GAOHIOMillennium Technical SalesCincinnatiPh: (513) 871-2424FAX: (513) 871-2524ColumbusPh: (614) 793-9545FAX: (614) 793-0256ClevelandPh: (216) 461-3500FAX: (216) 461-.1335PENNSYLVANIAOmni SalesErdenheimPh: (21 5) 233-4600FAX: (215) 233-4702SOUTH CAROLINARefer calls to Elcom, Norcross, GATENNESSEERefer calls to Eicom, Huntsville, ALVIRGINIABurgin-Kreh AssociatesRefer calls toBurgin-Kreh, MarylandWISCONSINCircuit Sales, Inc.WaukeshaPh: (414) 542-6550FAX: (414) 542-271111-0

IInternationalDistributors & Sales RepresentativesEUROPEHEADQUARTERSSilicon Systems, EuropeThe Business CentreGor-ray House758-760 Great Cambridge Rd.EnfieldMiddlesex EN13RN, EnglandPh: (44) 81-443-7061FAX: (44)81-443-7022AUSTRIACodico GmbhPerchtoldsdorf bei WienPh: (43) 1-863-05FAX: (43) 1-863-05-98BELGIUMAlcom Electronics nvlsaKontichPh: (32) 3-458-3033FAX: (32) 3-458-3126DENMARKOptoTelHoltePh: (45) 4541-0506FAX: (45) 4242-0730ENGLANDMagna Technology (Rep. Sales only)Swallowfield, BerkshirePh: (44) 73-488-0211FAX: (44) 73-488-2116Pronto (Distribution Sales only)liford, EssexPh: (44) 81-554-6222FAX: (44) 81-518-3222Cristel UK LTD(Distribution Sales only)AylesburyPh: (44) 296-393-134FAX: (44) 296-393-136FINLANDBexab FinlandEspooPh: (358) 0-5023200FAX: (358) 0-5023294FRANCEMISILRungis CedexPh: (33) 1-45-60-00-21FAX: (33) 1-45-60-01-86GERMANYAtlantik Elektronik GmbH(Distribution Sales Only)MunichPh: (49) 89-857-0000FAX: (49) 89-857-3702HamburgPh: (49) 40-241-072FAX: (49) 40-241-074Data Tech GmbHGermeringPh: (49) 89-8947-0030FAX: (49) 89-84-2072GREECEPeter Caritato & Associates, Ltd.AthensPh: (30) 1-902-0115FAX: (30) 1-901-7024IRELANDMemec Ireland, Ltd.Limerick, Republic of IrelandPh: 353-61-411842FAX: 353-61-411888ITALYCefralSprague Ita/ianaMilanoPh: (39) 2-4801-2355FAX: (39) 2-4800-8167THE NETHERLANDSAlcom Electronics BV2908 U Capelle AID IJSSELPh: (31) 10-451-9533FAX: (31) 10-458-6482NORWAYHans H. Schive(Distribution Sales Only)AskerPh: (47) 66-900-900FAX: (47) 66-904-484PORTUGALDiodeLisboaPh: (351) 1-386-4157FAX: (351) 1-386-0987SPAINDiodeMadridPh: (34) 1-555-3686FAX: (34) 1-556-7159Amitron-Arrow S.A.MadridPh: (34) 1-542-09-06FAX: (34) 1-541-76-55SWEDENBexab Technology ABTlIbyPh: (46) 8-630-8800FAX: (46) 8-732-7058SWITZERLANDEllypticAGZurichPh: (41) 1-493-1000FAX: (41) 1-492-2255YUGOSLAVIAEllypticAGMariborPh: (38) 61-223-787AFRICA & MID. EASTAFRICA (Excluding South Africa)Monte Vista International5673 W. Las Positas BI., Ste. 205Pleasanton, CA 94588 U.S.A.Ph: (510) 463-8693FAX: (510) 463-8732REP. OF SOUTH AFRICAPrime Source (PTY) LTDOrange GrovePh: 27-11-444-723727-11-444-7298ISRAELMTI Engineering, Ltd.Tel AvivPh: (972) 3-648-7901FAX: (972) 3-648-7940TURKEYInterIstanbulPh: (90) 216-349-9400FAX: (90) 216-349-9430RUSSIAP.T.G.Laguna Beach, CaliforniaPh: (714) 499-6736FAX: (714) 499-9507FAR EAST(excluding Japan)HEADQUARTERSSilicon Systems, Singapore3015A Ubi Road 1, #01-01Kampong UBI Industrial EstateSingapore 1440Ph: (65) 744-7700FAX: (65) 748-2431AUSTRALIAR&D ElectronicsVictoriaPh: (61) 3-558-0444FAX: (61) 3-558-0955HONG KONGCET, Ltd.Kwai FongPh: (852) 2-485-3899FAX: (852) 2-485-3802KOREAHanaro CorporationSeoulPh: (82) 2-516-1144FAX: (82) 2-516-1151MALAYSIADynamar Computer ProductsPenangPh: 604-228-1860FAX: 604-228-1420NEW ZEALANDApex Electronics, Ltd.(Distribution Sales Only)WellingtonPh: (64) 4-385-3404FAX: (64) 4-385-3483PHILIPPINESMaedan EnterprisesManilaPh: (632) 812-3307FAX: (632) 823-7486SINGAPOREDynamar Computer ProductsPh: (65) 281-3388FAX: (65) 281-3308TAIWANDynamar Taiwan Co., Ltd.TaipeiPh: (886) 2-721-3007FAX: (886) 2-775-1597THAILANDDynamar Computer ProductsBangkokPh: (662) 376-0132FAX: (662) 376-0133JAPANSSifTDK CORP. HEADQUARTERS(Distribution Sales Only)1-13-1 Nihonbashi, Chuo-KuTokyo 103, JapanPh: (81) 3-5201-7231FAX: (81) 3-5201-7232MEXICOCHIHUAHUA & SONORA ONLYWestern High Tech. MarketingAlbuquerque, New MexicoPh: (505) 884-2256FAX: (505) 884-2258All other areas:SONIKAMexico CityPh: (52) 5-754-6480FAX: (52) 5-752-2787GuadalajaraPh: (52) 36-474250FAX: (52) 36-473433SOUTH AMERICAARGENTINAYEL S. R. L.Buenos AiresPh: (45) 1-372-7140FAX: (45) 1-476-2551BRAZILEtek (Distribution Sales Only)Boca Raton, FloridaPh: (407) 997-6277FAX: (407) 997-5467HitechSao PauloPh: (55) 11-505-5299FAX: (55) 11-505-2984CHILEVictronics, Ltd.Santiago CentroPh: (56-2) 633-0237(56-2) 633-2787FAX: (56-2) 633-4432CANADAALBERTAEnerlec - CalgaryPh: (403) 256-3627FAX: (403) 254-9121BRITISH COLUMBIAEnerlec - RichmondPh: (604) 273-0882FAX: (604) 273-0884ONTARIOHar-Tech - ConcordPh: (905) 660-3419FAX: (905) 660-5102Har-Tech - NepeanPh: (613) 726-9410FAX: (613) 726-8834QUEBECHar-Tech - Pointe ClairePh: (514) 694-6110FAX: (514) 694-8501I11-1

North AmericanAuthorized Distributor OfficesPioneer SE = Pioneer StandardElectronics Inc.Pioneer TG = PioneerTechnologies GroupALABAMAFLORIDANu HorizonsNu HorizonsHuntsvilleAltamonte SpringsPh: (205) 722-9930 Ph: (407) 831-8008FAX: (205) 722-9348 FAX: (407) 831-8862PioneerTGFt. LauderdaleHuntsville Ph: (305) 735-2555Ph: (205) 837-9300 FAX: (305) 735-2880FAX: (205) 837-9358PioneerTGARIZONAAlamonte SpringsAved, Inc. Ph: (407) 834-9090Phoenix FAX: (407) 834-0865Ph: (602) 951-9788Deerfield BeachFAX: (602) 951-4182 Ph: (305) 428-8877CALIFORNIA FAX: (305) 481-2950Aved,lnc.GEORGIASan DiegoNu HorizonsPh: (619) 558-8890NorcrossFAX: (619) 558-3018 Ph: (404) 416-8666Tustin FAX: (404) 416-9060Ph: (714) 573-5000Pioneer TGFAX: (714) 573-5050DuluthNu Horizons Ph: (404) 623-1003San Jose FAX: (404) 623-0665Ph: (408) 434-0800ILLINOISFAX: (408) 434-0935PioneerSEPioneerSEAddisonAgora Hills Ph: (708) 495-9560Ph: (818) 865-5800 FAX: (708) 495-9831FAX: (818) 865-5814MARYLANDIrvineNu HorizonsPh: (714) 753-5090ColumbiaFAX: (714) 753-5074Ph: (410) 995-6330San Diego FAX: (410) 995-6332Ph: (619) 546-4906PioneerTGFAX: (619) 535-8154GaithersburgPioneerTG Ph: (301) 921-0660San Jose FAX: (301) 921-4255Ph: (408) 954-9100MASSACHUSETTSFAX: (408) 954-9113Nu HorizonsWesternWakefieldMicro technology Ph: (617) 246-4442Greater LA area FAX: (617) 246-4462Ph: 1 (800) 634-2248PioneerSEIrvineLexingtonPh: (714) 637-0200 Ph: (617) 861-9200FAX: (714) 998-1883 FAX: (617) 863-1547San DiegoWesternPh: (619) 453-8430Micro technologyFAX: (619) 453-1465BurlingtonSaratoga Ph: (617) 273-2800Ph: (408) 725-1660 FAX: (617) 229-2815FAX: (408) 446-0413MICHIGANCOLORADOPioneerSEAvedGrand RapidsWheat Ridge Ph: (616) 698-9600Ph: (303) 422-1701 FAX: (616) 698-1831FAX:(303) 422-2529PlymouthPioneerTG Ph: (313) 416-2157Denver FAX: (313) 416-2415Ph: (719) 548-0816MINNESOTAFAX: (719) 590-1537PioneerSECONNECTICUTEden PrairieNu Horizons Ph: (612) 944-3355Danbury FAX: (612) 944-3794Ph: (203) 265-0162MISSOURIPioneerSEPioneerSESheltonSt. LouisPh: (203) 929-5600 Ph: (314) 542-3077FAX: (203) 929-9791 FAX: (314) 542-3078NEW JERSEYNu HorizonsPine BrookPh: (201) 882-8300FAX: (201) 882-8398PioneerSEFairfieldPh: (201) 575-3510FAX: (201) 575-3454WesternMicrotechnologySo. New Jersey/PhiladelphiaPh: (609) 596-7775FAX: (609) 985-2797NEW YORKNu HorizonsAmityvillePh: (516) 226-6000FAX: (516) 226-0082RochesterPh: (716) 292-0777FAX: (716) 292-0750PioneerSEBinghamtonPh: (607) 722-9300FAX: (607) 722-9562FairportPh: (716) 381-7070FAX: (716) 381-5955New YorkPh: (212) 631-4700FAX: (212) 971-0374WoodburyPh: (516) 677-1720FAX: (516) 921-2143NORTH CAROLINAPioneerTGMorrisvillePh: (919) 460-1530FAX: (919) 460-1540OHIOPioneerSEClevelandPh: (216) 587-3600FAX: (216) 663-1004DaytonPh: (513) 236-9900FAX: (513) 236-8133WorthingtonPh: (614) 848-4854FAX: (614) 848-4889OKLAHOMAPioneerSETulsaPh: (918) 665-7840FAX: (918) 665-1891OREGONWesternMicrotechnologyBeavertonPh: (503) 629-2082FAX: (503) 629-8645PioneerTGBeavertonPh: (503) 626-7300PENNSYLVANIANu HorizonsMount Laurel, New JerseyPh: (215) 557-6450 - PAPh: (609) 231-0900 - NJFAX: (609) 231-9510 - NJ FAXPioneerSEPittsburghPh: (412) 782"1.2300FAX: (412) 963-8255Pioneer TGHorshamPh: (215) 674-4000FAX: (215) 674-3107TEXASNu HorizonsDallasPh: (214) 488-2255FAX: (214) 488-2265Pioneer SEAustinPh: (512) 835-4000FAX: (512) 835-9829DallasPh: (214) 386-7300FAX: (214) 490-6419Houstonph: (713) 495-4700FAX: (713) 495-5642San AntonioPh: (512) 377-3440FAX: (512) 378-3626UTAHAved Inc.MidvalePh: (801) 565-8300FAX: (801) 565-9983WASHINGTONPioneer TGBellevuePh: (206) 644-7500FAX: (206) 644-7300Western MicrotechnologyBellevuePh: (206) 453-1699FAX: (206) 453-1827WISCONSINPioneerSEBrookfieldPh: (414) 784-3480FAX: (414) 784-8207CANADAONTARIOHar-Tech ElectronicsConcordPh: (905) 660-3419FAX: (905) 660-5102BRITISH COLUMBIAEnerlecCalgaryPh: (403) 256-3627RichmondPh: (604) 273-0882FAX: (604) 273-088411-2

SILICON SYSTEMS'MISSION STATEMENTExceed customer expectations bydeveloping and manufacturing the highest qualitycustom and standard, system-level mixed-signalintegrated circuits and MSICs®-based subsystems.The mission statement provides the foundation fromwhich we operate. The continuous improvement missionstatement outlined below supports the overall corporatemission and enhances it.SILICON SYSTEMS'CONTINUOUS IMPROVEMENTMISSION STATEMENTBe the supplier of choice by exceedingcustomer expectations throughcontinuous improvements in ourproducts, systems and services.Jiluon Jl rskmJ"A TDK ~ompanY

Silicon Systems, Inc.Communications Products Division14351 Myford Road, Tustin, CA 92680-7022Ph (714) 573-6000, Fax (714) 573-6914E-Mail: cpd@SSi1.com© 1995 Silicon Systems • Printed in the U.S.A.