estimation of path delays using vhdl logic simulation - LEDA

its output, but rising transition at an input is capable toproduce falling transition at the output only if risingtransition had previously arrived at the other gate input.Delay model of arbitrary complexity can be applied, takinginto account input signal slopes, loading capacitances andother parameters that influence ranges of gate delays tr andtf. Each time a delay attribute of output signal f is changed,an event must be scheduled to signal f with zero delay inorder to activate the processes performing the timingsimulation in the gates driven by the NAND gate.To implement the timing simulation algorithm in logicsimulator, a generalized signal attribute modeling mechanismis proposed in [2]. It is built in AleC++ hardware descriptionlanguage – the input language of Alecsis simulator [7]. InAleC++ user-defined signal attributes can be accessed andupdated in the processes during the simulation. Theexperimental results presented in [2] show that the proposedmethod is fast and appropriate for interactive use during logicverification.3. IMPLEMENTATION IN VHDLAlthough the user-defined signal attributes are availablein VHDL [87], they cannot be accessed and updated from theprocesses during the simulation. Therefore, a differentmodeling mechanism is necessary for the implementation ofthe timing simulation in VHDL simulator. We propose theuse of composite signals of the record type. Such acomposite signal consists of logic state and the timingattributes arr1mn, arr1mx, arr0mn, arr0mx, d1mn, d1mx,d0mn and d0mx. The record type DCSM_std_logic for the scalarsignals can be declared in VHDL as:type DCSM_std_logic is recordstatemn: std_ulogic;d0mn: time;d1mn: time;arr0mn: boolean;arr1mn: boolean;statemx: std_ulogic;d0mx: time;d1mx: time;arr0mx: boolean;arr1mx: boolean;end record DCSM_std_ulogic;For the bus signals type DCSM_std_logic_vector can bedeclared as:type DCSM_std_logic_vector is array(natural range ) of DCSM_std_logic;Assuming the input and output signals of theDCSM_std_logic type, the complete model of a two-inputNAND gate can be described in VHDL as shown in Fig. 2.Processes labeled p1 and p2 are intended for standard logicsimulation. They model the logic function and delay functionof the NAND gate. Processes labeled p3 and p4 are intendedfor the timing simulation. They monitor the timing attributesof gate inputs inp1 and inp2 and update the timing attributesof gate output oupt.Note that processes p3 and p4 are sensitive to the timingattributes of the input signals inp1 and inp2, but not to theirlogic states. Similarly, process p1 and p2 are sensitive toevents on input signal states, but not to their timing attributes.Hence, the two types of processes are independent. Logicsimulation and timing simulation can be performedseparately or simultaneously.It is also important that the changes of the timingattributes of the output signal outp are always scheduled withzero delay in processes p3 and p4. If the timing simulation isinitiated at some time instant of simulation time, it will befinished at the same time instant, since the activity related totiming simulation is performed with no delay. We suggestthat timing simulation should be performed in initial timeinstant t=0 of simulation. If no timing attribute is changedduring the simulation, timing simulation is suppressed andthe simulator performs standard logic simulation. Timingsimulation is invoked by setting the timing attributes arr1mn,arr1mx, arr0mn and arr0mx of primary inputs to value true. Ifthe primary inputs are grouped into a bus signal inp, thetiming analysis can be invoked by only one concurrent signalassignment command:inp ('0', 0 sec, 0 sec, true, true, '0', 0 sec, 0 sec, true, true));.Once the simulation time advances to t>0 sec, longest andshortest path delays of all signals in the circuit are availableand can be logged out. One additional process in the toplevelentity can be added that waits for some small timeperiod (for example, 1 pico second), prints the shortest andthe longest path delays to the screen or file, and thensuspends to the end of the simulation. An example of such aprocess is as follows:log: processbeginwait for 1 ps;--- print the timing analysis resultswait;end process log;entity nandg isgeneric (tpd_hlmn : time := 0.95 ns;tpd_lhmn : time := 1 ns;tpd_hlmx : time := 0.9 ns;tpd_lhmx : time := 1.05 ns);port (out1 : out DCSM_std_logic := ('0', 0.0 sec, 0.0 sec, false,false, '0', 0.0 sec, 0.0 sec, false, false);in1, in2: in DCSM_std_logic := ('0', 0.0 sec, 0.0 sec, false,false, '0', 0.0 sec, 0.0 sec, false, false));end nandg;architecture only of nandg isbegin---- Logic function:p1: process(in1.statemn, in2.statemn)variable val,ex_value : std_logic := '0';beginval := in1.statemn and in2.statemn;val := not (val);if val /= ex_value thenex_value := val;case val iswhen '0' =>out1.statemn out1.statemn end case;end if;end process p1;p2: process(in1.statemx, in2.statemx)variable val,ex_value : std_logic := '0';beginval := in1.statemx and in2.statemx;val := not (val);if val /= ex_value thenex_value := val;case val iswhen '0' =>out1.statemx out1.statemx end case;100