estimation of path delays using vhdl logic simulation - LEDA

ISCAS'85 circuit, the simulation result was a list of d1 andd0, minimal and maximal parameters of all primary outputsignals. The maximal of these values is given in column D mx,while the minimal values are given in column D mn of Table 1representing the delay of the longest and the shortest paths inthe circuit.CircuitnameTable 1: Results of timing and logic simulation of ISCAS'85benchmark circuits with a VHDL simulatorNumberofsignalsNumberofinputsNumberofoutputsNumberofgatesD[ns]D fmn[ns]D fmx[ns]D rmn[ns]D rmx[ns]c17 11 5 2 6 3 1.95 2.85 1.95 3c432 196 36 7 160 17 1.95 16.5 1.95 16.5c499 243 41 32 202 11 0.95 1125 1 11.4c880 443 60 26 383 24 5.8 23.4 5.9 23.7c1355 587 41 32 546 24 2.9 23.55 2.95 23.25c2670 1426 233 140 1193 32 4.9 31.65 4.85 31.2c3540 1719 50 22 1669 47 13.7 46.2 13.5 46.95c5315 2485 178 123 2307 49 3.95 48.3 3.85 47.25c6288 2448 32 32 2416 124 4.85 120.9 4.9 120.9c7552 3719 207 108 3512 43 5.9 41.85 5.8 42To estimate the additional CPU time consumed by thetiming simulation during the simulator run, the ISCAS'85circuits are also simulated using standard logic packageieee.std_logic_1164. Signals of type std_logic and std_logic_vectorwere used in this experiment. Since timing simulation in thefirst experiment is finished at t=2 picoseconds, the logicsimulation in the second experiment is also finished at t=2picoseconds. Timing simulation does not increasesignificantly the total CPU time.5. CONCLUSIONDuring the design process of digital integrated circuits itis extremely important to estimate the longest and theshortest path delays as early as possible. Design verificationis one of the early phases in the design process. It is usuallyperformed using a logic simulator to verify that the circuitmeets the required logic function and a timing simulator toverify that the circuit meets the required timingspecifications. The method proposed in this paper combinesthese two tools into one by enabling the VHDL simulator toperform the timing simulation. In this way the design processis simplified and accelerated.The problem of introducing of the timing simulation intothe VHDL simulator is solved by the use of signals of recordtype in VHDL. Additional timing data is associated with eachsignal and used only when the timing simulation is requested.Eight timing attributes are added to each signal.Extra memory for storing the timing attributes isproportional to the total number of signals in the circuit. Forsimulated ISCAS'85 circuits this number is less than 4000.Even if very complex circuits with millions of signals shouldbe simulated, the required extra memory would be of theorder of only tens of Mbytes. Storing memory is not a criticalissue and the simulator performance should not be affectedby the memory requirements.The experimental results also indicate that extrasimulation CPU time due to timing simulation is almostnegligible for ISCAS'85 circuits. Timing simulation affectsonly the initialization phase of the simulation, whereas therest of the simulation flow usually takes the most of the CPUtime. The proposed method is simple for implementation andlibraries of gate models used in semi-custom designmethodologies.REFERENCES[1] D. M. Maksimović, V. B. Litovski, "LogicSimulation Methods For Longest Path DelayEstimation", IEE Proc.-Comput. Digit. Tech., Vol.149, No. 2, March 2002.[2] D. M. Maksimović, V. B. Litovski, "Tuning logicsimulators for timing analysis", Electronics Letters,Vol. 35, No. 10, pp. 800-802, Stevenage, UK, May1999.[3] J. K. Ousterhout, "CRYSTAL: A Timing Analyzerfor NMOS VLSI Circuits", Proc. 3rd Caltech Conf.on VLSI, pp. 57-69, March 1983.[4] N. Jouppi, "TV: An NMOS Timing Analyzer", Proc.3rd Caltech Conf. on VLSI, pp. 71-85, March 1983.[5] C. Oh, M.R. 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Symp. on Circuits andSystems, pp. 1929-1934, Kyoto, Japan, June 1985.[10] Active-HDL, ver. 5.1, ALDEC Inc., 2003.Sadržaj – U ovom radu predložen je metod analizekašnjenja korišćenjem VHDL simulatora. Ovaj metod jenadgradnja onih objavljenih u [1, 2], i omogućavasumulatoru da odredi minimalna i maksimalna kašnjenja svihputeva u kolu, i to izvršavanjem samo jedne simulacije ukolu. Vremenska analiza se izvršava u trenutku t=0, i samoneznatno produžava procesorsko vreme potrebno zasimulaciju. Da bi se verifikovala efikasnost predloženogmetoda, prikazani su i rezultati simulacije ISCAS'85benchmark kola, korišćenjem VHDL simulatora. Ovaj metodizuzetno je pogodan u ranim fazama procesa projektovanjagde je potrebno ponavljati vremensku analizu uvek kada sekolo optimizuje ili redizajnira.PROCENA KAŠNJENJA LOGIČKOG PUTAKORIŠĆENJEM VHDL LOGIČKE SIMULACIJEMiljana Sokolović and Dejan Maksimović102