ARM Instruction set

ARM Instruction setARM instruction set format

ARM instruction set (1)ARM instruction set (2)

Condition Code Branch Instructions• Branch and Branch with Link (B,BL)B{L}{}

Branch Instructions• Example (Data ProcessingInstructions)

(Data ProcessingInstructions)(Data ProcessingInstructions)• {cond}{S} Rd, qMOVMVN• {cond} Rn, qCMP,CMN,TEQ,TST ()• {cond}{S} Rd, Rn, qAND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC

(Data ProcessingInstructions)• Immediate Operand=1• Exampleq MOV R0, #100 //R0=100q CMP R1, #200 // R1 200q ADD R0, R1, #0x0ff //R0 = R1 + 0x0ff(Data ProcessingInstructions)• Immediate Operand=0q Shift

(Data ProcessingInstructions)q (Logical Shift Left, LSL)(Data ProcessingInstructions)q (Logical Shift Right, LSR)

(Data ProcessingInstructions)q (Arithmetic Shift Right, ASR)(Data ProcessingInstructions)q (Rotate Right, ROR)

(Data ProcessingInstructions)• Exampleq MOV R0, R1, LSR #3 //R0 = R1>>3q SUB R0, R1, R2, LSL #5 //R0 = R1 – (R27)q MOV R3, R4, LSL R5 //R5(Rs)//R4PSR Transfer (MRS, MSR)• MRS: Move register from SPSR orSPSR_

(PSR)• MRS- PSR registerq MRS{cond} Rd, q Example:• MRS R1, CPSR //R1= CPSR• MRS R2, SPSR //R2 = SPSR• MSR- register PSRq MSR{cond} , Rmq Example:• MSR SPSR, R0 // SPSR= R0(PSR)• MSR- register PSRqqMSR{cond} , RmExample:• MSR CPSR_c, R3//CPSR[7:0] = R3[7:0]• MSR-PSRqqMSR{cond} , Example:• MSR CPSR_f, #0xe0000000 //CPSR[31:28]=0b1110

(Block Data Transferinstructions)(Block Data Transferinstructions)• {cond}Rn{!}, {^}qqqRn{}{R0R1-R7R8}{!} !(W=1)(W=0)

(Block Data Transferinstructions)• Addressing mode names• Increment after

• Increment after• Increment before

• Increment after• decrement after

• decrement after• decrement before

• decrement before(Coprocessor Instructions)• Coprocessor Register Transfer Instructionsq MCR (Move to Coprocessor from ARM Register)q MRC (Move to ARM Register from Coprocessor)

(Coprocessor RegisterTransfer Instructions)(Coprocessor RegisterTransfer Instructions)• {cond}p#,,Rd,cn,cm{,}qqqqqqqqMRCCoprocessor ARMMCRARMCoprocessor{cond}p# CoprocessorCP OpcRd ARMcn and cm CoprocessorCP

(Coprocessor RegisterTransfer Instructions)• Exampleq MRC p15, 2, R2, c1, c2, 3// 15 (CP15)//opcode 1=2, opcode 2= 3//CP15 source register 1 and 2//transfer data to ARM register, R2