Simulation, Design and Hardware Implementation of a Low Cost ...

Asian Transactions on Engineering (ATE ISSN: 2221-4267) Volume 02 Issue 01Simulation, Design and Hardware Implementation of a LowCost ProcessorAteeq A. KhanAbstract -Embedded microprocessor has beenwidely used as a tool for technological innovationsand cost reduction for the last forty years. Themain characteristic determining its performanceare its speed and programmability. Therefore, fora design to be competitive its processor has to fitfor the characteristics like: relativeinexpensiveness, flexibility, adaptation, speed andre-configurability. A solution to this is the use ofField Programmable Gate Arrays (FPGA). Thispaper describes the realization of a 4-bit FPGAbased simple low cost processor. The system isimplemented on the Xilinx Spartan 3xc3s200FT256 using ISE foundation 9.2i andVHDL. 88(4%) of the slices are used. A maximumfrequency of 61.451 MHz was reached with amaximum delay of 10.145 ns.Keywords: Processor, FPGA, VHDL, Simulation,SynthesisI. INTRODUCTIONFigure 1 shows how the different parts andcomponents fit together to form the microprocessor.From transistors, the basic logic gates are built. Logicgates are combined together to form eithercombinational circuits or sequential circuits. Thedifference between these two types of circuits is onlyin the way the logic gates are connected together.Latches and flip-flops are the simplest forms ofsequential circuits, and they provide the basicbuilding blocks for more complex sequential circuits.Certain combinational circuits and sequential circuitsare used as standard building blocks for largercircuits, such as the microprocessor. These standardcombinational and sequential components usually arefound in standard libraries and serve as largerbuilding blocks for the microprocessor. Differentcombinational components and sequentialcomponents are connected together to form either thedatapath or the control unit of a microprocessor. Thecircuit for either a dedicated or a generalmicroprocessor in the end will be produced bycombining the datapath and the control unit together.Microprocessor is the main building block fortechnological components and functions as the heartof smart devices. It has a wide range of uses and ahuge market. These days embedded microprocessorsare used in wireless communication, computing androbotic devices. They comprise thousands ofelectronic components and use a collection ofmachine instructions which enables them to performmathematical operations and transfer informationfrom one memory location to another. The hardwareimplementation of a simple low cost 4-bitmicroprocessor on a Spartan 3 FPGA (fieldprogrammable gate array) is developed whichperforms programming of some simple operationsusing VHDL.CombinationalCircuitsCombinationalComponentsTransistorsGatesFlip-FlopsSeq. CircuitsSequentialComponentsManuscript received February 11, 2012. This work was supportedby Salman Bin Abdul Aziz University, Al Kharj, Saudi Arabia.DatapathControl UnitDr. Ateeq Ahmad Khan is an Assistant Professor at theDepartment of Electrical Engineering at Salman Bin Abdul AzizUniversity. Phone-+966508840934 , Email ateeq@ksu.edu.saDedicatedMicroprocessorII.DIGITAL CIRCUITGeneralMicroprocessorFigure 1: Microprocessor ComponentsroMar 2012 ATE-10227012©Asian-Transactions 7

Asian Transactions on Engineering (ATE ISSN: 2221-4267) Volume 02 Issue 01III.MICROPROCESSOR DESIGNThis microprocessor performs the followinginstructionsGeneralformaLDA< taddr>ADDSUBJZJCANDObjectInstruction codeOperation Comment8 A loadAccumulatorAAr>B -MCDECMA 0If Z=1 thenPCIf C=1 thenPCMdirectAddAccumulatordirectSubAccumulatordirectJump onZero flag setJump onCarry flagsetlogic ANDAccumulatordirectComplementOperationINCA 2 IncrementAccumulatorDCRA 4 -1DecrementAccumulatorHLT 6 Halt Halt CPUA=AccumulatorM= Memoryaddr= AddressZ=Zero FlagC= Carry FlagTable 1: Instruction SetPC= Program CounterThe details about the design and actual architectureof the control unit, what operation code (opcode) isassigned to each of the instructions and how manybits are to be encoded in an instruction and what arethe control words used in micro program are given incontrol unit of microprocessor.III.(i)MEMORYAt first the memory was created as RandomAccesses Memory (RAM) with 16 words of 4-bits, inorder to support the store and load instructions, butsince our design has no actual inputs the memory wasturned into a Read Only Memory (ROM) with samesize so we can store our program that we want themicroprocessor to execute. As a result the storeoperation was canceled and subsequently theconnection between the accumulator and the memorywas eliminated.III.(ii) CONTROL UNIT DESIGNThe purpose of the control unit is to initiate aseries of sequential steps of micro-operations. Duringany given time, certain operations are to be initiatedwhile all others remain idle. Thus, the controlvariables at any given time can be represented by astring of l’s and 0's called a control word. As such,control words can be programmed to initiate thevarious components in the system in an organizedmanner. A control unit whose control variables arestored in a memory is called a micro program controlunit. Each control word of memory is called amicroinstruction, and a sequence of microinstructionsis called a micro program since alteration of themicro program is seldom needed, the control memorycan be a ROM. The use of a micro program involvesplacing all control variables in words of the ROM foruse by the control unit through successive readoperations. The content of the word in the ROM at agiven address determines the micro operations for thesystem. Figure 2 illustrates the general configurationof the micro program control unit. The controlmemory is assumed to be a ROM, within which allcontrol information is permanently stored. Thecontrol memory address register specifies the controlword read from control memory. It must be realizedthat a ROM operates as a combinational circuit, withthe address value as the input and the correspondingword as the output. The content of the specified wordremains on the output wires as long as the addressvalue remains in die address register, no read signalis needed as in a random-access memory. The wordout of the ROM should be transferred to a bufferregister if the address register changes while theROM word is still in use. If the change in addressand ROM word can occur simultaneously, no bufferregister is needed.Mar 2012 ATE-10227012©Asian-Transactions 8

Asian Transactions on Engineering (ATE ISSN: 2221-4267) Volume 02 Issue 01The word read from control memory represents amicroinstruction. The microinstruction specifies oneor more micro operations for the components of thesystem. Once these operations are executed, thecontrol unit must determine the next address. Thelocation of the next microinstruction may be the nextone in sequence, or it may be located somewhere elsein the control memory. For this reason, or it isnecessary to use some bits of the microinstruction tocontrol the generation of the address for the nextmicroinstruction. The next address may also be afunction of external input conditions. While themicro operations are being executed, the next addressis computed in the next-address generator circuit andthen transferred (with the next clock pulse) into thecontrol address register to read the nextmicroinstruction.III.(iii) CONTROL MEMORYControl memory is a ROM with 6-bitaddress given as 64 words, but actually only the first48 are used. Each word is 23-bit long of which themost significant 13-bit are sent to the datapath ascontrolling signals determining how each componentin the datapath behaves subject to what kind ofoperation is being preformed. The 6-bits after thecontrol bits in the control word are the brunch bitswhich make the ROM jump from one word toanother if needed depending on the status conditionscoming from the datapath particularly the zero andcarry flags as well as the signals from the IR . The 4least significant bits in the control word are thecondition selectors which select one of the statusconditions to be checked if needed and do so byserving as the selecting signals for a 16X1multiplexer where the output of the multiplexer is thecontrol signal for the MPC. Based on this way ofoperating, the controlling words were created. Afterthat the VHDL code was written for it and simulated.A simple behavioral model was used for creating theROM. Since it is a read-only memory, no clocksignal or write-enable pin is necessary. The circuitcontains a pile of pre-stored words, being the oneselected by the address input (addr) presented at theoutput (data).III.(iv)MICROPROCESSOR CONNECTIONSFigure 2: Control Unit ArchitectureThe microprocessor is built by connectingthe datapath with the control unit. This is done byusing the same method in creating the datapath andcontrol unit which is port mapping of the structuralmodel, with the inputs being a clock signal to helpregulate the transfer of data inside themicroprocessor, and a reset signal to make themicroprocessor go to the start of the control wordsstored in the ROM by resetting the MPC which holdsthe address of the ROM. The microprocessor has a 4-bit output which is the result of the instructionsexecuted by it.The program stored in the memory of the datapathwhich defines the instructions that will be executedand the order they are executed in, can be written inany manner seen appropriate for a specificfunction(s) that the microprocessor is intended toperform. The only limitation is that the space inwhich the instructions can be stored is limited to 16word, bearing in mind that some instructions needtwo words while other need only one word of space.The program written is designed to test all of theMar 2012 ATE-10227012©Asian-Transactions 9

Asian Transactions on Engineering (ATE ISSN: 2221-4267) Volume 02 Issue 01Figure 3: The Microprocessor Behavioral SimulationFigure 4: The Microprocessor Timing Simulationinstructions the microprocessor can perform in orderto determine the success of this paper.The behavioral simulation has been done to ensurethat the microprocessor performs the program storedin its memory, after that the place and routesimulation (timing simulation) is done to find out theMar 2012 ATE-10227012©Asian-Transactions 10

Asian Transactions on Engineering (ATE ISSN: 2221-4267) Volume 02 Issue 01delay and if it is too much that it could hinder theperformance of the microprocessor. Both simulationsare shown in figure 3 and figure 4.IV. CONCLUSIONA large number of low cost prototype boardsavailable for various FPGAs. This is certainly nottrue for ASICs as the tool cost alone can beprohibitive in many cases. The other reason for thelow setup cost is that the use of an FPGA means thatthe mask costs associated with an ASIC are avoidedwhich can be a significant saving for a moderntechnology.The design of the microprocessor isanalyzed carefully to ensure that any failure would becorrected, this is done at each step making sure thatevery component is functioning accurately on its ownand also when it is connected to other parts. Themeasure of accuracy is the simulation which couldgive a clear picture on how the component performsas well as helping in finding what causes failureswhen they occur.FPGA-based 4-bit microprocessor on XilinxSpartan 3 board is successfully implemented usingVHDL language. The microprocessor is made of thecontrol unit, an arithmetic logic unit (ALU), amemory unit and registers. The processor has amaximum frequency of 61.451 MHz and 88 slices areutilized. It can perform ten different instructions asdescribed in the specifications of the microprocessor.Simulations are done to ensure its functionality.The microprocessor can be upgraded by adding thestore instruction to it by changing the datapathmemory into a RAM, also by increasing the numberof bits the microprocessor can process; it could beused in many applications.As far as the future work is concerned, latestXilinx with new family of FPGA can be used to forspeed improvement and area reduction. Altera can betried for comparison of two technologies.REFERENCES[1] Enoch O. Hwang, “Digital Logic andMicroprocessor Design with VHDL”, Brooks Cole,2005.[2] Volnei. A. Pedroni, “Circuit Design with VHDL”,Massachusetts, MIT Press, 2004.[3] Pierre-Emanuel Gaillardon, M.Haykel Ben Jamma,Giovanni Betti Benevetti, Fabien Clermidy, LucaPerniola, “Emerging Memory Technologies forReconfigurable Routing in FPGA architecture”;IEEE International Conference on Electronics,Circuits and Systems (ICECS)-invited paper,December 2010.[4] J.Rose and D.Hill, “ Architectural and Physical DesignChallenges for One-Million Gate FPGAs andBeyond”, Proceedings of the ACM FifthInternational Symposium on Field-ProgrammableGate arrays, pp.129-132, Feb.1997.[5] Singh, et.al. “A Novel High ThroughputReconfigurable FPGA Architecture”, Proceedings ofthe ACM/SIGDA Symposium on Field-Programmable Gate arrays, pp. 22-29, Feb.2000.[6] M. Abd-El-Barr and H. El-Rewini, “Fundamentalsof Computer Organization and Architecture”, NewJersey, John Wiley & Sons. Inc, 2005.[7] E. Ayeh, K. Agbedanu, Y. Morita, O. Adamo, and P.Guturu, “FPGA Implementation of an 8-bit SimpleProcessor”, in the proceedings of Region 5Conference, 2008 IEEE held in Kansas City, MO,April 2008.[8] Baker, R. Jacob (2010). “CMOS: Circuit Design,Layout, and Simulation”, Third Edition. Wiley-IEEE.pp. 1174. ISBN 978-0-470-88132-3. http://CMOSedu.com/[9] Wiśniewski,Remigiusz . “Synthesis of compositionalmicroprogram control units for programmabledevices”. Zielona Góra: University of Zielona Góra.pp. 153. ISBN 978-83-7481-293-1.2009.[10] Ralph D. Wittig and Paul Chow. “OneChip: AnFPGA Processor with Reconfigurable Logic”. In TheFourth Annual IEEE Symposium on FPGAs forCustom Computing Machines FCCM'96, pages 126-135. IEEE, March 1996[11] P. A. Wilsey T. J. McBrayer, and D. Sims, "TowardsA Formal Model of VLSI Systems Compatible withVHDL," VLSI '91, A. Halaas and P. B. Denyer(eds), Elsevier Science Publishers B.V. (North-Holland), 225-236, 1991.[12] M. Kauppi and J-P. Soininen, "FunctionalSpecification and Verification of Digital Systemsusing VHDL Combined with Graphical StructuredAnalysis," EuroVHDL, 1991[13] D. Borrione and J. L. Paillet, "An approach to theformal verification of VHDL descriptions,"IMAG/Artemis, Grenoble, November 1987.[14] S. Hadjis, A. Canis, J.H. Anderson, J. Choi, K. Nam,S. Brown. T. Czajkowski, "Impact of FPGAarchitecture on resource sharing in high-levelsynthesis," to appear in the ACM/SIGDAInternational Symposium on Field ProgrammableGate Arrays, to be held at Monterey, CA, February2012.[15] M. H. Ben Jamaa, D. Atienza, Y. Leblebici, and G.De Micheli. “Programmable Logic Circuits Basedon Ambipolar CNFET”. Design AutomationConference (DAC), Anaheim, California, USA,2008.[16] Krishna Kant “Microprocessors andMicrocontrollers: Architecture Programming AndSystem Desig n”. PHI Learning Pvt. Ltd.,2007 ISBN 8120331915 page 61, describing theiAPX 432[17] Gerry Kane, Adam Osborne “16 Bit MicroprocessorHandbook”. ISBN 0079310435 (0-07-931043-5)Mar 2012 ATE-10227012©Asian-Transactions 11

Asian Transactions on Engineering (ATE ISSN: 2221-4267) Volume 02 Issue 01[18] L.Sterpone, M. Violante. “Hardening FPGA-basedsystems against SEUs: A new design methodology”.Academy Publisher Journal of Computers, Vol.1,No.1, April 2006, pp.22-30.[19] JD Plummer, M.D. Deal, P.B. Griffin, “Silicon VLSITechnology”, Prentice Hall Inc., USA, 2000[20] A.Singh, et al. “ A Novel High ThroughputReconfigurable FPGA Architecture”, Proceedings ofthe ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays, pp. 22-29. Feb 2000.Ateeq Ahmad Khan was born in India in 1955. Heobtained his PhD in Electronics Engineering fromAligarh Muslim University in 1999.He joined as Assistant Professor in AMU in 1981 andwas promoted as Associate Professor in 1987. Later,he joined Electrical Engineering Department, Collegeof Engineering, King Saud University, Riyadh in 2003and then joined Salman Bin Abdul Aziz University atAl Kharj and is presently continuing there. Dr. Khan isa fellow of Institute of Electronic andTelecommunication Engineering IETE and seniormember of Institution of Engineers, India.Mar 2012 ATE-10227012©Asian-Transactions 12