PIC16C55X, EPROM-Based 8-Bit CMOS MCU Data Sheet

PIC16C55X7.4 Power-on Reset (POR), Power-upTimer (PWRT), Oscillator Start-upTimer (OST)7.4.1 POWER-ON RESET (POR)A Power-on Reset pulse is generated on-chip whenVDD rise is detected (in the range of 1.6 V – 1.8 V). Totake advantage of the POR, just tie the MCLR pinthrough a resistor to VDD. This will eliminate externalRC components usually needed to create Power-onReset. A maximum rise time for VDD is required. SeeElectrical Specifications for details.The POR circuit does not produce internal reset whenVDD declines.When the device starts normal operation (exits thereset condition), device operating parameters (voltage,frequency, temperature, etc.) must be met to ensureoperation. If these conditions are not met, the devicemust be held in reset until the operating conditions aremet.For additional information, refer to Application NoteAN607 “Power-up Trouble Shooting”.7.4.2 POWER-UP TIMER (PWRT)The Power-up Timer provides a fixed 72 ms (nominal)time-out on power-up only, from POR. The Power-upTimer operates on an internal RC oscillator. The chip iskept in reset as long as PWRT is active. The PWRTdelay allows the VDD to rise to an acceptable level. Aconfiguration bit, PWRTE can disable (if set) or enable(if cleared or programmed) the Power-up Timer. ThePower-Up Time delay will vary from chip to chip anddue to VDD, temperature and process variation. SeeDC parameters for details.7.4.3 OSCILLATOR START-UP TIMER (OST)The Oscillator Start-Up Timer (OST) provides a 1024oscillator cycle (from OSC1 input) delay after thePWRT delay is over. This ensures that the crystaloscillator or resonator has started and stabilized.The OST time-out is invoked only for XT, LP and HSmodes and only on power-on reset or wake-up fromSLEEP.7.4.4 TIME-OUT SEQUENCEOn power-up, the time-out sequence is as follows: FirstPWRT time-out is invoked after POR has expired, thenOST is activated. The total time-out will vary based onoscillator configuration and PWRTE bit status. Forexample, in RC mode with PWRTE bit erased (PWRTdisabled), there will be no time-out at all. Figure 7-8,Figure 7-9 and Figure 7-10 depict time-out sequences.Since the time-outs occur from the POR pulse, if MCLRis kept low long enough, the time-outs will expire. Thenbringing MCLR high will begin execution immediately(see Figure 7-9). This is useful for testing purposes orto synchronize more than one PIC16C55X device operatingin parallel.Table 7-5 shows the reset conditions for some specialregisters, while Table 7-6 shows the reset conditions forall the registers.DS40143C-page 40 Preliminary © 1998 Microchip Technology Inc.