PIC16C55X, EPROM-Based 8-Bit CMOS MCU Data Sheet

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PIC16C55XFIGURE 7-14:WATCHDOG TIMER BLOCK DIAGRAMFrom TMR0 Clock Source(Figure 6-6)WatchdogTimer01•MUXPostscaler88 - to -1 MUXPSWDTEnable BitPSA•To TMR0 (Figure 6-6)01MUXPSAWDTTime-outNote: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.FIGURE 7-15:SUMMARY OF WATCHDOG TIMER REGISTERSAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on PORValue on allother Resets2007h Config. bits — + CP1 CP0 PWRTE WDTE FOSC1 FOSC081h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111Legend: Shaded cells are not used by the Watchdog Timer.— = Unimplemented location, read as ‘0’.+ = Reserved for future use.DS40143C-page 48 Preliminary © 1998 Microchip Technology Inc.
PIC16C55X7.8 Power-Down Mode (SLEEP)The Power-down mode is entered by executing aSLEEP instruction.If enabled, the Watchdog Timer will be cleared butkeeps running, the PD bit in the STATUS register iscleared, the TO bit is set, and the oscillator driver isturned off. The I/O ports maintain the status they had,before SLEEP was executed (driving high, low, orhi-impedance).For lowest current consumption in this mode, all I/Opins should be either at VDD, or VSS, with no externalcircuitry drawing current from the I/O pin. I/O pins thatare hi-impedance inputs should be pulled high or lowexternally to avoid switching currents caused by floatinginputs. The T0CKI input should also be at VDD orVSS for lowest current consumption. The contributionfrom on chip pull-ups on PORTB should be considered.The MCLR pin must be at a logic high level (VIHMC).Note:It should be noted that a RESET generatedby a WDT time-out does not drive MCLRpin low.7.8.1 WAKE-UP FROM SLEEPThe device can wake-up from SLEEP through one ofthe following events:1. External reset input on MCLR pin2. Watchdog Timer Wake-up (if WDT was enabled)3. Interrupt from RB0/INT pin or RB Port changeThe first event will cause a device reset. The two latterevents are considered a continuation of program execution.The TO and PD bits in the STATUS register canbe used to determine the cause of device reset. PDbit, which is set on power-up is cleared when SLEEP isinvoked. TO bit is cleared if WDT Wake-up occurred.When the SLEEP instruction is being executed, thenext instruction (PC + 1) is pre-fetched. For the deviceto wake-up through an interrupt event, the correspondinginterrupt enable bit must be set (enabled). Wake-upis regardless of the state of the GIE bit. If the GIE bit isclear (disabled), the device continues execution at theinstruction after the SLEEP instruction. If the GIE bit isset (enabled), the device executes the instruction afterthe SLEEP instruction and then branches to the interruptaddress (0004h). In cases where the execution ofthe instruction following SLEEP is not desirable, theuser should have an NOP after the SLEEP instruction.Note:If the global interrupts are disabled (GIE iscleared), but any interrupt source has bothits interrupt enable bit and the correspondinginterrupt flag bits set, the device willimmediately wakeup from sleep. The sleepinstruction is completely executed.The WDT is cleared when the device wakes-up fromsleep, regardless of the source of wake-up.FIGURE 7-16:WAKE-UP FROM SLEEP THROUGH INTERRUPTOSC1CLKOUT(4)Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4TOST(2)INT pinINTF flag(INTCON)GIE bit(INTCON)Processor inSLEEPInterrupt Latency(Note 2)INSTRUCTION FLOWPCInstructionfetchedInstructionexecutedPC PC+1 PC+2Inst(PC) = SLEEPInst(PC - 1)Inst(PC + 1)SLEEPPC+2Inst(PC + 2)Inst(PC + 1)PC + 2 0004h 0005hInst(0004h) Inst(0005h)Dummy cycle Dummy cycle Inst(0004h)Note 1: XT, HS or LP oscillator mode assumed.2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.4: CLKOUT is not available in these osc modes, but shown here for timing reference.© 1998 Microchip Technology Inc. Preliminary DS40143C-page 49
Page 4 and 5: PIC16C55XNOTES:DS40143C-page 4 Prel
Page 6 and 7: PIC16C55XTABLE 1-1:PIC16C55X FAMILY
Page 8 and 9: PIC16C55XNOTES:DS40143C-page 8 Prel
Page 10: PIC16C55XFIGURE 3-1: BLOCK DIAGRAMD
Page 15: PIC16C55X4.2.2 SPECIAL FUNCTION REG
Page 18 and 19: PIC16C55X4.2.2.3 INTCON REGISTERThe
Page 20 and 21: PIC16C55X4.3 PCL and PCLATHThe prog
Page 22 and 23: PIC16C55XNOTES:DS40143C-page 22 Pre
Page 24 and 25: PIC16C55XTABLE 5-1:PORTA FUNCTIONSN
Page 26 and 27: PIC16C55XFIGURE 5-4:BLOCK DIAGRAM O
Page 30 and 31: PIC16C55XFIGURE 6-3: TIMER0 TIMING:
Page 32 and 33: PIC16C55X6.3 PrescalerAn 8-bit coun
Page 36 and 37: PIC16C55X7.1 Configuration BitsThe
Page 38 and 39: PIC16C55X7.2.3 EXTERNAL CRYSTAL OSC
Page 40 and 41: PIC16C55X7.4 Power-on Reset (POR),
Page 42 and 43: PIC16C55XTABLE 7-5:INITIALIZATION C
Page 44 and 45: PIC16C55XFIGURE 7-11:EXTERNAL POWER
Page 46 and 47: PIC16C55X7.5.1 RB0/INT INTERRUPTAn
Page 50 and 51: PIC16C55X7.9 Code ProtectionIf the
Page 52 and 53: PIC16C55XTABLE 8-2:Mnemonic,Operand
Page 54 and 55: PIC16C55XBCFBit Clear fSyntax: [ la
Page 56 and 57: PIC16C55XCLRWDTSyntax:Operands:Oper
Page 58 and 59: PIC16C55XIORWFInclusive OR W with f
Page 60 and 61: PIC16C55XRETURN Return from Subrout
Page 62 and 63: PIC16C55XSWAPFSwap Nibbles in fSynt
Page 64 and 65: PIC16C55X9.6 SIMICE Entry-Level Har
Page 66 and 67: PIC16C55X9.16 KEELOQ ® Evaluation
Page 70 and 71: PIC16C55XTABLE 10-1:CROSS REFERENCE
Page 72 and 73: PIC16C55X10.2 DC CHARACTERISTICS: P
Page 74 and 75: PIC16C55X10.3 DC CHARACTERISTICS: P
Page 76 and 77: PIC16C55X10.5 Timing Diagrams and S
Page 78 and 79: PIC16C55XFIGURE 10-4:RESET, WATCHDO
Page 82 and 83: PIC16C55XPackage Type:K04-010 18-Le
Page 84 and 85: PIC16C55XPackage Type:K04-051 18-Le
Page 90 and 91: PIC16C55XPrescaler ................
Page 92 and 93: PIC16C55XREADER RESPONSEIt is our i
Page 96: WORLDWIDE SALES AND SERVICEAMERICAS

PIC16C55X, EPROM-Based 8-Bit CMOS MCU Data Sheet

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