PIC16C55X, EPROM-Based 8-Bit CMOS MCU Data Sheet

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<strong>PIC16C55X</strong>7.5.1 RB0/INT INTERRUPTAn external interrupt on RB0/INT pin is edge triggered:either rising if INTEDG bit (OPTION) is set, or fallingif INTEDG bit is clear. When a valid edge appearson the RB0/INT pin, the INTF bit (INTCON) is set.This interrupt can be disabled by clearing the INTEcontrol bit (INTCON). The INTF bit must be clearedin software in the interrupt service routine beforere-enabling this interrupt. The RB0/INT interrupt canwake-up the processor from SLEEP, if the INTE bit wasset prior to going into SLEEP. The status of the GIE bitdecides whether or not the processor branches to theinterrupt vector following wake-up. See Section 7.8 fordetails on SLEEP and Figure 7-16 for timing ofwake-up from SLEEP through RB0/INT interrupt.7.5.2 TMR0 INTERRUPTAn overflow (FFh → 00h) in the TMR0 register willset the T0IF (INTCON) bit. The interrupt canbe enabled/disabled by setting/clearing T0IE(INTCON) bit. For operation of the Timer0 module,see Section 6.0.7.5.3 PORTB INTERRUPTAn input change on PORTB sets the RBIF(INTCON) bit. The interrupt can be enabled/disabledby setting/clearing the RBIE (INTCON) bit.For operation of PORTB (Section 5.2).Note:If a change on the I/O pin should occurwhen the read operation is being executed(start of the Q2 cycle), then the RBIF interruptflag may get set.FIGURE 7-13:INT PIN INTERRUPT TIMINGQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4OSC1CLKOUT 34INT pinINTF flag(INTCON)151Interrupt Latency2GIE bit(INTCON)INSTRUCTION FLOWPCInstructionfetchedPC PC+1 PC+1 0004h 0005hInst (PC)Inst (PC+1)—Inst (0004h)Inst (0005h)InstructionexecutedInst (PC-1)Inst (PC)Dummy CycleDummy CycleInst (0004h)Note1: INTF flag is sampled here (every Q1).2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.3: CLKOUT is available only in RC oscillator mode.4: For minimum width of INT pulse, refer to AC specs.5: INTF is enabled to be set anytime during the Q4-Q1 cycles.DS40143C-page 46 Preliminary © 1998 Microchip Technology Inc.
<strong>PIC16C55X</strong>7.6 Context Saving During InterruptsDuring an interrupt, only the return PC value is savedon the stack. Typically, users may wish to save key registersduring an interrupt, e.g. W register and STATUSregister. This will have to be implemented in software.Example 7-1 stores and restores the STATUS and Wregisters. The user register, W_TEMP, must be definedin both banks and must be defined at the same offsetfrom the bank base address (i.e., W_TEMP is definedat 0x20 in Bank 0 and it must also be defined at 0xA0in Bank 1). The user register, STATUS_TEMP, must bedefined in Bank 0. The Example 7-1:• Stores the W register• Stores the STATUS register in Bank 0• Executes the ISR code• Restores the STATUS (and bank select bitregister)• Restores the W registerEXAMPLE 7-1:SAVING THE STATUS ANDW REGISTERS IN RAMMOVWF W_TEMP ;copy W to temp register,;could be in either bankSWAPF STATUS,W ;swap status to be saved into WBCF STATUS,RP0 ;change to bank 0 regardless;of current bankMOVWF STATUS_TEMP ;save status to bank 0;register:: (ISR):SWAPF STATUS_TEMP,W ;swap STATUS_TEMP register;into W, sets bank to original;stateMOVWF STATUS ;move W into STATUS registerSWAPF W_TEMP,F ;swap W_TEMPSWAPF W_TEMP,W ;swap W_TEMP into W7.7 Watchdog Timer (WDT)The watchdog timer is a free running on-chip RC oscillatorwhich does not require any external components.This RC oscillator is separate from the RC oscillator ofthe CLKIN pin. That means that the WDT will run, evenif the clock on the OSC1 and OSC2 pins of the devicehas been stopped, for example, by execution of aSLEEP instruction. During normal operation, a WDTtime-out generates a device RESET. If the device is inSLEEP mode, a WDT time-out causes the device towake-up and continue with normal operation. The WDTcan be permanently disabled by programming the configurationbit WDTE as clear (Section 7.1).7.7.1 WDT PERIODThe WDT has a nominal time-out period of 18 ms, (withno prescaler). The time-out periods vary with temperature,VDD and process variations from part to part (seeDC specs). If longer time-out periods are desired, aprescaler with a division ratio of up to 1:128 can beassigned to the WDT under software control by writingto the OPTION register. Thus, time-out periods up to2.3 seconds can be realized.The CLRWDT and SLEEP instructions clear the WDTand the postscaler, if assigned to the WDT, and preventit from timing out and generating a device RESET.The TO bit in the STATUS register will be cleared upona Watchdog Timer time-out.7.7.2 WDT PROGRAMMING CONSIDERATIONSIt should also be taken in account that under worst caseconditions (VDD = Min., Temperature = Max., max.WDT prescaler) it may take several seconds before aWDT time-out occurs.© 1998 Microchip Technology Inc. Preliminary DS40143C-page 47
Page 4 and 5: PIC16C55XNOTES:DS40143C-page 4 Prel
Page 6 and 7: PIC16C55XTABLE 1-1:PIC16C55X FAMILY
Page 8 and 9: PIC16C55XNOTES:DS40143C-page 8 Prel
Page 10: PIC16C55XFIGURE 3-1: BLOCK DIAGRAMD
Page 15: PIC16C55X4.2.2 SPECIAL FUNCTION REG
Page 18 and 19: PIC16C55X4.2.2.3 INTCON REGISTERThe
Page 20 and 21: PIC16C55X4.3 PCL and PCLATHThe prog
Page 22 and 23: PIC16C55XNOTES:DS40143C-page 22 Pre
Page 24 and 25: PIC16C55XTABLE 5-1:PORTA FUNCTIONSN
Page 26 and 27: PIC16C55XFIGURE 5-4:BLOCK DIAGRAM O
Page 30 and 31: PIC16C55XFIGURE 6-3: TIMER0 TIMING:
Page 32 and 33: PIC16C55X6.3 PrescalerAn 8-bit coun
Page 36 and 37: PIC16C55X7.1 Configuration BitsThe
Page 38 and 39: PIC16C55X7.2.3 EXTERNAL CRYSTAL OSC
Page 40 and 41: PIC16C55X7.4 Power-on Reset (POR),
Page 42 and 43: PIC16C55XTABLE 7-5:INITIALIZATION C
Page 44 and 45: PIC16C55XFIGURE 7-11:EXTERNAL POWER
Page 48 and 49: PIC16C55XFIGURE 7-14:WATCHDOG TIMER
Page 50 and 51: PIC16C55X7.9 Code ProtectionIf the
Page 52 and 53: PIC16C55XTABLE 8-2:Mnemonic,Operand
Page 54 and 55: PIC16C55XBCFBit Clear fSyntax: [ la
Page 56 and 57: PIC16C55XCLRWDTSyntax:Operands:Oper
Page 58 and 59: PIC16C55XIORWFInclusive OR W with f
Page 60 and 61: PIC16C55XRETURN Return from Subrout
Page 62 and 63: PIC16C55XSWAPFSwap Nibbles in fSynt
Page 64 and 65: PIC16C55X9.6 SIMICE Entry-Level Har
Page 66 and 67: PIC16C55X9.16 KEELOQ ® Evaluation
Page 70 and 71: PIC16C55XTABLE 10-1:CROSS REFERENCE
Page 72 and 73: PIC16C55X10.2 DC CHARACTERISTICS: P
Page 74 and 75: PIC16C55X10.3 DC CHARACTERISTICS: P
Page 76 and 77: PIC16C55X10.5 Timing Diagrams and S
Page 78 and 79: PIC16C55XFIGURE 10-4:RESET, WATCHDO
Page 82 and 83: PIC16C55XPackage Type:K04-010 18-Le
Page 84 and 85: PIC16C55XPackage Type:K04-051 18-Le
Page 90 and 91: PIC16C55XPrescaler ................
Page 92 and 93: PIC16C55XREADER RESPONSEIt is our i
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PIC16C55X, EPROM-Based 8-Bit CMOS MCU Data Sheet

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