"TMS320C55x DSP Library DSPLIB Programmer's Reference"

iircas4Benchmarks(preliminary)Cycles Core: nx*(7+ 31*nbiq)Overhead: 77Code size(in bytes)203iircas4FunctionCascaded IIR Direct Form II Using 4 Coefficients per Biquadushort oflag = iircas4 (DATA *x, DATA *h, DATA *r, DATA *dbuffer, ushort nbiq,ushort nx)(defined in iir4cas4.asm)Argumentsx [nx]Pointer to input data vector of size nxh[4*nbiq]r[nx]Pointer to filter coefficient vector with the followingformat:h = a11 a21 b21 b11 ....a1i a2i b2i b1iwhere i is the biquad index (a21 is the a2 coefficient ofbiquad 1). Pole (recursive) coefficients = a. Zero(non-recursive) coefficients = bPointer to output data vector of size nx. r can be equalthan x.dbuffer[2*nbiq] Pointer to address of delay line d.Each biquad has 2 delay line elements separated bynbiq locations in the following format:d1(n–1), d2(n–1),..di(n–1) d1(n–2), d2(n–2)...di(n–2)where i is the biquad index (d2(n–1) is the (n–1)thdelay element for biquad 2).nbiqIn the case of multiple-buffering schemes, this arrayshould be initialized to 0 for the first block only. Betweenconsecutive blocks, the delay buffer preservesthe previous r output elements needed.Memory alignment: this is a circular buffer and muststart in a k-bit boundary(that is, the k LSBs of thestarting address must be zeros) where k = log2(2*nbiq).Number of biquads4-56