"TMS320C55x DSP Library DSPLIB Programmer's Reference"

iircas51r[nx]dbuffer[4*nbiq]nbiqnxoflagPointer to output data vector of size nx. r can be equalthan x.Pointer to address of delay line dbuffer. Each biquadhas 4 delay line elements stored consecutively inmemory in the following format:x1(n–1), x1(n–2), y1(n–1), y1(n–2) ... xi(n–2), xi(n–2),yi(n–1),yi(n–2)where i is the biquad index(x1(n–1) is the (n–1)thdelay element for biquad 1).In the case of multiple-buffering schemes, this arrayshould be initialized to 0 for the first block only. Betweenconsecutive blocks, the delay buffer preservesthe previous r output elements needed.Memory alignment: No need for memory alignment.Number of biquadsNumber of elements of input and output vectorsOverflow flag. If oflag = 1, a 32-bit overflow has occurred. If oflag = 0, a 32-bit overflow has not occurred.DescriptionComputes a cascade IIR filter of nbiq biquad sections. Each biquad section isimplemented using Direct-form I. All biquad coefficients (5 per biquad) arestored in vector h. The real data input is stored in vector x. The filter outputresult is stored in vector r.This function retains the address of the delay filter memory d containing theprevious delayed values to allow consecutive processing of blocks. This functionis more efficient for block-by-block filter implementation due to the C-callingoverhead. However, it can be used for sample-by-sample filtering (nx = 1).The usage of 5 coefficients instead of 4 facilitates the design of filters with aunit gain of less than 1 (for overflow avoidance), typically achieved by filtercoefficient scaling.Algorithm(for biquad)y(n) b0*x(n) b1*x(n 1) b2*x(n 2) a1*y(n 1) a2*y(n 2)Overflow Handling MethodologySpecial Requirements noneImplementation Notes noneExampleNo scaling implemented for overflow prevention.See examples/iircas51 subdirectory4-60