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Wind River ICE 2 - Embedded Tools GmbH

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BenefitsSimplifies complex system design withvisibility into advanced multi-core SoCsthat cannot be provided by externallogic or bus analyzersEnables developers to isolate andresolve challenging multi-core systemlevelissuesProvides cost-effective JTAG solution- Allows access to multiple targets- Enables remote debugProtects investment through firmwareupgrades and support for a broad setof processors and operating systems- Supports ARM, ColdFire Intel, MIPS,and PowerPC architectures- Supports VxWorks, <strong>Wind</strong> <strong>River</strong> Linux,and open source Linux kernels- Optional Trace 2 real-time externaltrace unit (for supported processors)The <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 platform suppliesdevelopers with a rich set of features thatprovide support for a broad range ofdevelopment capabilities: target connectionand control management, download,flash programming, diagnostics, registerand memory access, cache support, andrun control, which includes hardware andsoftware breakpoints, data and expressionbreakpoints, stepping, trace support,and synchronized run control.The <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 platform is built ona flexible and extensible framework thatallows it to scale and extend capabilitiesto meet the needs of future complexdevice software development projects.Basic Run Control Support<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides developers witha direct connection to their targets. <strong>Wind</strong><strong>River</strong> <strong>ICE</strong> 2 supports devices from 32-bitmicrocontroller devices through complex64-bit multi-core processor SoCs.Through its support of industry-leadingmicroprocessors, <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 canconnect and manage devices. <strong>Wind</strong> <strong>River</strong><strong>ICE</strong> 2 provides support for the following:Target connection managementTarget resetDownloading software to the deviceFlash programmingStarting and stopping the deviceStepping (step one statement orinstruction into function calls and stepover or out of a function)Hardware and software breakpointsupportAccess to target registers and memoryAdvanced Run Control SupportTarget Initialization Files<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides developerswith a library of target initialization filesfor supported SoCs and semiconductorvendor reference design platforms.Developers are able to use these targetinitialization register files to quickly bringup their hardware and move on to thenext stage in the project.Hardware Diagnostics<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 features a suite ofhardware diagnostic scripts that providedevelopers with the ability to runlow-level diagnostic routines on theirsystems for the purpose of validatingaddress and data bus configuration aswell as verifying read/write memory.Hardware diagnostics include a comprehensivesuite of RAM tests, scope loops,and cyclic redundancy check (CRC) tests.Cache Support<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides developerswith access to L1 and L2 instruction anddata cache for supported processors.This data can be accessed and viewedwhen <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 is used with <strong>Wind</strong><strong>River</strong> Workbench On-Chip Debugging oraccessed through a rich command setwhen used with either Workbench’scommand shell, host shell, or the <strong>Wind</strong><strong>River</strong> On-Chip Debugging API.MMU Support<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides memorymanagement unit (MMU) support fortranslation lookaside buffer (TLB)configuration and management when<strong>ICE</strong> 2 is used with operating systems thatrequire the MMU to be enabled, such asVxWorks 6.x, VxWorks 653, and <strong>Wind</strong><strong>River</strong> Linux.Synchronized Run Control<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides simultaneousconnectivity to up to 16 cores. Whenused in this configuration, <strong>Wind</strong> <strong>River</strong><strong>ICE</strong> 2 can synchronously start and stopall cores or just some of them and setcross-correlated breakpoints so thatwhen a breakpoint is hit in one core itcan stop that core or all cores in thesystem.Internal Trace Buffer Support<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 supports the internaltrace buffer capabilities provided onsupported processors. When used with<strong>Wind</strong> <strong>River</strong> Workbench On-ChipDebugging, <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 can extracttrace data and provide a visual representationin the Workbench Trace view. Thiscapability provides developers withvisibility into what code executes on thetarget.Multi-core Debugging<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 was designed forcomplex multi-core debugging. Itfeatures <strong>Wind</strong> <strong>River</strong>’s JTAG servertechnology that leverages debugcapabilities of the processor andmanages multiple cores with a singleJTAG connection. This allows developersto do the following:Access a single device on the scanchain, or multiple devices simultaneously,to provide synchronous start andstop.Set breakpoints within a single core tohalt the execution of multiple cores.Establish and remove connectionswithout affecting any microprocessoror device on the scan chain.Simplified Usage<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides developerswith an LCD panel that displays an IPaddress and enables developers tobetter monitor debug status.High-Performance JTAG<strong>ICE</strong> 2’s efficient use of the JTAG interfaceeliminates slow download times and runcontrol when developing with on-chipdebugging microprocessors. Hardwarelogic that caches common JTAG scanchains improves performance. <strong>Wind</strong> <strong>River</strong><strong>ICE</strong> 2 combines this capability with ahigh-speed Gigabit Ethernet connectionand a JTAG/EJTAG/BDM interface thatprovides support for up to 100MHz clockrates.


Remote Debugging<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 offers the ability tosupport remote debugging, when yourtarget system is not located next to yourdesktop environment. With <strong>Wind</strong> <strong>River</strong><strong>ICE</strong> 2, your device can be locatedanywhere, as long as you can connect toit via a network. With its target consoleport, <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 supports remotedebugging by allowing developers tobackhaul the serial output port of thetarget device via an Ethernet connection.Scalability<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 is a scalable solutionthat enables developers to add capabilities,such as trace support, through asimple plug-in module. <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2also provides a broad range of processorsupport with easy migration from oneprocessor family to another via aninterchangeable adapter located at theend of the emulator’s target connectioncable.Target Console Port<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides a targetconsole port that provides connectivity tothe serial port on the target hardwarethrough <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2’s Ethernetinterface. The target console portbackhauls serial traffic over the networkto the developers’ desktops and transportscommands back down to the serialinterface. With the target console port,developers are able to debug remotelyand still have access to serial communicationdata coming off the target.Boot OptionsStatic BootIn this mode, a default target driver isloaded automatically when the <strong>Wind</strong><strong>River</strong> <strong>ICE</strong> 2 unit is booted. Multiple targetdrivers can also be automatically loadedat boot. The whole process is controlledby a bootapps.1st file, similar to anautoexec.bat file. This file can begenerated by the <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 unitor it can be edited on a host and copiedinto the flash file system.Dynamic BootDynamic boot is the default mode for the<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 unit. Without thebootapps.1st file, no applications areloaded. Target drivers can be loadedmanually using the Load command or byusing <strong>Wind</strong> <strong>River</strong> Workbench, whichautomatically loads the target driverrequired by the specified target in theRemote Systems Explorer view.Additional Custom RegistersThe <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 unit supports 32custom register groups, with a total of960 custom registers.<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 Firmware UpdateEmulation<strong>ICE</strong> 2 can be updated with new firmwarevia the Firmware Update Utility in <strong>Wind</strong><strong>River</strong> Workbench. After the update, theunit defaults the updated firmware tostatic boot.<strong>Wind</strong> <strong>River</strong> TechnologiesJTAG ServerThe majority of CPUs available todaymake use of the JTAG scan chain to offeraccess to core components that enablecontrol and configuration of the CPU fordebugging. Access through the JTAGscan chain provides visibility and controlof internal processor resources (hardwarebreakpoints and registers) as well asexternal memory to allow users todownload code or program Flash.<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2, coupled with <strong>Wind</strong><strong>River</strong>’s JTAG Server technology, allowsdevelopers to control all the devices thatexist in the scan chain via a single tool.With a single interface, this systemeliminates the need to separate the scanchain and use precious board real estatefor additional JTAG access headers.Fewer headers also means reducedrouting complexity and increased boardyield rate.Within the scan chain, <strong>Wind</strong> <strong>River</strong>’sleading-edge tools provide the capabilityto simultaneously or individually debugcode on one or more CPUs or coresembedded within a SoC. <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong>2 also supports multiple debug sessionsrunning on one or more hostssimultaneously.<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 High-Performance JTAG<strong>Wind</strong> <strong>River</strong>’s JTAG Accelerator technologyenables <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 to incorporatemaximum scheduling efficiency, yielding100 percent use of the available JTAGscan chain communication bandwidth.<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 eliminates slowdownload times and slow user responseto user-run control commands (step in,step out, and single step) whendeveloping with on-chip debuggermicroprocessors. With our new hardwarelogic that optimizes JTAG scan chaincommunications, <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2dramatically improves performance indevelopment.Related Products<strong>Wind</strong> <strong>River</strong> Workbench<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 is fully compatible with<strong>Wind</strong> <strong>River</strong> Workbench, the industryleadingopen and extensibledevelopment suite. <strong>Wind</strong> <strong>River</strong>Workbench On-Chip Debugging isspecifically configured to meet the needsof developers early in the device softwaredevelopment cycle—handling initialboard bring-up and validation,developing device drivers, incorporatinglow-level software capabilities, anddeveloping C/C++ applications. Thisedition offers a feature-rich developmentsuite optimized for the capabilities ofJTAG-based debugging using <strong>Wind</strong> <strong>River</strong><strong>ICE</strong> 2 and <strong>Wind</strong> <strong>River</strong> Probe.<strong>Wind</strong> <strong>River</strong> Trace 2The <strong>Wind</strong> <strong>River</strong> Trace 2 external tracemodule extends the capability of <strong>Wind</strong><strong>River</strong> <strong>ICE</strong> 2 to include real-time tracecapability for supported processors andprovide better visibility into hardware/software interaction on the targetplatform. This enables developers toidentify and resolve the most difficultprogram-flow problems such as whensoftware is randomly crashing the targetor when the root cause is not easilyfound using standard system-leveldebugging methods via register andmemory access. Benefits include thefollowing:1GB trace buffer for storage of instructionsand timestamp informationAbility to capture real-time trace atclock speeds up to 200MHzIntegration with <strong>Wind</strong> <strong>River</strong> Workbenchfor program-flow monitoring and userspecifiedtrace configuration and eventfilteringFast hardware-based buffer postprocessingto enable efficient viewing,analysis, and navigation of traceinformation


Figure 3: <strong>Wind</strong> <strong>River</strong> Trace 2Figure 2: <strong>Wind</strong> <strong>River</strong> Workbench GUI<strong>Wind</strong> <strong>River</strong> Connect 2<strong>Wind</strong> <strong>River</strong> Connect enables developersto connect multiple processors, scanchains, and boards by tying the individualscan chains associated with each processortogether onto one continuous scanchain. This process requires complexdebugging tools, but it allows developersto simultaneously stop and start theprocessor’s program execution, synchronouslyrestarting the processors as wellas reading their internal registers andmemory contents.<strong>Wind</strong> <strong>River</strong> Connect provides a unit totake uncommon JTAG scan chains andconcatenate up to four independent scanchains together onto a common scanchain.Features include the following:Connection of up to four independentscan chains to a single <strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2Scan chains that can each run at theirown voltage levels, from 1.65V to 3.3VIntegrated with <strong>Wind</strong> <strong>River</strong> WorkbenchOn-Chip Debugging 3.2 and higherversions<strong>Wind</strong> <strong>River</strong> On-Chip Debugging API<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 is fully integrated withthe <strong>Wind</strong> <strong>River</strong> On-Chip Debugging API,allowing fast and flexible integration of<strong>ICE</strong> 2’s powerful capabilities into yourown custom environment (e.g., automatedtest and production application).<strong>Wind</strong> <strong>River</strong> On-Chip Debugging APIcomes with complete and intuitivedocumentation, so developers can takefull advantage of its features andbenefits.Technical SpecificationsHost OS Support*Fedora Core 13, 32-bit x86 and 64-bitx86-64Red Hat Enterprise Linux Workstation 6(Update 1), 32-bit x86 and 64-bit x86-64Red Hat Enterprise Linux Workstation5.0–5.7, 32-bit x86 and 64-bit x86-64Red Hat Enterprise Linux Workstation 4(Update 9), 32-bit x86Ubuntu Desktop 10.04, 32-bit x86-32and 64-bit x86-64SUSE Linux Enterprise Desktop 11.0,32-bit x86-32 and 64-bit, x86-64OpenSUSE 11.2, 32-bit x86-32 and64-bit x86-64Solaris 10, 32-bit SPARC/GTK**<strong>Wind</strong>ows XP Professional with ServicePack 3, 32-bit x86<strong>Wind</strong>ows 7 with Service Pack 1, 32-bitx86 and 64-bit x86*When used with <strong>Wind</strong> <strong>River</strong> Workbench On-ChipDebugging 3.3.2 or <strong>Wind</strong> <strong>River</strong> On-Chip DebuggingAPI 3.9.6**<strong>Wind</strong> <strong>River</strong> Probe is not supported on Solaris hosts.Figure 4: <strong>Wind</strong> <strong>River</strong> Trace 2 configuration and debug interface


Target OS Support<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 provides support for thefollowing target operating systems:VxWorks 6.3 and higherVxWorks 653VxWorks MILSVxWorks CertVxWorks 5.5<strong>Wind</strong> <strong>River</strong> LinuxOpen source Linux kernels versions2.6.x.<strong>Wind</strong> <strong>River</strong> Hypervisor 1.3.1UEFI-compliant BIOS and boot loaders(Intel architecture)Customizable target OS awarenesscapability for <strong>Wind</strong> <strong>River</strong> WorkbenchOn-Chip Debugging enables support forother target operating systems.Supported ArchitecturesSupport for specific processors varies byWorkbench On-Chip Debugging versionand specific JTAG debug unit. Fordetails on currently supportedprocessors, refer to the processorsupport matrix at www.windriver.com/products/OCD/. <strong>Wind</strong> <strong>River</strong> is continuallyadding new processor support. Ifyou do not see your processor listed,contact your <strong>Wind</strong> <strong>River</strong> salesrepresentative.<strong>Wind</strong> <strong>River</strong> <strong>ICE</strong> 2 Processor Family SupportARMARM9ARM11ARM Cortex-A8ARM Cortex-A9*ARM CoreTile Express A9x4ARM Cortex-M3ST Micro SPEAr1310ATMEL AT9x*Cavium Econa*Freescale i.MX*Marvell*TI OMAP*ColdFireMCF52xxMCF53xxMCF54xxMCF544xxIntel ArchitectureIntel Atom*Intel Core 2* DuoIntel Core i3*Intel Core i5*Intel Core i7*Intel Xeon*MIPSMIPS 4Kc, 4Km, 4Kp, 4KEcMIPS 5Kc, 5KfMIPS 20KcMIPS 24kc, 24kfMIPS (continued)MIPS 25KfMIPS 74k*Broadlight BL23570RAltera MP32*Broadcom BCM11xx*, BCM12xx*,BCM14xx*Broadcom BCM33xx*, BCM35xx*Broadcom BCM47xx*Broadcom BCM5300xBroadcom BCM53xx*, BCM5621x*,BCM58xx*Broadcom BCM63xx*, BCM65xx*Broadcom BCM70xx*, BCM71xx*Broadcom BCM73xx*, BCM74xx*Cavium OCTEON CN3xxx*Cavium OCTEON Plus CN5xxx*Cavium OCTEON 2 CN6xxx*NEC VR41xx*, VR54xx*, VR55xx*,VR77xx*NetLogic (RMI) AU1x00* (formerly AMDAlchemy)NetLogic (RMI) XLR*, XLS*Philips PR19xx*, PR39xx*, PR44xx*Philips PNX30xx*, PNX73xx*,Philips PNX83xx*, PNX85xx*PMC-Sierra RM79xx*, RM9xxx*Toshiba TX49xx*Wintegra Winpath*Power Architecture (PowerPC)AMCC PPC403*AMCC PPC405*AMCC PPC440*AMCC PPC460*CPU Tech Acalis CPU872LSI Axxia ACP3442LSI Axxia ACP3448Freescale PPC5xx*Freescale MPC512x*Freescale MPC52xx*Freescale MPC55xx*, MPC56xx*Freescale/IBM PPC6xx*Freescale/IBM PPC7xx*Freescale MPC74xx*Freescale MPC8xx*Freescale MPC82xx*Freescale MPC83xx*Freescale MPC85xx*Freescale MPC86xx*Freescale QorIQ P1xxx*Freescale QorIQ P2xxx*Freescale QorIQ P3xxx*Freescale QorIQ P4080*Freescale QorIQ P5xxx*P.A. Semi PA6T-1682MST Microelectronics SPC560xxx*Xilinx Virtex-II Pro X2VP*Xilinx Virtex-4 XC4V**Specific processors only; for details on currently supported processors, refer to the processor support matrix atwww.windriver.com/products/OCD/. If you do not see your processor listed, contact your <strong>Wind</strong> <strong>River</strong> sales representative.<strong>Embedded</strong> <strong>Tools</strong>, Ihr langjähriger Partner für alle <strong>Wind</strong> <strong>River</strong> Entwicklungswerkzeuge<strong>Wind</strong> <strong>River</strong>-Compiler, -Workbench, -Probe, -<strong>ICE</strong>, -<strong>ICE</strong>2

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