WEARABLE/IMPLANTABLE

SESSION 19
Wednesday February 3 rd , 8:30 AM
Digital PLLs
Session Chair: John Maneatis, True Circuits, Mountain View, CA
Associate Chair: Kathy Wilcox, AMD, Boxborough, MA
8:30 AM
19.1 A 0.5-to-9.5GHz 1.2µs-Lock-Time Fractional-N DPLL with ±1.25% UI
Period Jitter in 16nm CMOS For Dynamic Frequency and Core-Count
Scaling in SoC
F. Ahmad, G. Unruh, A. Iyer, P-E. Su, S. Abdalla, B. Shen, M. Chambers, I. Fujimori
Broadcom, Irvine, CA
9:00 AM
19.2 A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with
Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing
Mismatch Detection
S. Kundu 1 , B. Kim 2 , C. H. Kim 1
1
University of Minnesota, Minneapolis, MN
2
Rambus, Sunnyvale, CA
9:30 AM
19.3 A 2.4GHz 1.5mW Digital MDLL Using Pulse-Width Comparator and
Double Injection Technique in 28nm CMOS
H. Kim 1,2 , Y. Kim 1 , T. Kim 2 , H. Park 2 , S. Cho 1
1
KAIST, Daejeon, Korea
2
Samsung Electronics, Hwaseong, Korea
Break 10:00 AM
10:15 AM
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB Built-In Supply
Noise Rejection and Self-Bandwidth Control in 14nm CMOS
K-Y. J. Shen, S. F. Syed Farooq, Y. Fan, K. M. Nguyen, Q. Wang, A. Elshazly, N. Kurd
Intel, Hillsboro, OR
10:45 AM
19.5 A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise
Cancellation
C-W. Yeh, C-E. Hsieh, S-I. Liu
National Taiwan University, Taipei, Taiwan
11:00 AM
19.6 Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking
Implementation of a 0.7-to-1.2V DVFS System
F. U. Rahman, V. S. Sathe
University of Washington, Seattle, WA
11:15 AM
19.7 A 65nm CMOS ADPLL with 360μW 1.6ps-INL SS-ADC-Based Period-
Detection-Free TDC
A. Sai, S. Kondo, T. T. Ta, H. Okuni, M. Furuta, T. Itakura
Toshiba, Kawasaki, Japan
11:45 AM
19.8 A 0.0021mm 2 1.82mW 2.2GHz PLL Using Time-Based Integral
Control in 65nm CMOS
J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S-J. Kim, P. K. Hanumolu
University of Illinois, Urbana-Champaign, IL
Conclusion 12:15 PM
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