Design Checklist for PowerQUICC II Pro MPC8313E Processor

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JTAG and Debug From Target Board Sources (if any) 1 2 3 5 7 9 11 13 15 4 6 8 10 12 KEY No pin 16 COP Connector Physical Pin Out COP Header PORESET SRESET HRESET HRESET 13 11 4 6 1 5 15 14 2 8 9 1 3 7 2 10 12 16 HRESET SRESET TRST VDD_SENSE NC CHKSTP_OUT CHKSTP_IN TMS TDO TDI TCK NC NC NC Figure 6. COP Connections to PowerQUICC II Pro Design Checklist for PowerQUICC II Pro MPC8313E Processor, Rev. 3 SRESET 16 Freescale Semiconductor 2 k� 10 k� 10 k� 10 k� 10 k� 10 k� 10 k� PORESET NV DD NV DD NV DD NV DD TRST NV DD CHKSTP_OUT NV DD NVDD CHKSTP_IN Notes: 1. Some systems require power to be fed from the application board into the debugger repeater card through the COP header. In this case the resistor value for VDD_SENSE should be around 20 �. 2. Key location; pin 14 is not physically present on the COP header. TMS TDO TDI TCK
This table details the termination recommendations for the JTAG, TEST, and PMC pins. Signal Pin Type TCK I As needed + 10 k� to NV DD Termination If used If not used 6 Functional Blocks Design Checklist for PowerQUICC II Pro MPC8313E Processor, Rev. 3 Functional Blocks This section presents the recommendations and guidelines for designing with various functional blocks on the PowerQUICC II Pro. 6.1 PCI Bus Interface Table 7. JTAG and TEST Pin Listing The reset configuration word high controls the hardware configuration of the PCI blocks as follows: • RCWH[PCIHOST]— Host/agent mode for PCI • RCWH[PCIARB]—PCI internal/external arbiter mode select. As shown in this table, signals of the PCI interface are multiplexed with the CompactPCI Hot Swap pins. Either PCI or Hot Swap functionality is selected by the RCWH[PCIARB] bit setting. When an external arbiter is selected (RCWH[PCIARB] = 0), the CompactPCI Hot Swap pins function. When an internal arbiter is selected (RCWH[PCIARB] = 1), the GNTx/REQx pins function. Freescale Semiconductor 17 Notes 10 k� to NV DD Commonly used for boundary scan testing. If this pin is truly not used, it can be tied directly to GND. TDI I As needed Open This JTAG pin has a weak internal pull-up P-FET that is always enabled. TDO O As needed Open Actively driven during RESET TMS I As needed Open This JTAG pin has a weak internal pull-up P-FET that is always enabled. TRST I Tie to the output of a Negative OR gate + 10 k� to NV DD Tie to PORESET through a 0 k� This JTAG pin has a weak internal pull-up P-FET that is always enabled. If an In-Circuit Emulator is used in the design, TRST should be tied to the output of a Negative OR gate logic. The inputs to the Negative OR gate logic should be any external TRST source and the PORESET signal TEST I Tie directly to GND — Test PMC QUIESCE O As needed Open —
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: 1.4 Product Revisions This table sh
Page 5 and 6: There are several reliable ways to
Page 7 and 8: 3 Clocking This figure shows the in
Page 9 and 10: 3.1 System Clock in PCI Host Mode D
Page 11 and 12: Design Checklist for PowerQUICC II
Page 15: If the JTAG interface and COP heade
Page 19 and 20: Signal PCI_PERR I/O As needed + 2 k
Page 21 and 22: 6.3 Enhanced Local Bus Controller D
Page 23 and 24: 6.3.2 NAND Flash Interface Design C
Page 27 and 28: 6.5 Integrated Programmable Interru
Page 29 and 30: Signal NOTE • eTSEC1: Pin functio
Page 31 and 32: 6.8 I 2 C Interface This table list
Page 33 and 34: Signal Pin Type 7 Revision History
Page 35 and 36: Rev. Number Design Checklist for Po

Design Checklist for PowerQUICC II Pro MPC8313E Processor

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