Design Checklist for PowerQUICC II Pro MPC8313E Processor

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Functional Blocks For details on the reset configuration word high settings, see MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual. Signal Pin Type Table 8. PCI Bus Interface Pin Listing Connection If Used If Not Used Design Checklist for PowerQUICC II Pro MPC8313E Processor, Rev. 3 18 Freescale Semiconductor Notes PCI_INTA O 2 k–10 k� to NV DD 2 k–10 k� to NV DD Open drain signal. In agent mode, INTA typically connects to a central interrupt controller. In host mode, INTA may be used to assert interrupts to other devices, such as a second processor. PCI_RESET_OUT O As needed Open This signal is used only in host mode. It should be left unconnected in agent mode. PCI_AD[31:0] I/O As needed 2 k–10 k� to NV DD or Open PCI_C/BE[3:0] I/O As needed + 2 k–10 k� to NV DD 2 k–10 k� to NV DD or Open If the PCI port is not used, no termination is needed if the bus is parked. Software needs to park the bus as follows: 1. RCWHR[PCIHOST] = 1 2. RCWHR[PCIARB] = 1 3a. PCIACR(PCI Arbiter Control Register)[PM(Parking mode)] = 1 or 3b. PCI_GCR[BBR] = 1 If the PCI port is not used, no termination is needed if the bus is parked. Software needs to park the bus as follows: 1. RCWHR[PCIHOST] = 1 2. RCWHR[PCIARB] = 1 3a. PCIACR(PCI Arbiter Control Register)[PM(Parking mode)] = 1 or 3b. PCI_GCR[BBR] = 1 PCI_PAR I/O As needed 2 k–10 k� to NV DD If the PCI port is not used, this signal must be pulled up. PCI_FRAME I/O As needed + 2 k–10 k� to NV DD PCI_TRDY I/O As needed + 2 k–10 k� to NV DD PCI_IRDY I/O As needed + 2 k–10 k� to NV DD PCI_STOP I/O As needed + 2 k–10 k� to NV DD PCI_DEVSEL I/O As needed + 2 k–10 k� to NV DD PCI_IDSEL I PCI host: Tie to GND PCI agent: One of PCI_AD[31:0] PCI_SERR I/O As needed + 2 k–10 k� to NV DD 2 k–10 k� to NV DD PCI specification requires a weak pull up. 2 k–10 k� to NV DD PCI specification requires a weak pull up. 2 k–10 k� to NV DD PCI specification requires a weak pull up. 2 k–10 k� to NV DD PCI specification requires a weak pull up. 2 k–10 k� to NV DD PCI specification requires a weak pull up. 4.7 k� to GND IDSEL should be connected to GND for host systems and to one address line for agent systems. If the PCI port is not used, it should be grounded. • PCI host is selected by RCWH[PCIHOST] = 1. • PCI agent is selected by RCWH[PCIHOST] = 0. 2 k–10 k� to NV DD PCI specification requires a weak pull up.
Signal PCI_PERR I/O As needed + 2 k–10 k� to NV DD PCI_REQ0 I/O External arbiter: As needed PCI_REQ1/ CPCI_HS_ES Internal arbiter: As needed + 2 k–10 k� to NV DD I External arbiter: As needed Internal arbiter: As needed + 2 k–10 k� to NV DD PCI_REQ[0:2] I As needed + 2 k–10 k� to NV DD PCI_GNT0 I/O External arbiter: As needed + 2 k–10 k� to NV DD PCI_GNT1/ CPCI_HS_LED PCI_GNT2/ CPCI_HS_ENUM Pin Type Internal arbiter: As needed 2 k–10 k� to NV DD PCI specification requires a weak pull up. External arbiter: Open Internal arbiter: 2 k–10 k� to NV DD Design Checklist for PowerQUICC II Pro MPC8313E Processor, Rev. 3 Functional Blocks If an external arbiter is used, REQ0 becomes an output signal and does not need to be terminated. • External arbiter selected by RCWH[PCIARB] = 0. • Internal arbiter selected by RCWH[PCIARB] = 1. 2 k–10 k� to NV DD This pin is multiplexed with a CompactPCI Hot Swap function. CompactPCI functionality selected when external arbiter is used. • External arbiter selected by RCWH[PCIARB] = 0. • Internal arbiter selected by RCWH[PCIARB] = 1. 2 k–10 k� to NV DD External arbiter: 2 k–10 k� to NV DD Internal arbiter: Open Freescale Semiconductor 19 — If an external arbiter is used, GNT0 becomes an input signal and should be pulled up with 2 k–10 k� to NV DD. • External arbiter selected by RCWH[PCIARB] = 0. • Internal arbiter selected by RCWH[PCIARB] = 1. O As needed Open This pin is multiplexed with a CompactPCI Hot Swap function. CompactPCI functionality selected when external arbiter is used. • External arbiter selected by RCWH[PCIARB] = 0. • Internal arbiter selected by RCWH[PCIARB] = 1. O External arbiter: As needed + 2 k–10 k� to NV DD Table 8. PCI Bus Interface Pin Listing (continued) Internal arbiter: As needed Connection If Used If Not Used External arbiter: Open Internal arbiter: Open M66EN I As needed 5 k� to NV DD or 1k� to GND Notes This pin is multiplexed with a CompactPCI Hot Swap function. CompactPCI functionality selected when external arbiter is used. • If CompactPCI Hot Swap function is used, a weak pullup is required (2 k–10 k� to NV DD ). • External arbiter selected by RCWH[PCIARB] = 0. • Internal arbiter selected by RCWH[PCIARB] = 1. Open-drain signal. No role if PCI is not used. PCI_PME I/O As needed 4.7 k� to NV DD Internal pull-up present on this pin.
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: 1.4 Product Revisions This table sh
Page 5 and 6: There are several reliable ways to
Page 7 and 8: 3 Clocking This figure shows the in
Page 9 and 10: 3.1 System Clock in PCI Host Mode D
Page 11 and 12: Design Checklist for PowerQUICC II
Page 15 and 16: If the JTAG interface and COP heade
Page 17: This table details the termination
Page 21 and 22: 6.3 Enhanced Local Bus Controller D
Page 23 and 24: 6.3.2 NAND Flash Interface Design C
Page 27 and 28: 6.5 Integrated Programmable Interru
Page 29 and 30: Signal NOTE • eTSEC1: Pin functio
Page 31 and 32: 6.8 I 2 C Interface This table list
Page 33 and 34: Signal Pin Type 7 Revision History
Page 35 and 36: Rev. Number Design Checklist for Po

Design Checklist for PowerQUICC II Pro MPC8313E Processor

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