Design Checklist for PowerQUICC II Pro MPC8313E Processor

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Power 2.7 Pin Listing and Connections This table summarizes the power signal pins. Signal Pin Type MPC8313E MPC8313 Table 2. Power Signal Pin Listing Connection Notes AV DD1 — X X 1.0 V ± 50 mV Power for e300 PLL AV DD2 — X X 1.0 V ± 50 mV Power for system PLL SDAV DD — X X 1.0 V ± 50 mV Power for Serdes PLL USB_PLL_PWR1 — X X 1.0 V ± 50 mV Power for USB PLL USB_PLL_PWR3 — X X 3.3 V ± 330mV Power for USB PLL USB_VDDA — X X 3.3 V ± 330mV Power for USB transceiver USB_VDDA_BIAS — X X 3.3 V ± 330mV Power for USB BIAS circuit GV DD — X X 2.5 V ± 125 mV 1.8 V ± 80mV LV DDA — X X 2.5 V ± 125 mV 3.3 V ± 330 mV LV DDB — X X 2.5 V ± 125 mV 3.3 V ± 330 mV Power for DDR I/O voltage Power for eTSEC2 Power for eTSEC1/ USBDR I/O LV DD — X X 3.3 V ± 330mV Power for eLBC I/O V DDC — X X 1.0 V ± 50 mV Power for the core. Continuos power V DD — X X 1.0 V ± 50 mV Power for the core. Switchable power NV DD — X X 3.3 V ± 330 mV Power supply for PCI, I 2 C, SPI, and other standard I/Os. MVREF[1:2] I X X 0.49 x GV DD to 0.51 x GV DD DDR reference voltage NOTE • LV DDA and LV DDB can be powered from different I/O voltage supplies • For MII and RMII operations, LV DDA and LV DDB should be tied to 3.3 V • For RGMII and RTBI operations, LV DDA and LV DDB can be at 2.5 V or 3.3 V • For DDR1, GV DD should be tied to 2.5 V • For DDR2, GV DD should be tied to 1.8 V • Core power V DD can be switched off during power down mode • All the power supply pins should be connected to their respective voltage even if they are not being used. • All the I/Os should be interfaced with peripherals operating at same voltage levels. Design Checklist for PowerQUICC II Pro MPC8313E Processor, Rev. 3 6 Freescale Semiconductor
3 Clocking This figure shows the internal distribution of clocks within the MPC8313E. USB_CLK_IN USB_CR_CLK_IN Crystal USB_CR_CLK_OUT CFG_CLKIN _DIV SYS_CLK_IN SYS_CR_CLK_IN Crystal SYS_CR_CLK_OUT GTX_CLK125 25-/125-MHz Source SD_REF_CLK/ SD_REF_CLK 125-MHz Source 1 4.7 k��pull-down if not used. MPC8313E USB Mac USB PHY PLL eTSEC Protocol Converter SGMII PHY Interface PLL mux /1,/2 System PLL e300c3 core csb_clk Clock Unit PCI Clock Divider (�2) PMC Core PLL ddr_clk lbc_clk to DDR memory controller core_clk To local bus LBC Clock Divider csb_clk to rest of the device DDR Clock Divider /2 Figure 3. Clock Subsystem Block Diagram Design Checklist for PowerQUICC II Pro MPC8313E Processor, Rev. 3 LCLK[0:1] PCI_CLK/ PCI_SYNC_IN PCI_CLK[0:2] Clocking Local Bus Memory Device PCI_SYNC_OUT Freescale Semiconductor 7 /n 1 0 Sys Ref RTC 3 MEMC_MCK MEMC_MCK RTC_PIT_CLOCK 1 (32 KHz) DDR Memory Device
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: 1.4 Product Revisions This table sh
Page 5: There are several reliable ways to
Page 9 and 10: 3.1 System Clock in PCI Host Mode D
Page 11 and 12: Design Checklist for PowerQUICC II
Page 15 and 16: If the JTAG interface and COP heade
Page 17 and 18: This table details the termination
Page 19 and 20: Signal PCI_PERR I/O As needed + 2 k
Page 21 and 22: 6.3 Enhanced Local Bus Controller D
Page 23 and 24: 6.3.2 NAND Flash Interface Design C
Page 27 and 28: 6.5 Integrated Programmable Interru
Page 29 and 30: Signal NOTE • eTSEC1: Pin functio
Page 31 and 32: 6.8 I 2 C Interface This table list
Page 33 and 34: Signal Pin Type 7 Revision History
Page 35 and 36: Rev. Number Design Checklist for Po

Design Checklist for PowerQUICC II Pro MPC8313E Processor

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