Reveal Troubleshooting Guide - Lattice Semiconductor

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Contents REveal Troubleshooting Guide 2
HDL Language Restrictions Reveal Troubleshooting Guide This document describes the design restrictions for using on-chip debug. The following features are valid in the VHDL and Verilog languages but are not supported in the Reveal Inserter when you use the RTL flow: � Array types of two dimensions or more are not shown in the port or node section. � Undeclared wires attached to instantiated component instances are not shown in the hierarchical design tree. You must declare these wires explicitly if you want to trace or trigger with them. � Variables used in generate statements are not available for tracing and triggering. � Variables used in conditional statements like if-then-else statements are not available for tracing and triggering. � Variables used in selection statements like the case statement are not available for tracing and triggering. � If function calls are used in the array declaration, the actual size of the array is unknown to the Reveal Inserter. � Entity and architecture of the same design cannot be in different files. The following types are valid in the VHDL language but are not supported in the Reveal Inserter when you use the RTL flow: � Integer types � Boolean types Reveal Troubleshooting Guide 1
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Page 3 and 4: latest version of the relevant info
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Reveal Troubleshooting Guide - Lattice Semiconductor

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